WO2006026526A3 - Memory system and method for strobing data, command and address signals - Google Patents

Memory system and method for strobing data, command and address signals Download PDF

Info

Publication number
WO2006026526A3
WO2006026526A3 PCT/US2005/030593 US2005030593W WO2006026526A3 WO 2006026526 A3 WO2006026526 A3 WO 2006026526A3 US 2005030593 W US2005030593 W US 2005030593W WO 2006026526 A3 WO2006026526 A3 WO 2006026526A3
Authority
WO
WIPO (PCT)
Prior art keywords
command
memory device
memory controller
data signals
memory
Prior art date
Application number
PCT/US2005/030593
Other languages
French (fr)
Other versions
WO2006026526A2 (en
Inventor
Feng Lin
Brent Keeth
Brian Johnson
Seong-Hoon Lee
Original Assignee
Micron Technology Inc
Feng Lin
Brent Keeth
Brian Johnson
Seong-Hoon Lee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Feng Lin, Brent Keeth, Brian Johnson, Seong-Hoon Lee filed Critical Micron Technology Inc
Priority to JP2007528103A priority Critical patent/JP2008511061A/en
Priority to EP05794172A priority patent/EP1784833A4/en
Publication of WO2006026526A2 publication Critical patent/WO2006026526A2/en
Publication of WO2006026526A3 publication Critical patent/WO2006026526A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Abstract

A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.
PCT/US2005/030593 2004-08-31 2005-08-26 Memory system and method for strobing data, command and address signals WO2006026526A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007528103A JP2008511061A (en) 2004-08-31 2005-08-26 Memory system and method for strobing data, command and address signals
EP05794172A EP1784833A4 (en) 2004-08-31 2005-08-26 Memory system and method for strobing data, command and address signals

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/931,472 2004-08-31
US10/931,472 US7126874B2 (en) 2004-08-31 2004-08-31 Memory system and method for strobing data, command and address signals

Publications (2)

Publication Number Publication Date
WO2006026526A2 WO2006026526A2 (en) 2006-03-09
WO2006026526A3 true WO2006026526A3 (en) 2006-05-04

Family

ID=35942828

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/030593 WO2006026526A2 (en) 2004-08-31 2005-08-26 Memory system and method for strobing data, command and address signals

Country Status (5)

Country Link
US (5) US7126874B2 (en)
EP (1) EP1784833A4 (en)
JP (1) JP2008511061A (en)
KR (1) KR100867282B1 (en)
WO (1) WO2006026526A2 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7126874B2 (en) * 2004-08-31 2006-10-24 Micron Technology, Inc. Memory system and method for strobing data, command and address signals
US7490208B1 (en) * 2004-10-05 2009-02-10 Nvidia Corporation Architecture for compact multi-ported register file
US7428284B2 (en) * 2005-03-14 2008-09-23 Micron Technology, Inc. Phase detector and method providing rapid locking of delay-lock loops
DE102005019041B4 (en) * 2005-04-23 2009-04-16 Qimonda Ag Semiconductor memory and method for adjusting the phase relationship between a clock signal and strobe signal in the acquisition of transferable write data
US7512201B2 (en) * 2005-06-14 2009-03-31 International Business Machines Corporation Multi-channel synchronization architecture
JP4786262B2 (en) * 2005-09-06 2011-10-05 ルネサスエレクトロニクス株式会社 Interface circuit
US8121237B2 (en) 2006-03-16 2012-02-21 Rambus Inc. Signaling system with adaptive timing calibration
TWI302320B (en) * 2006-09-07 2008-10-21 Nanya Technology Corp Phase detection method, memory control method, and related device
US7715251B2 (en) * 2006-10-25 2010-05-11 Hewlett-Packard Development Company, L.P. Memory access strobe configuration system and process
US20110264851A1 (en) * 2006-12-07 2011-10-27 Tae-Keun Jeon Memory system and data transmitting method thereof
US7688652B2 (en) * 2007-07-18 2010-03-30 Mosaid Technologies Incorporated Storage of data in memory via packet strobing
US8051320B2 (en) 2007-12-12 2011-11-01 Mips Technologies, Inc. Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof
US8289760B2 (en) 2008-07-02 2012-10-16 Micron Technology, Inc. Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
KR101079209B1 (en) * 2010-04-28 2011-11-03 주식회사 하이닉스반도체 Data input/output apparatus and method of semiconductor system
US8533538B2 (en) * 2010-06-28 2013-09-10 Intel Corporation Method and apparatus for training a memory signal via an error signal of a memory
KR101188264B1 (en) 2010-12-01 2012-10-05 에스케이하이닉스 주식회사 Semiconductor System, Semiconductor Memory Apparatus, and Method for Input/Output of Data Using the Same
WO2012078341A1 (en) * 2010-12-09 2012-06-14 Rambus Inc. Memory components and controllers that utilize multiphase synchronous timing references
US8400808B2 (en) 2010-12-16 2013-03-19 Micron Technology, Inc. Phase interpolators and push-pull buffers
KR101819664B1 (en) * 2011-02-07 2018-03-02 엘지디스플레이 주식회사 Timing controller and liquid crystal display using the same
JP2012205100A (en) * 2011-03-25 2012-10-22 Toshiba Corp Memory system, memory controller and synchronization device
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US9190132B2 (en) * 2012-11-14 2015-11-17 Broadcom Corporation Reducing signal skew in memory and other devices
US9171597B2 (en) * 2013-08-30 2015-10-27 Micron Technology, Inc. Apparatuses and methods for providing strobe signals to memories
US9368172B2 (en) * 2014-02-03 2016-06-14 Rambus Inc. Read strobe gating mechanism
US9478268B2 (en) * 2014-06-12 2016-10-25 Qualcomm Incorporated Distributed clock synchronization
KR20170008062A (en) * 2015-07-13 2017-01-23 에스케이하이닉스 주식회사 Memory apparatus performing training operation and memory system using the same
US10727824B2 (en) * 2018-02-01 2020-07-28 SK Hynix Inc. Strobe generation circuit and semiconductor device including the same
KR20190093293A (en) 2018-02-01 2019-08-09 에스케이하이닉스 주식회사 Serializer and semiconductor system including the same
US10339998B1 (en) 2018-03-27 2019-07-02 Micron Technology, Inc. Apparatuses and methods for providing clock signals in a semiconductor device
US10388362B1 (en) * 2018-05-08 2019-08-20 Micron Technology, Inc. Half-width, double pumped data path
US10418081B1 (en) * 2018-10-10 2019-09-17 Micron Technology, Inc. Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed
KR102538706B1 (en) * 2019-01-08 2023-06-02 에스케이하이닉스 주식회사 Semiconductor device
WO2020176448A1 (en) 2019-02-27 2020-09-03 Rambus Inc. Low power memory with on-demand bandwidth boost

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5896347A (en) * 1996-12-27 1999-04-20 Fujitsu Limited Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same
US6167495A (en) * 1998-08-27 2000-12-26 Micron Technology, Inc. Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories
US6918046B2 (en) * 2000-06-30 2005-07-12 Hynix Semiconductor, Inc. High speed interface device for reducing power consumption, circuit area and transmitting/receiving a 4 bit data in one clock period

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
DE2855118C2 (en) * 1978-12-20 1981-03-26 IBM Deutschland GmbH, 70569 Stuttgart Dynamic FET memory
US5471607A (en) * 1993-04-22 1995-11-28 Analog Devices, Inc. Multi-phase multi-access pipeline memory system
KR100190373B1 (en) * 1996-02-08 1999-06-01 김영환 High-speed dynamic memory device for read pass
US6073204A (en) * 1997-04-23 2000-06-06 Micron Technology, Inc. Memory system having flexible architecture and method
JP3703241B2 (en) * 1997-01-28 2005-10-05 Ｎｅｃエレクトロニクス株式会社 Semiconductor memory device
US6243797B1 (en) * 1997-02-18 2001-06-05 Micron Technlogy, Inc. Multiplexed semiconductor data transfer arrangement with timing signal generator
US5831929A (en) * 1997-04-04 1998-11-03 Micron Technology, Inc. Memory device with staggered data paths
US5974499A (en) * 1997-04-23 1999-10-26 Micron Technology, Inc. Memory system having read modify write function and method
US6175891B1 (en) * 1997-04-23 2001-01-16 Micron Technology, Inc. System and method for assigning addresses to memory devices
US6021459A (en) * 1997-04-23 2000-02-01 Micron Technology, Inc. Memory system having flexible bus structure and method
JP3420018B2 (en) * 1997-04-25 2003-06-23 株式会社東芝 Data receiver
US5959935A (en) * 1997-05-30 1999-09-28 Sgs-Thomson Microelectronics S.R.L. Synchronization signal generation circuit and method
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
JP3929116B2 (en) * 1997-07-04 2007-06-13 富士通株式会社 Memory subsystem
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6111446A (en) * 1998-03-20 2000-08-29 Micron Technology, Inc. Integrated circuit data latch driver circuit
US6069506A (en) * 1998-05-20 2000-05-30 Micron Technology, Inc. Method and apparatus for improving the performance of digital delay locked loop circuits
JP2000076853A (en) * 1998-06-17 2000-03-14 Mitsubishi Electric Corp Synchronous semiconductor storage
US6338127B1 (en) * 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
KR100575860B1 (en) 1999-06-28 2006-05-03 주식회사 하이닉스반도체 Data input control circuit in synchronous memory device
KR100343139B1 (en) * 1999-11-22 2002-07-05 윤종용 Data synchronizing circuit
US6518794B2 (en) * 2000-04-24 2003-02-11 International Business Machines Corporation AC drive cross point adjust method and apparatus
US6445231B1 (en) 2000-06-01 2002-09-03 Micron Technology, Inc. Digital dual-loop DLL design using coarse and fine loops
US6807613B1 (en) * 2000-08-21 2004-10-19 Mircon Technology, Inc. Synchronized write data on a high speed memory bus
KR100382736B1 (en) * 2001-03-09 2003-05-09 삼성전자주식회사 Semiconductor memory device having different data rates in read operation and write operation
US6487141B2 (en) * 2001-03-15 2002-11-26 Micron Technology, Inc. Digital delay, digital phase shifter
JP2002324398A (en) * 2001-04-25 2002-11-08 Mitsubishi Electric Corp Semiconductor memory device, memory system and memory module
JP2003068077A (en) * 2001-08-28 2003-03-07 Mitsubishi Electric Corp Semiconductor memory
KR100403635B1 (en) * 2001-11-06 2003-10-30 삼성전자주식회사 Data input circuit and data input method for synchronous semiconductor memory device
US6646929B1 (en) * 2001-12-05 2003-11-11 Lsi Logic Corporation Methods and structure for read data synchronization with minimal latency
US6496043B1 (en) * 2001-12-13 2002-12-17 Lsi Logic Corporation Method and apparatus for measuring the phase of captured read data
US6952123B2 (en) * 2002-03-22 2005-10-04 Rambus Inc. System with dual rail regulated locked loop
TWI256542B (en) 2002-03-22 2006-06-11 Via Tech Inc Data latch time control method and device
US7003686B2 (en) 2002-05-20 2006-02-21 Hitachi Ltd. Interface circuit
KR100477809B1 (en) * 2002-05-21 2005-03-21 주식회사 하이닉스반도체 Digital dll apparatus for correcting duty cycle and method thereof
US6600681B1 (en) * 2002-06-10 2003-07-29 Lsi Logic Corporation Method and apparatus for calibrating DQS qualification in a memory controller
FR2847078B1 (en) * 2002-11-12 2005-02-18 Thales Sa DEVICE FOR REDUCING PHASE NOISE
US6940768B2 (en) * 2003-11-04 2005-09-06 Agere Systems Inc. Programmable data strobe offset with DLL for double data rate (DDR) RAM memory
KR100596435B1 (en) * 2003-12-17 2006-07-05 주식회사 하이닉스반도체 Semiconductor memory device for reducing address access time
US7084686B2 (en) * 2004-05-25 2006-08-01 Micron Technology, Inc. System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US7042260B2 (en) 2004-06-14 2006-05-09 Micron Technology, Inc. Low power and low timing jitter phase-lock loop and method
US7126874B2 (en) * 2004-08-31 2006-10-24 Micron Technology, Inc. Memory system and method for strobing data, command and address signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5896347A (en) * 1996-12-27 1999-04-20 Fujitsu Limited Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same
US6167495A (en) * 1998-08-27 2000-12-26 Micron Technology, Inc. Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories
US6918046B2 (en) * 2000-06-30 2005-07-12 Hynix Semiconductor, Inc. High speed interface device for reducing power consumption, circuit area and transmitting/receiving a 4 bit data in one clock period

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1784833A4 *

Also Published As

Publication number Publication date
US7269094B2 (en) 2007-09-11
US7251194B2 (en) 2007-07-31
JP2008511061A (en) 2008-04-10
EP1784833A4 (en) 2008-10-15
US20060044891A1 (en) 2006-03-02
US7187617B2 (en) 2007-03-06
US20060140023A1 (en) 2006-06-29
US20060143491A1 (en) 2006-06-29
WO2006026526A2 (en) 2006-03-09
KR100867282B1 (en) 2008-11-10
US20060126406A1 (en) 2006-06-15
KR20070049241A (en) 2007-05-10
EP1784833A2 (en) 2007-05-16
US7245553B2 (en) 2007-07-17
US7126874B2 (en) 2006-10-24
US20060133165A1 (en) 2006-06-22

Similar Documents

Publication Publication Date Title
WO2006026526A3 (en) Memory system and method for strobing data, command and address signals
TWI257099B (en) Integrated circuit device for providing selectively variable write latency and method thereof
JP2009510568A5 (en)
GB2458040A (en) Memory controller including a dual-mode memory interconnect
EP1818941A3 (en) Semiconductor memory and data access method
TW200632927A (en) Memory circuit
JP5590605B2 (en) Memory device control for self-refresh mode
WO2007008324A3 (en) High-speed interface for high-density flash with two levels of pipelined cache
WO2006121874A3 (en) Memory device and method having a data bypass path to allow rapid testing and calibration
JP2008226423A5 (en)
ATE363715T1 (en) MEMORY MODULE WITH MULTIFUNCTIONAL STROBE CONNECTIONS
TW200723296A (en) Data input circuit of semiconductor memory device and data input method thereof
TW200639875A (en) Configuration of memory device
JP2006114192A (en) Data output compression circuit for testing cell in bank and its method
US8483005B2 (en) Internal signal generator for use in semiconductor memory device
US9530465B2 (en) Semiconductor memory device
WO2005038637A3 (en) Well-matched echo clock in memory system
US20130279271A1 (en) Pipe register circuit and semiconductor memory apparatus having the same
US7345930B2 (en) Write circuit of memory device
KR20160075006A (en) Column control signal generating circuit of semiconductor memory device
TW349226B (en) A test method of high speed memory devices in which limit conditions for the clock signals are defined
US20150048870A1 (en) Semiconductor device, semiconductor system including the same, and method for operating the same
WO2007115326A3 (en) Apparatus and methods for handling requests over an interface
US7499371B2 (en) Semiconductor memory system with a variable and settable preamble f
US20100165760A1 (en) Data strobe signal noise protection apparatus and semiconductor integrated circuit

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2005794172

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2007528103

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020077007422

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2005794172

Country of ref document: EP