WO2006033746A3 - Method of forming a semiconductor device having a metal layer - Google Patents

Method of forming a semiconductor device having a metal layer Download PDF

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Publication number
WO2006033746A3
WO2006033746A3 PCT/US2005/029772 US2005029772W WO2006033746A3 WO 2006033746 A3 WO2006033746 A3 WO 2006033746A3 US 2005029772 W US2005029772 W US 2005029772W WO 2006033746 A3 WO2006033746 A3 WO 2006033746A3
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WO
WIPO (PCT)
Prior art keywords
metal layer
etch
metal
forming
semiconductor device
Prior art date
Application number
PCT/US2005/029772
Other languages
French (fr)
Other versions
WO2006033746A2 (en
Inventor
Tab A Stevens
Brian J Goolsby
Bich-Yen Nguyen
Voon-Yew Thean
Original Assignee
Freescale Semiconductor Inc
Tab A Stevens
Brian J Goolsby
Bich-Yen Nguyen
Voon-Yew Thean
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Tab A Stevens, Brian J Goolsby, Bich-Yen Nguyen, Voon-Yew Thean filed Critical Freescale Semiconductor Inc
Priority to JP2007532343A priority Critical patent/JP4891906B2/en
Publication of WO2006033746A2 publication Critical patent/WO2006033746A2/en
Publication of WO2006033746A3 publication Critical patent/WO2006033746A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/963—Removing process residues from vertical substrate surfaces

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Composite Materials (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

A metal layer (24) is formed over a metal oxide (14), where the metal oxide is formed over a semiconductor substrate (12). A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings (26) at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer (22) is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
PCT/US2005/029772 2004-09-17 2005-08-23 Method of forming a semiconductor device having a metal layer WO2006033746A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007532343A JP4891906B2 (en) 2004-09-17 2005-08-23 Method for forming a semiconductor device having a metal layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/943,383 2004-09-17
US10/943,383 US7208424B2 (en) 2004-09-17 2004-09-17 Method of forming a semiconductor device having a metal layer

Publications (2)

Publication Number Publication Date
WO2006033746A2 WO2006033746A2 (en) 2006-03-30
WO2006033746A3 true WO2006033746A3 (en) 2007-05-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/029772 WO2006033746A2 (en) 2004-09-17 2005-08-23 Method of forming a semiconductor device having a metal layer

Country Status (4)

Country Link
US (1) US7208424B2 (en)
JP (1) JP4891906B2 (en)
KR (1) KR20070057844A (en)
WO (1) WO2006033746A2 (en)

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US7354847B2 (en) * 2004-01-26 2008-04-08 Taiwan Semiconductor Manufacturing Company Method of trimming technology
KR100562657B1 (en) * 2004-12-29 2006-03-20 주식회사 하이닉스반도체 Recess gate and method for manufacturing semiconductor device with the same
US7435681B2 (en) * 2006-05-09 2008-10-14 Macronix International Co., Ltd. Methods of etching stacks having metal layers and hard mask layers
JP5578389B2 (en) * 2006-05-16 2014-08-27 Ｎｌｔテクノロジー株式会社 Laminated film pattern forming method and gate electrode forming method
US7655550B2 (en) * 2006-06-30 2010-02-02 Freescale Semiconductor, Inc. Method of making metal gate transistors
US8394724B2 (en) * 2006-08-31 2013-03-12 Globalfoundries Singapore Pte. Ltd. Processing with reduced line end shortening ratio
US7977218B2 (en) * 2006-12-26 2011-07-12 Spansion Llc Thin oxide dummy tiling as charge protection
US20080237751A1 (en) * 2007-03-30 2008-10-02 Uday Shah CMOS Structure and method of manufacturing same
JP5248063B2 (en) * 2007-08-30 2013-07-31 株式会社日立ハイテクノロジーズ Semiconductor element processing method
US8012811B2 (en) * 2008-01-03 2011-09-06 International Business Machines Corporation Methods of forming features in integrated circuits
US8168542B2 (en) * 2008-01-03 2012-05-01 International Business Machines Corporation Methods of forming tubular objects
JP5579374B2 (en) * 2008-07-16 2014-08-27 株式会社日立ハイテクノロジーズ Semiconductor processing method
JP5042162B2 (en) * 2008-08-12 2012-10-03 株式会社日立ハイテクノロジーズ Semiconductor processing method
JP5210915B2 (en) * 2009-02-09 2013-06-12 株式会社東芝 Manufacturing method of semiconductor device
JP5250476B2 (en) * 2009-05-11 2013-07-31 株式会社日立ハイテクノロジーズ Dry etching method
KR20110042614A (en) * 2009-10-19 2011-04-27 삼성전자주식회사 Semiconductor devices and methods of forming the same
US10438909B2 (en) * 2016-02-12 2019-10-08 Globalfoundries Singapore Pte. Ltd. Reliable passivation for integrated circuits
US10685849B1 (en) * 2019-05-01 2020-06-16 Applied Materials, Inc. Damage free metal conductor formation

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US6651678B2 (en) * 2001-11-16 2003-11-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
US6677244B2 (en) * 1998-09-10 2004-01-13 Hitachi, Ltd. Specimen surface processing method
US6794229B2 (en) * 2000-04-28 2004-09-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for semiconductor device

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JP3705977B2 (en) * 1999-12-03 2005-10-12 松下電器産業株式会社 Method for forming gate electrode
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US6794229B2 (en) * 2000-04-28 2004-09-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for semiconductor device
US6651678B2 (en) * 2001-11-16 2003-11-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
KR20070057844A (en) 2007-06-07
JP2008514001A (en) 2008-05-01
JP4891906B2 (en) 2012-03-07
WO2006033746A2 (en) 2006-03-30
US7208424B2 (en) 2007-04-24
US20060063364A1 (en) 2006-03-23

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