WO2006034854A3 - Semiconductor memory device having charge-trapping memory cells - Google Patents

Semiconductor memory device having charge-trapping memory cells Download PDF

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Publication number
WO2006034854A3
WO2006034854A3 PCT/EP2005/010470 EP2005010470W WO2006034854A3 WO 2006034854 A3 WO2006034854 A3 WO 2006034854A3 EP 2005010470 W EP2005010470 W EP 2005010470W WO 2006034854 A3 WO2006034854 A3 WO 2006034854A3
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WO
WIPO (PCT)
Prior art keywords
charge
trapping
sidewalls
ridge
cells
Prior art date
Application number
PCT/EP2005/010470
Other languages
French (fr)
Other versions
WO2006034854A2 (en
Inventor
Martin Verhoeven
Original Assignee
Infineon Technologies Ag
Martin Verhoeven
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Martin Verhoeven filed Critical Infineon Technologies Ag
Publication of WO2006034854A2 publication Critical patent/WO2006034854A2/en
Publication of WO2006034854A3 publication Critical patent/WO2006034854A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

The memory cell is arranged in a ridge (15) of semiconductor material forming a fin (1) with sidewalls and a channel region between source and drain regions (2). Memory layer sequences (4), such as ONO, provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes (3). This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.
PCT/EP2005/010470 2004-09-29 2005-09-28 Semiconductor memory device having charge-trapping memory cells WO2006034854A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/952,707 2004-09-29
US10/952,707 US7423310B2 (en) 2004-09-29 2004-09-29 Charge-trapping memory cell and charge-trapping memory device

Publications (2)

Publication Number Publication Date
WO2006034854A2 WO2006034854A2 (en) 2006-04-06
WO2006034854A3 true WO2006034854A3 (en) 2006-06-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/010470 WO2006034854A2 (en) 2004-09-29 2005-09-28 Semiconductor memory device having charge-trapping memory cells

Country Status (4)

Country Link
US (1) US7423310B2 (en)
DE (1) DE102004050929B4 (en)
TW (1) TWI276218B (en)
WO (1) WO2006034854A2 (en)

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US7473952B2 (en) * 2005-05-02 2009-01-06 Infineon Technologies Ag Memory cell array and method of manufacturing the same
JP4822792B2 (en) * 2005-10-04 2011-11-24 株式会社東芝 Semiconductor device and manufacturing method thereof
US7589387B2 (en) * 2005-10-05 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
US7394128B2 (en) * 2005-12-15 2008-07-01 Infineon Technologies Ag Semiconductor memory device with channel regions along sidewalls of fins
JP4496179B2 (en) * 2006-03-13 2010-07-07 株式会社東芝 Semiconductor memory device and manufacturing method thereof
US20070246765A1 (en) * 2006-03-30 2007-10-25 Lars Bach Semiconductor memory device and method for production
KR100777016B1 (en) 2006-06-20 2007-11-16 재단법인서울대학교산학협력재단 A nand flash memory array having a pillar structure and a fabricating method of the same
US7700427B2 (en) * 2007-06-13 2010-04-20 Qimonda Ag Integrated circuit having a Fin structure
JP5301123B2 (en) * 2007-07-25 2013-09-25 スパンション エルエルシー Semiconductor device and manufacturing method thereof
JPWO2009025368A1 (en) * 2007-08-22 2010-11-25 株式会社東芝 Semiconductor memory device and manufacturing method of semiconductor memory device
US7919792B2 (en) * 2008-12-18 2011-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell architecture and methods with variable design rules
US8461640B2 (en) 2009-09-08 2013-06-11 Silicon Storage Technology, Inc. FIN-FET non-volatile memory cell, and an array and method of manufacturing
US9443851B2 (en) 2014-01-03 2016-09-13 Samsung Electronics Co., Ltd. Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same
US9634018B2 (en) 2015-03-17 2017-04-25 Silicon Storage Technology, Inc. Split gate non-volatile memory cell with 3D finFET structure, and method of making same
CN108243625B (en) 2015-11-03 2022-04-22 硅存储技术公司 Split-gate non-volatile flash memory cell with metal gate and method of making the same
WO2017104505A1 (en) * 2015-12-18 2017-06-22 株式会社フローディア Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device
JP6688698B2 (en) * 2016-07-08 2020-04-28 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US10312247B1 (en) 2018-03-22 2019-06-04 Silicon Storage Technology, Inc. Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication
US10468428B1 (en) 2018-04-19 2019-11-05 Silicon Storage Technology, Inc. Split gate non-volatile memory cells and logic devices with FinFET structure, and method of making same
US10727240B2 (en) 2018-07-05 2020-07-28 Silicon Store Technology, Inc. Split gate non-volatile memory cells with three-dimensional FinFET structure
US10714536B2 (en) * 2018-10-23 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method to form memory cells separated by a void-free dielectric structure
US11257908B2 (en) * 2018-10-26 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with stacked semiconductor layers as channels
US10797142B2 (en) 2018-12-03 2020-10-06 Silicon Storage Technology, Inc. FinFET-based split gate non-volatile flash memory with extended source line FinFET, and method of fabrication
US10937794B2 (en) 2018-12-03 2021-03-02 Silicon Storage Technology, Inc. Split gate non-volatile memory cells with FinFET structure and HKMG memory and logic gates, and method of making same
CN111200020B (en) * 2019-04-15 2021-01-08 合肥晶合集成电路股份有限公司 High voltage semiconductor device and method for manufacturing the same
US20210193671A1 (en) 2019-12-20 2021-06-24 Silicon Storage Technology, Inc. Method Of Forming A Device With Split Gate Non-volatile Memory Cells, HV Devices Having Planar Channel Regions And FINFET Logic Devices
US11114451B1 (en) * 2020-02-27 2021-09-07 Silicon Storage Technology, Inc. Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices
US11362100B2 (en) 2020-03-24 2022-06-14 Silicon Storage Technology, Inc. FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling
US11237205B2 (en) * 2020-05-06 2022-02-01 Nanya Technology Corporation Test array structure, wafer structure and wafer testing method
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Also Published As

Publication number Publication date
WO2006034854A2 (en) 2006-04-06
DE102004050929A1 (en) 2006-04-13
TWI276218B (en) 2007-03-11
US20060071259A1 (en) 2006-04-06
US7423310B2 (en) 2008-09-09
TW200618264A (en) 2006-06-01
DE102004050929B4 (en) 2010-07-29

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