WO2006039224A3 - Racecheck: a race logic analyzer program for digital integrated circuits - Google Patents

Racecheck: a race logic analyzer program for digital integrated circuits Download PDF

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Publication number
WO2006039224A3
WO2006039224A3 PCT/US2005/034315 US2005034315W WO2006039224A3 WO 2006039224 A3 WO2006039224 A3 WO 2006039224A3 US 2005034315 W US2005034315 W US 2005034315W WO 2006039224 A3 WO2006039224 A3 WO 2006039224A3
Authority
WO
WIPO (PCT)
Prior art keywords
race logic
racecheck
designs
design
logic analysis
Prior art date
Application number
PCT/US2005/034315
Other languages
French (fr)
Other versions
WO2006039224A2 (en
Inventor
Terence Chan
Original Assignee
Terence Chan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Terence Chan filed Critical Terence Chan
Priority to GB0712530A priority Critical patent/GB2438327A/en
Publication of WO2006039224A2 publication Critical patent/WO2006039224A2/en
Publication of WO2006039224A3 publication Critical patent/WO2006039224A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318314—Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

This invention describes RaceCheck, which audits IC designs for race logic design errors. Specically, RaceCheck make use of structural and timing information of IC designs for accurate static and/or dynamic race logic analysis The static logic analysis reports all possible race logic in IC designs,and it can be used in all stages of IC’s decelopment. The dynamic race logic analysis is used once an IC design’s testbench is available It uses a HDL simulation kernel to execute the IC design operations, and reports the exact times and locations of detected race logic in the design. The use of both structural and timing information of IC designs to filter out false violations, the detection of concurrent invocation races of system-and user-defined functions and tasks, and the use of a HDL simulation kernel for dynamic race logic analysis are all novel features of the invention.
PCT/US2005/034315 2004-10-01 2005-09-22 Racecheck: a race logic analyzer program for digital integrated circuits WO2006039224A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0712530A GB2438327A (en) 2004-10-01 2005-09-22 Racecheck:a race logic analyzer program for digital integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61510804P 2004-10-01 2004-10-01
US60/615,108 2004-10-01

Publications (2)

Publication Number Publication Date
WO2006039224A2 WO2006039224A2 (en) 2006-04-13
WO2006039224A3 true WO2006039224A3 (en) 2007-08-09

Family

ID=36142988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/034315 WO2006039224A2 (en) 2004-10-01 2005-09-22 Racecheck: a race logic analyzer program for digital integrated circuits

Country Status (3)

Country Link
US (2) US7334203B2 (en)
GB (1) GB2438327A (en)
WO (1) WO2006039224A2 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7584442B2 (en) * 2005-12-09 2009-09-01 Lsi Corporation Method and apparatus for generating memory models and timing database
KR101282963B1 (en) * 2006-05-12 2013-07-08 삼성전자주식회사 Emulation system and method thereof
US7448008B2 (en) * 2006-08-29 2008-11-04 International Business Machines Corporation Method, system, and program product for automated verification of gating logic using formal verification
US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
US8756557B2 (en) * 2007-05-09 2014-06-17 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US9405870B2 (en) * 2007-09-06 2016-08-02 Globalfoundries Inc. Generating coverage data for a switch frequency of HDL or VHDL signals
US7991605B1 (en) * 2008-06-06 2011-08-02 Cadence Design Systems, Inc. Method and apparatus for translating a verification process having recursion for implementation in a logic emulator
US8239791B2 (en) * 2008-06-09 2012-08-07 International Business Machines Corporation Method of designing multi-state restore circuitry for restoring state to a power managed functional block
JP5185439B2 (en) 2008-07-23 2013-04-17 オパラックス インコーポレーテッド Tunable photonic crystal composition
JP5265318B2 (en) * 2008-12-03 2013-08-14 ルネサスエレクトロニクス株式会社 Logic verification device
US8826250B2 (en) * 2010-06-30 2014-09-02 Bioproduction Group Method for just-in-time compilation and execution of code blocks within discrete event simulations
US9038048B2 (en) * 2010-07-22 2015-05-19 The Trustees Of Columbia University In The City Of New York Methods, systems, and media for protecting applications from races
US9454460B2 (en) 2010-07-23 2016-09-27 The Trustees Of Columbia University In The City Of New York Methods, systems, and media for providing determinism in multithreaded programs
CN101989311B (en) * 2010-09-03 2012-07-04 王振国 Simulate coverage rate statistical method and device based on hardware
US9858368B2 (en) * 2011-07-13 2018-01-02 International Business Machines Corporation Integrating manufacturing feedback into integrated circuit structure design
US8543953B2 (en) * 2012-01-04 2013-09-24 Apple Inc. Automated stimulus steering during simulation of an integrated circuit design
CN102930090B (en) * 2012-10-22 2015-12-16 中兴通讯股份有限公司 Higher level lanquage realizes the modeling method of hardware unblock assignment
US9032347B1 (en) * 2013-03-15 2015-05-12 Cadence Design Systems, Inc. System and method for automated simulator assertion synthesis and digital equivalence checking
CN103699757B (en) * 2014-01-06 2016-05-25 西北工业大学 A kind ofly take into account pneumatic and mini-sized flap wings analytical system and method structure Coupling characteristic
US9183331B1 (en) 2014-03-31 2015-11-10 Cadence Design Systems, Inc. Formalizing IP driver interface
US9208282B1 (en) * 2014-07-30 2015-12-08 Cadence Design Systems, Inc. Enabling IP execution on a simulation execution platform
US9477800B1 (en) * 2015-02-11 2016-10-25 Cadence Design Systems, Inc. System, method, and computer program product for automatically selecting a constraint solver algorithm in a design verification environment
US11429679B1 (en) * 2015-07-17 2022-08-30 EMC IP Holding Company LLC System and method for augmenting element records associated with the elements of a distributed computing environment with user-defined content
CN105653409B (en) * 2015-12-25 2019-02-01 北京时代民芯科技有限公司 A kind of hardware emulator verify data extraction system based on data type conversion
US10565335B2 (en) * 2016-03-04 2020-02-18 Montana Systems Inc. Event-driven design simulation
JP6721423B2 (en) * 2016-06-14 2020-07-15 株式会社日立製作所 App logic and its verification method
US10198539B1 (en) * 2017-03-02 2019-02-05 Cadence Design Systems, Inc. Systems and methods for dynamic RTL monitors in emulation systems
US10755014B2 (en) * 2018-03-14 2020-08-25 Montana Systems Inc. Event-driven design simulation
US11023637B1 (en) 2019-12-20 2021-06-01 Cadence Design Systems, Inc. Hybrid deferred assertion for circuit design
JP2022049470A (en) 2020-09-16 2022-03-29 キオクシア株式会社 Logic simulation verification system, logic simulation verification method and program
CN113947050B (en) * 2021-08-27 2022-09-02 芯华章科技股份有限公司 Method, electronic device, and storage medium for generating formal verification environment
US11704461B1 (en) * 2022-01-04 2023-07-18 International Business Machines Corporation Dynamic control of coverage by a verification testbench
CN117250480B (en) * 2023-11-08 2024-02-23 英诺达(成都)电子科技有限公司 Loop detection method, device, equipment and storage medium of combinational logic circuit

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5901061A (en) * 1996-05-24 1999-05-04 Hewlett-Packard Company Method of checking for races in a digital design
US6625788B1 (en) * 1998-06-26 2003-09-23 Xilinx, Inc. Method for verifying timing in a hard-wired IC device modeled from an FPGA
US20030188276A1 (en) * 2002-04-02 2003-10-02 Pie Charles Corey Method and apparatus for identifying switching race conditions in a circuit design
US20040088666A1 (en) * 2002-10-31 2004-05-06 Daniel Poznanovic System and method for partitioning control-dataflow graph representations
US20040133409A1 (en) * 2003-01-06 2004-07-08 Rajarshi Mukherjee Method and system for design verification
US6785873B1 (en) * 1997-05-02 2004-08-31 Axis Systems, Inc. Emulation system with multiple asynchronous clocks
US6907599B1 (en) * 2001-06-15 2005-06-14 Verisity Ltd. Synthesis of verification languages

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69327389T2 (en) * 1992-10-29 2000-06-15 Altera Corp Procedure for testing designs for programmable logic circuits
US5949983A (en) * 1996-04-18 1999-09-07 Xilinx, Inc. Method to back annotate programmable logic device design files based on timing information of a target technology
US6651225B1 (en) * 1997-05-02 2003-11-18 Axis Systems, Inc. Dynamic evaluation logic system and method
US6135647A (en) * 1997-10-23 2000-10-24 Lsi Logic Corporation System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code
US6097884A (en) * 1997-12-08 2000-08-01 Lsi Logic Corporation Probe points and markers for critical paths and integrated circuits
US6836877B1 (en) * 1998-02-20 2004-12-28 Lsi Logic Corporation Automatic synthesis script generation for synopsys design compiler
US20060117274A1 (en) * 1998-08-31 2006-06-01 Tseng Ping-Sheng Behavior processor system and method
US6466898B1 (en) 1999-01-12 2002-10-15 Terence Chan Multithreaded, mixed hardware description languages logic simulation on engineering workstations
US6745160B1 (en) * 1999-10-08 2004-06-01 Nec Corporation Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
US6728908B1 (en) * 1999-11-18 2004-04-27 California Institute Of Technology I2C bus protocol controller with fault tolerance
US6618839B1 (en) * 1999-11-30 2003-09-09 Synplicity, Inc. Method and system for providing an electronic system design with enhanced debugging capabilities
US6496966B1 (en) * 2000-09-07 2002-12-17 Hewlett-Packard Company Place and route scan chain partitioning by clock regions
US6807520B1 (en) * 2000-12-11 2004-10-19 Synopsys, Inc. System and method for simulation of an integrated circuit design using a hierarchical input netlist and divisions along hierarchical boundaries thereof
US6792580B2 (en) * 2001-01-31 2004-09-14 Kabushiki Kaisha Toshiba Method and computer program product for software/hardware language model conversion
US6957403B2 (en) * 2001-03-30 2005-10-18 Syntest Technologies, Inc. Computer-aided design system to automate scan synthesis at register-transfer level
US6606734B2 (en) * 2001-06-21 2003-08-12 David J. Greaves Simulation method and compiler for hardware/software programming
US6754763B2 (en) * 2001-07-30 2004-06-22 Axis Systems, Inc. Multi-board connection system for use in electronic design automation
US7039882B2 (en) * 2002-06-17 2006-05-02 Amar Pal Singh Rana Technology dependent transformations for Silicon-On-Insulator in digital design synthesis
US20040139411A1 (en) * 2003-01-13 2004-07-15 Smith Winthrop W. Heterogenous design process and apparatus for systems employing static design components and programmable gate array sub-array areas
US7162703B1 (en) * 2003-06-19 2007-01-09 Altera Corporation Electrical design rule checking expert traverser system
US7219315B1 (en) * 2003-09-22 2007-05-15 Tenison Technology Eda Limited Comparison of semiconductor circuitry simulations
US7478350B2 (en) * 2005-01-27 2009-01-13 Arc International (Uk) Limited Model modification method for timing Interoperability for simulating hardware
US7716608B2 (en) * 2005-06-01 2010-05-11 Massachusetts Institute Of Technology Circuit synthesis with sequential rules

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5901061A (en) * 1996-05-24 1999-05-04 Hewlett-Packard Company Method of checking for races in a digital design
US6785873B1 (en) * 1997-05-02 2004-08-31 Axis Systems, Inc. Emulation system with multiple asynchronous clocks
US6625788B1 (en) * 1998-06-26 2003-09-23 Xilinx, Inc. Method for verifying timing in a hard-wired IC device modeled from an FPGA
US6907599B1 (en) * 2001-06-15 2005-06-14 Verisity Ltd. Synthesis of verification languages
US20030188276A1 (en) * 2002-04-02 2003-10-02 Pie Charles Corey Method and apparatus for identifying switching race conditions in a circuit design
US20040088666A1 (en) * 2002-10-31 2004-05-06 Daniel Poznanovic System and method for partitioning control-dataflow graph representations
US20040133409A1 (en) * 2003-01-06 2004-07-08 Rajarshi Mukherjee Method and system for design verification

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
HUANG I.-J. ET AL.: "An Extended Classification of Inter-instruction Dependency and Its Application in Automatic Synthesis of Pipelined Processors", PROCEEDINGS OF THE 26TH ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 1 December 1993 (1993-12-01), pages 236 - 246 *
JOSEPHS M.B. ET AL.: "Modeling and Design of Asynchronous Circuits", PROCEEDINGS OF THE IEEE, vol. 87, no. 2, February 1999 (1999-02-01), pages 234 - 242 *
POZNIANSKY E. ET AL.: "Efficient On-the-Fly Detection in Multithreaded C++ Programs", PROCEEDINGS OF INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM, 22 April 2003 (2003-04-22), pages 1 - 8 *

Also Published As

Publication number Publication date
US7757191B2 (en) 2010-07-13
US20080098339A1 (en) 2008-04-24
US20060075367A1 (en) 2006-04-06
GB0712530D0 (en) 2007-08-08
WO2006039224A2 (en) 2006-04-13
US7334203B2 (en) 2008-02-19
GB2438327A (en) 2007-11-21

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