WO2006048874A3 - Method of managing a multi-bit-cell flash memory - Google Patents

Method of managing a multi-bit-cell flash memory Download PDF

Info

Publication number
WO2006048874A3
WO2006048874A3 PCT/IL2005/001149 IL2005001149W WO2006048874A3 WO 2006048874 A3 WO2006048874 A3 WO 2006048874A3 IL 2005001149 W IL2005001149 W IL 2005001149W WO 2006048874 A3 WO2006048874 A3 WO 2006048874A3
Authority
WO
WIPO (PCT)
Prior art keywords
flash memory
cells
cell
represent
managing
Prior art date
Application number
PCT/IL2005/001149
Other languages
French (fr)
Other versions
WO2006048874A2 (en
Inventor
Menachem Lasser
Original Assignee
Milsys Ltd
Menachem Lasser
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Milsys Ltd, Menachem Lasser filed Critical Milsys Ltd
Publication of WO2006048874A2 publication Critical patent/WO2006048874A2/en
Publication of WO2006048874A3 publication Critical patent/WO2006048874A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A flash memory is managed by reserving one or more cells as flag cells to represent the number N of bits to store in the cells of a memory block, selecting the value of N from at least three candidates, and programming the flag cell(s) to represent the selected value. A flash memory is managed by selecting a value of the number N>2 of bits to store in the cells of a portion (e.g. a block or page) of the memory, reserving one other cell of the memory as a flag cell to represent how many bits actually are stored in each cell of the portion, and, as the cells of the portion are successively programmed with 1≤n≤N bits, programming the flag cell to represent n.
PCT/IL2005/001149 2004-11-04 2005-11-02 Method of managing a multi-bit-cell flash memory WO2006048874A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US62467504P 2004-11-04 2004-11-04
US60/624,675 2004-11-04
US11/198,180 2005-08-08
US11/198,180 US7716413B2 (en) 2004-02-15 2005-08-08 Method of making a multi-bit-cell flash memory

Publications (2)

Publication Number Publication Date
WO2006048874A2 WO2006048874A2 (en) 2006-05-11
WO2006048874A3 true WO2006048874A3 (en) 2009-04-30

Family

ID=36319558

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2005/001149 WO2006048874A2 (en) 2004-11-04 2005-11-02 Method of managing a multi-bit-cell flash memory

Country Status (3)

Country Link
US (2) US7716413B2 (en)
KR (1) KR100963707B1 (en)
WO (1) WO2006048874A2 (en)

Families Citing this family (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7660941B2 (en) * 2003-09-10 2010-02-09 Super Talent Electronics, Inc. Two-level RAM lookup table for block and page allocation and wear-leveling in limited-write flash-memories
US7333364B2 (en) * 2000-01-06 2008-02-19 Super Talent Electronics, Inc. Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory
WO2007023674A1 (en) * 2005-08-22 2007-03-01 Matsushita Electric Industrial Co., Ltd. Memory controller, nonvolatile storage, nonvolatile memory system, and method for writing data
JP4575288B2 (en) * 2005-12-05 2010-11-04 株式会社東芝 Storage medium, storage medium playback apparatus, storage medium playback method, and storage medium playback program
CN103258572B (en) 2006-05-12 2016-12-07 苹果公司 Distortion estimation in storage device and elimination
WO2007132452A2 (en) * 2006-05-12 2007-11-22 Anobit Technologies Reducing programming error in memory devices
WO2007132457A2 (en) * 2006-05-12 2007-11-22 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
WO2007132456A2 (en) * 2006-05-12 2007-11-22 Anobit Technologies Ltd. Memory device with adaptive capacity
US8060806B2 (en) * 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
KR100782329B1 (en) * 2006-10-02 2007-12-06 삼성전자주식회사 Nonvolatile memory device having a separately arranged flag cell array in memory cell array and method of operating the same
CN101601094B (en) 2006-10-30 2013-03-27 苹果公司 Reading memory cells using multiple thresholds
WO2008053472A2 (en) 2006-10-30 2008-05-08 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US8151163B2 (en) * 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US7900102B2 (en) * 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7593263B2 (en) * 2006-12-17 2009-09-22 Anobit Technologies Ltd. Memory device with reduced reading latency
US7751240B2 (en) * 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
US8151166B2 (en) * 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US7646636B2 (en) 2007-02-16 2010-01-12 Mosaid Technologies Incorporated Non-volatile memory with dynamic multi-mode operation
CN101715595A (en) * 2007-03-12 2010-05-26 爱诺彼得技术有限责任公司 Adaptive estimation of memory cell read thresholds
US8001320B2 (en) * 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US8234545B2 (en) * 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
WO2008139441A2 (en) 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
KR101303177B1 (en) * 2007-06-22 2013-09-17 삼성전자주식회사 Non-volatile memory device and operating method of the same
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US7869273B2 (en) 2007-09-04 2011-01-11 Sandisk Corporation Reducing the impact of interference during programming
US8174905B2 (en) * 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
WO2009050703A2 (en) * 2007-10-19 2009-04-23 Anobit Technologies Data storage in analog memory cell arrays having erase failures
US8068360B2 (en) * 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
WO2009063450A2 (en) * 2007-11-13 2009-05-22 Anobit Technologies Optimized selection of memory units in multi-unit memory devices
US7633798B2 (en) * 2007-11-21 2009-12-15 Micron Technology, Inc. M+N bit programming and M+L bit read for M bit memory cells
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) * 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
KR100948468B1 (en) * 2007-12-24 2010-03-17 주식회사 하이닉스반도체 The method for flag satus deterimining of non volatile memory device
US8085586B2 (en) * 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8156398B2 (en) * 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) * 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US8230300B2 (en) * 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8341331B2 (en) * 2008-04-10 2012-12-25 Sandisk Il Ltd. Method, apparatus and computer readable medium for storing data on a flash device using multiple writing modes
US8111548B2 (en) * 2008-07-21 2012-02-07 Sandisk Technologies Inc. Programming non-volatile storage using binary and multi-state programming processes
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US7852671B2 (en) 2008-10-30 2010-12-14 Micron Technology, Inc. Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array
US8208304B2 (en) * 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8248831B2 (en) * 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8397131B1 (en) 2008-12-31 2013-03-12 Apple Inc. Efficient readout schemes for analog memory cell devices
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
KR101005120B1 (en) * 2009-02-04 2011-01-04 주식회사 하이닉스반도체 Method of programming a non volatile memory device
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8458114B2 (en) * 2009-03-02 2013-06-04 Analog Devices, Inc. Analog computation using numerical representations with uncertainty
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8107306B2 (en) * 2009-03-27 2012-01-31 Analog Devices, Inc. Storage devices with soft processing
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8218366B2 (en) 2010-04-18 2012-07-10 Sandisk Technologies Inc. Programming non-volatile storage including reducing impact from other memory cells
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
KR20120119331A (en) * 2011-04-21 2012-10-31 에스케이하이닉스 주식회사 Memory and method for operating the same
US20120297248A1 (en) * 2011-05-17 2012-11-22 Alan David Bennett Block write handling after corruption
US9588883B2 (en) * 2011-09-23 2017-03-07 Conversant Intellectual Property Management Inc. Flash memory system
JP2013131275A (en) * 2011-12-22 2013-07-04 Toshiba Corp Nonvolatile semiconductor memory device
KR102005888B1 (en) 2012-07-06 2019-07-31 삼성전자주식회사 Nonvolatile memory device and read method thereof
US9236136B2 (en) * 2012-12-14 2016-01-12 Intel Corporation Lower page read for multi-level cell memory
US8913428B2 (en) 2013-01-25 2014-12-16 Sandisk Technologies Inc. Programming non-volatile storage system with multiple memory die
US9026757B2 (en) 2013-01-25 2015-05-05 Sandisk Technologies Inc. Non-volatile memory programming data preservation
US9117530B2 (en) 2013-03-14 2015-08-25 Sandisk Technologies Inc. Preserving data from adjacent word lines while programming binary non-volatile storage elements
US9009568B2 (en) 2013-08-09 2015-04-14 Sandisk Technologies Inc. Sensing parameter management in non-volatile memory storage system to compensate for broken word lines
US10096355B2 (en) * 2015-09-01 2018-10-09 Sandisk Technologies Llc Dynamic management of programming states to improve endurance
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297988B1 (en) * 2000-02-25 2001-10-02 Advanced Micro Devices, Inc. Mode indicator for multi-level memory

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268870A (en) 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5404485A (en) 1993-03-08 1995-04-04 M-Systems Flash Disk Pioneers Ltd. Flash file system
US5544312A (en) * 1994-04-29 1996-08-06 Intel Corporation Method of detecting loss of power during block erasure and while writing sector data to a solid state disk
US5671388A (en) * 1995-05-03 1997-09-23 Intel Corporation Method and apparatus for performing write operations in multi-level cell storage device
US5815434A (en) * 1995-09-29 1998-09-29 Intel Corporation Multiple writes per a single erase for a nonvolatile memory
DE69635105D1 (en) * 1996-01-31 2005-09-29 St Microelectronics Srl Multi-stage memory circuits and corresponding reading and writing methods
US5930167A (en) 1997-07-30 1999-07-27 Sandisk Corporation Multi-state non-volatile flash memory capable of being its own two state write cache
US5937425A (en) 1997-10-16 1999-08-10 M-Systems Flash Disk Pioneers Ltd. Flash file system optimized for page-mode flash technologies
US6226728B1 (en) * 1998-04-21 2001-05-01 Intel Corporation Dynamic allocation for efficient management of variable sized data within a nonvolatile memory
JP2000040375A (en) 1998-07-17 2000-02-08 Mitsubishi Electric Corp Semiconductor memory
KR20000031100A (en) 1998-11-03 2000-06-05 이종수 Electronic gauge using flash memory
US6148354A (en) 1999-04-05 2000-11-14 M-Systems Flash Disk Pioneers Ltd. Architecture for a universal serial bus-based PC flash disk
US6687325B1 (en) * 1999-06-23 2004-02-03 Intel Corporation Counter with non-uniform digit base
US6426893B1 (en) * 2000-02-17 2002-07-30 Sandisk Corporation Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US6834331B1 (en) * 2000-10-24 2004-12-21 Starfish Software, Inc. System and method for improving flash memory data integrity
US6522580B2 (en) 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US6549457B1 (en) * 2002-02-15 2003-04-15 Intel Corporation Using multiple status bits per cell for handling power failures during write operations
US6988175B2 (en) 2003-06-30 2006-01-17 M-Systems Flash Disk Pioneers Ltd. Flash memory management method that is resistant to data corruption by power loss
US6903972B2 (en) 2003-07-30 2005-06-07 M-Systems Flash Disk Pioneers Ltd. Different methods applied for archiving data according to their desired lifetime
US7181672B2 (en) * 2003-09-25 2007-02-20 Intel Corporation Method, system, and apparatus for supporting power loss recovery in ECC enabled memory devices
US7310347B2 (en) 2004-03-14 2007-12-18 Sandisk, Il Ltd. States encoding in multi-bit flash cells
US7272041B2 (en) * 2005-06-30 2007-09-18 Intel Corporation Memory array with pseudo single bit memory cell and method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297988B1 (en) * 2000-02-25 2001-10-02 Advanced Micro Devices, Inc. Mode indicator for multi-level memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TANENBAUM. A.S., STRUCTURED COMPUTER ORGANIZATION., 1984, pages 10 - 12 *

Also Published As

Publication number Publication date
KR20070087556A (en) 2007-08-28
US7716413B2 (en) 2010-05-11
US20060004952A1 (en) 2006-01-05
US8024509B2 (en) 2011-09-20
KR100963707B1 (en) 2010-06-14
US20080123412A1 (en) 2008-05-29
WO2006048874A2 (en) 2006-05-11

Similar Documents

Publication Publication Date Title
WO2006048874A3 (en) Method of managing a multi-bit-cell flash memory
WO2005076745A3 (en) Method of managing a multi-bit-cell flash memory
WO2005074386A3 (en) Two-phase programming of a flash memory
WO2006072945A3 (en) Method of managing a multi-bit cell flash memory with improved reliability and performance
ATE396483T1 (en) NON-VOLATILE STORAGE DEVICE AND METHOD FOR STORING STATUS INFORMATION USING MULTIPLE STRINGS
DE602004023209D1 (en) METHOD AND SYSTEM FOR OPTIMIZING THE RELIABILITY AND EFFICIENCY OF PROGRAMMING DATA IN NON-VOLATILE MEMORY BLOCKS
CN101174457B (en) Multi-bit flash memory device and memory cell array
WO2009037691A3 (en) Programming orders for reducing distortion in arrays of multi-level analog memory cells
EP1622164A3 (en) Method of operating a block of flash memory
WO2005103882A3 (en) Data structure for a hardware database management system
WO2003100786A8 (en) Serially sensing the output of multilevel cell arrays
EP1271550A3 (en) Method and device for reading dual bit memory cells using multiple reference cells with two side read
ATE423380T1 (en) ROBUST DATA MULTIPLE AND IMPROVED UPDATE PROCESS IN MULTI-BIT NON-VOLATILE MEMORY
EP1227498A3 (en) An EEPROM array and method for operation thereof
WO2005066793A3 (en) Non-volatile memory and method with non-sequential update block management
WO2008094899A3 (en) Memory device architectures and operation
WO2008098363A8 (en) Non-volatile memory with dynamic multi-mode operation
WO2007041064A3 (en) Reliably storing information across multiple computers
DE60130012D1 (en) DESCRIPTIVE TRACKING CELLS
TW200612433A (en) Programming inhibit for non-volatile memory
EP1603137A3 (en) Program/erase method for p-channel charge trapping memory device
EP1381056A3 (en) System and method for implementing a counter
TW200634838A (en) Page buffer of flash memory device with improved program operation performance and program operation control method
DE60301119D1 (en) Non-volatile SRAM memory cell
TW200710851A (en) Non-volatile memory device, and control method of non-volatile memory device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 1020077010170

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05802343

Country of ref document: EP

Kind code of ref document: A2