WO2006055476A2 - Method of integrating optical devices and electronic devices on an integrated circuit - Google Patents
Method of integrating optical devices and electronic devices on an integrated circuit Download PDFInfo
- Publication number
- WO2006055476A2 WO2006055476A2 PCT/US2005/041155 US2005041155W WO2006055476A2 WO 2006055476 A2 WO2006055476 A2 WO 2006055476A2 US 2005041155 W US2005041155 W US 2005041155W WO 2006055476 A2 WO2006055476 A2 WO 2006055476A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor substrate
- electronic device
- device portion
- semiconductor layer
- optical device
- Prior art date
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 158
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 125000006850 spacer group Chemical group 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 230000000903 blocking effect Effects 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 230000008901 benefit Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000007717 exclusion Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
Definitions
- the present invention relates to providing different devices types on the same integrated circuits, and more particularly to integrating optical devices with electronic devices on the same integrated circuit.
- a method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device portion.
- a semiconductor layer is epitaxially grown overlying an exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region. At least a portion of an electronic device is formed on the active semiconductor layer within the electronic device portion of the semiconductor substrate.
- the method further includes forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device; forming a salicide blocking layer overlying the optical device portion, and saliciding the electronic device portion, wherein the salicide blocking layer prevents salicidation of the epitaxially grown semiconductor layer within the optical device portion; and forming an interlevel dielectric layer overlying the electronic device portion and the optical device portion of the semiconductor substrate.
- FIG. 1 is a cross section of a semiconductor device structure useful in understanding a method according to a first embodiment of the invention at a stage in processing;
- FIG. 2 is a cross section of the semiconductor device structure of FIG. 1 at a subsequent stage in processing
- FIG. 3 is a cross section of the semiconductor device structure of FIG. 2 at a subsequent stage in processing
- FIG. 4 is a cross section of the semiconductor device structure of FIG. 3 at a subsequent stage in processing
- FIG. 5 is a cross section of the semiconductor device structure of FIG. 4 at a subsequent stage in processing
- FIG. 6 is a cross section of a semiconductor device structure of FIG. 5 at a subsequent stage in processing
- FIG. 7 is a cross section of the semiconductor device structure of FIG. 6 at a subsequent stage in processing
- FIG. 8 is a cross section of the semiconductor device structure of FIG. 7 at a subsequent stage in processing
- FIG. 9 is a cross section of the semiconductor device structure of FIG. 8 at a subsequent stage in processing
- FIG. 10 is a cross section of the semiconductor device structure of FIG. 9 at a subsequent stage in processing
- FIG. 11 is a cross section of the semiconductor device structure of FIG. 10 at a subsequent stage in processing
- FIG. 12 is a cross section of the semiconductor device structure of FIG. 11 at a subsequent stage in processing
- FIG. 13 is a cross section of the semiconductor device structure of FIG. 12 at a subsequent stage in processing
- FIG. 14 is a cross section of a semiconductor device useful in understanding a method according to a second embodiment of the invention at a stage in processing
- FIG. 15 is a cross section of the semiconductor device structure of FIG. 14 at a subsequent stage in processing
- FIG. 16 is a cross section of the semiconductor device structure of FIG. 15 at a subsequent stage in processing.
- a semiconductor device structure has both a waveguide and a transistor on the same integrated circuit.
- the starting material thickness requirements for high performance electronics and Optical Structures formed on SOI can be different.
- an epitaxial silicon growth may be required to optimize the thickness of one or both parts of the integrated circuit.
- trench isolation is used to form the electrical isolation of the transistors.
- an epitaxial silicon growth is performed in the optical regions of the circuit, wherein a thicker silicon layer may be desired for the formation of high performance waveguides within the region.
- epitaxial formation is performed after Source/Drain extension formation to maintain wafer planarity during the electronics device fabrication.
- silicon removal is used for defining the optical devices in the optics region.
- Such devices could include, but not be limited to: a waveguide, an optical grating coupler, an optical modulator, an optical wavelength-selective filter or an arrayed waveguide grating.
- a salicide block is used over the optical devices to prevent salicide formation in unwanted areas of the waveguide.
- FIG. 1 is a semiconductor device structure 10 comprising an insulating layer 12, a semiconductor layer 14 on insulating layer 12, a pad oxide layer 16 on semiconductor layer 14, and a nitride layer 18.
- Semiconductor device structure 10 is divided into an optical device region 20 and an electronic device region 22.
- optical device region 20 is for forming a waveguide and electronic device region 22 is for forming a transistor.
- Optical device region 20 has an opening 24 and an opening 26. Openings 24 and 26 extend to insulating layer 12.
- Semiconductor layer 14 is preferably monocrystalline silicon that is on the order of about 700 Angstroms thick.
- insulating layer 12 includes oxide of on the order of about 8000 Angstroms or greater in thickness on a relatively thick silicon substrate (not shown). The exact thickness is determined by the particular optical device requirements.
- Insulating layer 12 and semiconductor layer 14 together in this described manner are similar to a standard semiconductor on insulator (SOI) wafer except that in this case insulating layer 12 is thicker than the corresponding buried oxide layer in a conventional SOI wafer.
- SOI semiconductor on insulator
- optical region 20 is masked so that no openings are formed in optical region 20. Openings such as openings 24 and 26 are often called trenches.
- Pad oxide 16 and nitride 18 are conventional layers used in preparation for trench formation.
- a conventional trench fill is performed, preferably with high density plasma (HDP) oxide as shown in regions 36 and 38.
- CMP is performed to complete a conventional shallow trench isolation (STI) process module.
- HDP high density plasma
- a layer of photoresist 40 is deposited and patterned using photolithography on the wafer, thus creating an opening 42 over optics region 20.
- the photoresist could include a single spin-on resist or a stack of an anti-reflection coating and photoresist.
- FIG. 3 a portion of pad oxide 16 and nitride 18 are removed with an etching step in region 42 to form an opening 44 in optical device region 20. The photoresist 40 is subsequently removed.
- silicon is selectively epitaxially grown in open region 44, using film stack 18,16 as the selective growth window.
- the epitaxial growth is intended to thicken the silicon layer to a total of approximately 3000 angstroms.
- the actual final silicon film thickness is determined by the particular device requirements of the optical device.
- the resultant grown silicon is depicted as region 46.
- epitaxial growth requires careful pre-treatment to ensure that the silicon surface is clean and free of native oxide prior to growth. Such cleans may consist of a high temperature hydrogen bake. Such a heat cycle may not desirable after diffusions are formed in a transistor flow, and thus, this embodiment favorably places the epitaxial process prior to well formation in the standard electronics flow.
- the pad oxide 16 and remainder of nitride 18 are removed with an etching step in region 22.
- the nitride etch preferably includes a dry etch stopping on oxide 16 in the electronics region 22 and silicon in optics region 20.
- FIG. 6 standard semiconductor processing is followed to build the devices in electronics region 22, up through gate electrode deposition. Not shown, for simplicity, are the well implants in this region, which could be masked from optics region 20.
- a gate dielectric 48 is grown or deposited across the entire structure and then a gate electrode material 50 is deposited on top of the gate dielectric.
- the gate dielectric 48 could be formed either by a first, thick gate thermal oxidation followed by a strip or patterned strip and then followed by a subsequent or multiple repetitions of gate oxidations depending upon the specific electronic or optical device needs.
- FIG. 7 Shown in FIG. 7 is the structure following the patterning and etching of the gate electrode material 50 in region 22 to form the gate electrode 52. Note that the gate electrode material is completely removed from the top of the optics region 20.
- FIG. 8 Shown in FIG. 8 is the semiconductor device structure 10 through spacer formation in electronic region 22 using conventional means.
- the transistor comprises gate dielectric 48 over semiconductor layer 14 and etched gate electrode 52 over gate dielectric 48.
- Source/drain extensions 54 are formed through ion implantation.
- a spacer liner 56 is deposited everywhere and a sidewall spacer 58 is formed around gate 52 by etching of the spacer material 58 to stop on the spacer liner 56.
- FIG. 9 Shown in FIG. 9 is semiconductor device structure 10 after formation of trenches 60 and 62 in the epitaxially grown silicon 46 within optics region 20. Using standard photolithographic techniques, regions over epitaxial silicon 46 are opened and portions of liner 56 and silicon layer 46 are subsequently etched using a conventional timed silicon etch. The etch depth can be selected according the particular optical device requirements but would, in this embodiment, be about 1500 angstroms.
- semiconductor device structure 10 after formation of source/drain diffusions 64, 65, 66 and 67 in electronics region 22 and optional contact diffusions 68 and 70 in optical device region 20 and subsequent annealing. Such features can be formed by ion implantation and annealed with any thermal process with rapid thermal annealing being preferable.
- FIG. 11 semiconductor device structure 10 after deposition of a dielectric layer 72 intended as a salicide block layer.
- FIG. 12 Shown in FIG. 12 is semiconductor device structure 10 after selective removal of the salicide blocking film 72 and spacer liner oxide 56 over the exposed active regions 14 and gate electrode regions 52.
- the remainder of the film, 72 will be present over the entirety of the optical device region 20 as shown for simplicity in the accompanying figures, but may be removed in portions of the optical region 20 where contact diffusions are connected to the upper metallization (not shown in Figure 12).
- FIG. 13 Shown in FIG. 13 is semiconductor device structure 10 after the formation of a salicide 74 and subsequent interlayer dielectric deposition 76 and planarization.
- the salicide is formed through standard means by depositing a metal, preferably cobalt or nickel with a Ti of TiN cap, annealing to form a reaction between the metal and silicon 14 in contact with the metal and etching to remove unreacted metal. Additional heat cycles may be used in this process.
- Film 72 specifically prevents such a salicide from forming in the optical region where it might otherwise induce unacceptable optical losses.
- An interlayer dielectric film 76 or stack of films is deposited which simultaneously forms the side and upper cladding layers for optical devices in optical device portion 20. Subsequent to this step, contacts and metallizations are formed as in a conventional electronics process.
- FIG. 14 Shown in FIG. 14 is the device 10 in another embodiment of the present invention, wherein the epitaxial growth is not formed until after electronic device spacer deposition.
- This embodiment is motivated by the requirement of high-performance CMOS to have a planar surface prior to gate electrode patterning, thus enabling tight design rules and aggressive critical dimensions.
- a large exclusion region may be required between the optics and electronics portions of the chip.
- Standard electronics processing for the formation of high performance electronics is followed through spacer deposition.
- the electronics portion 22 is as it would be just prior to the spacer etch shown in FIG 8.
- the optics portion remains as active silicon.
- liner .dielectric 56 is shown to overlay the entire structure and spacer material, preferably a nitride, 57 is shown to overly the liner dielectric 56.
- an opening is patterned using photolithographic and etch techniques in the liner 56 and spacer film 57 in optics region 20 of the device.
- the entirety of electronics portion 22 is protected from this etch by photoresist.
- the photoresist is removed everywhere and the remainder of the layers 56 and 57 form a hardmask to define a region over the optics region 20 of the circuit for selective epitaxial growth.
- Approximately 2300 angstroms of silicon is grown in the opening in layers 56 and 57 to form a totality of about 3000 angstroms as region 80.
- the exact final thickness of the silicon 80 is determined by the specific device requirements on the optical device.
- spacer material 57 is etched to form sidewall spacers 58 in the electronics portion of the device. This etch would be performed selectively using a photoresist mask to protect the optics portion of the device. Subsequent processing would continue as indicated on FIG 9 with the exception that liner film 56 would not be present on the optical portion of the device and the remainder of liner and spacer material 56 and 57 would exist as the boundary of the window within which the epitaxial material (46 in embodiment 1 and 80 in embodiment 2) was grown. Likewise, the remainder of the process would follow FIGS 10, 11, 12 and 13 with the same modifications to the drawings.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007541397A JP5107049B2 (en) | 2004-11-15 | 2005-11-14 | Method for integrating an optical device and an electronic device on an integrated circuit |
EP05822578A EP1854128A4 (en) | 2004-11-15 | 2005-11-14 | Method of integrating optical devices and electronic devices on an integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/989,940 US7109051B2 (en) | 2004-11-15 | 2004-11-15 | Method of integrating optical devices and electronic devices on an integrated circuit |
US10/989,940 | 2004-11-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006055476A2 true WO2006055476A2 (en) | 2006-05-26 |
WO2006055476A3 WO2006055476A3 (en) | 2009-05-14 |
Family
ID=36386883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/041155 WO2006055476A2 (en) | 2004-11-15 | 2005-11-14 | Method of integrating optical devices and electronic devices on an integrated circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US7109051B2 (en) |
EP (1) | EP1854128A4 (en) |
JP (1) | JP5107049B2 (en) |
WO (1) | WO2006055476A2 (en) |
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US7574090B2 (en) * | 2006-05-12 | 2009-08-11 | Toshiba America Electronic Components, Inc. | Semiconductor device using buried oxide layer as optical wave guides |
US7916362B2 (en) | 2006-05-22 | 2011-03-29 | Eastman Kodak Company | Image sensor with improved light sensitivity |
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US8211732B2 (en) * | 2008-09-11 | 2012-07-03 | Omnivision Technologies, Inc. | Image sensor with raised photosensitive elements |
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US9143529B2 (en) | 2011-10-11 | 2015-09-22 | Citrix Systems, Inc. | Modifying pre-existing mobile applications to implement enterprise security policies |
US9280377B2 (en) | 2013-03-29 | 2016-03-08 | Citrix Systems, Inc. | Application with multiple operation modes |
US9599561B2 (en) | 2011-10-13 | 2017-03-21 | Affymetrix, Inc. | Methods, systems and apparatuses for testing and calibrating fluorescent scanners |
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KR102007258B1 (en) * | 2012-11-21 | 2019-08-05 | 삼성전자주식회사 | Method of fabricating optoelectronic substrate |
US9989703B2 (en) * | 2012-11-30 | 2018-06-05 | International Business Machines Corporation | Semiconductor structure and method for manufacturing a semiconductor structure |
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2004
- 2004-11-15 US US10/989,940 patent/US7109051B2/en not_active Expired - Fee Related
-
2005
- 2005-11-14 EP EP05822578A patent/EP1854128A4/en not_active Ceased
- 2005-11-14 WO PCT/US2005/041155 patent/WO2006055476A2/en active Application Filing
- 2005-11-14 JP JP2007541397A patent/JP5107049B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
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See references of EP1854128A4 * |
Also Published As
Publication number | Publication date |
---|---|
WO2006055476A3 (en) | 2009-05-14 |
JP5107049B2 (en) | 2012-12-26 |
EP1854128A4 (en) | 2010-12-15 |
US20060105479A1 (en) | 2006-05-18 |
JP2008521216A (en) | 2008-06-19 |
US7109051B2 (en) | 2006-09-19 |
EP1854128A2 (en) | 2007-11-14 |
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