WO2006057049A1 - カードおよびホスト機器 - Google Patents
カードおよびホスト機器 Download PDFInfo
- Publication number
- WO2006057049A1 WO2006057049A1 PCT/JP2004/017627 JP2004017627W WO2006057049A1 WO 2006057049 A1 WO2006057049 A1 WO 2006057049A1 JP 2004017627 W JP2004017627 W JP 2004017627W WO 2006057049 A1 WO2006057049 A1 WO 2006057049A1
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- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- card
- command
- response
- voltage range
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K17/00—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0608—Saving storage space on storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F2003/0697—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers device management, e.g. handlers, drivers, I/O schedulers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2206/00—Indexing scheme related to dedicated interfaces for computers
- G06F2206/10—Indexing scheme related to storage interfaces for computers, indexing schema related to group G06F3/06
- G06F2206/1014—One time programmable [OTP] memory, e.g. PROM, WORM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L2001/0092—Error control systems characterised by the topology of the transmission link
- H04L2001/0094—Bus
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a card and a host device, for example, confirmation of operating voltage and capacity of a memory card and a host device.
- the SD TM card is a memory card with built-in flash memory, card controller, etc., and is specifically designed to meet the demands for miniaturization, large capacity, and high-speed storage.
- the operating voltage of a memory card and its host device is in the 3.3V (high voltage) range, and supports a voltage range of 2.7 to 3.6V.
- the 1.8V (low voltage) range for example, the voltage range of 1.65 to 1.95V.
- An object of the present invention is to provide a memory card and a host device in which operating voltage and capacity can be mutually confirmed.
- the host device reads information from the card and writes information to the card, and belongs to either the first voltage range or the second voltage range lower than the first voltage range.
- a host device configured to supply a power supply voltage, and configured to issue a voltage identification command including a voltage range identification unit, an error detection unit, and a check pattern unit to the card;
- the voltage range identification unit includes information indicating whether the power supply voltage belongs to the first voltage range or the second voltage range, and the error detection unit receives the voltage identification command from the card.
- the voltage identification command It has a pattern configured to detect an error, and the check pattern portion has a preset pattern.
- the card according to the second aspect of the present invention has a memory for recording information, and a controller for controlling the memory, and has a first voltage range and a second voltage range lower than the first voltage range.
- a card configured to be supplied with a voltage identification command including a voltage range identification unit, an error detection unit, and a check pattern unit, In response to the voltage identification command, a response including a voltage range identification unit and an error detection unit or a check pattern unit is issued, and the voltage range identification unit of the response is the voltage range identification unit of the voltage identification command.
- the error detection unit of the response is configured so that the device that has received the response can detect the error of the response.
- the a, the switch Eck pattern portion of the response have the same pattern and the check pattern of the voltage identification command, it is characterized.
- FIG. 1 is a diagram schematically showing main parts of a card and a host device according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing a data arrangement in the NAND flash memory in the memory card of the first embodiment.
- FIG. 3 is a diagram exemplifying commands issued by the host device immediately before memory initialization.
- FIG. 4 is a diagram showing a main part of the contents of a voltage check command.
- FIG. 5 is a diagram showing a main part of the content of a response to a voltage check command.
- FIG. 6 is a flowchart showing processing for checking the operating voltage range when the host device operates in the high voltage range.
- FIG. 7 is a flowchart showing processing for checking the operating voltage range when the host device operates in the low voltage range.
- FIG. 8 is a diagram showing a main part of the contents of a memory initialization command according to the second embodiment of the present invention.
- FIG. 9 is a diagram showing a main part of the response contents of the memory initialization command according to the second embodiment.
- FIG. 10 is a flowchart showing a memory initialization process according to the second embodiment of the present invention.
- the first embodiment relates to mutual confirmation of operating voltage ranges supported by the host device and the card.
- Each card is initialized by a command from the host device when it is inserted into the host device.
- the host device issues a command for acquiring information in a register provided on the card that stores information on operating conditions. From this information, the host device can obtain information on the voltage supported by the card.
- the high voltage card operates with a low voltage power source supplied from the host even though the low voltage operation is not supported. May be supplied.
- the card since the card is operating at a voltage that is not originally supported by the card, the correctness of the transfer of the operating condition register information itself cannot be guaranteed. For this reason, if the host device attempts to initialize the inserted card and the initialization fails, it is determined that the card does not support low voltage operation. It becomes.
- the host device attempts to initialize the inserted card and the initialization fails, it is determined that the card does not support low voltage operation. It becomes.
- a conventional host device that supplies a high voltage and a two-voltage card, since both operate at a high voltage, no particular problem occurs.
- FIG. 1 schematically shows the main parts of a card and a host device according to the first embodiment of the present invention.
- card 1 contains memory 3 and card controller 4.
- Card 1 supports both low voltage (eg, 1.8V) operation and high voltage (eg, 3.3V) operation.
- low-voltage operation the card 1 and the host device 2 are actually configured to be able to handle voltages in the range including 1.8 V (eg, 1.65 to 1.95 V).
- high-voltage operation it is configured to be compatible with a voltage in the range including 3.3 V (for example, 2.7 to 3.6 V).
- the operating voltage range itself is the same between the card 1 and the host device 2.
- An unused voltage region is provided between the low voltage range and the high voltage range.
- the host device 2 includes a voltage supply unit 5, a reading Z writing unit 6, a command control unit 7, and the like.
- the voltage supply unit 5 operates with a high-voltage or low-voltage power supply potential Vdd and supplies the power supply potential Vdd and the common potential Vss to the card.
- Read Z writing unit 6 reads data from and writes information to / from card 1.
- Command control unit 7 exchanges commands and responses with card 1. Reference numerals 11, 12, 13, 14 and 17 will be described in the second embodiment.
- FIG. 3 shows the data layout of NAND flash memory.
- Each page of NAND flash memory 11 168 6-minute redundant part) X 4), and 128 pages are one erasure unit (256kByte + 8kByte).
- the NAND flash memory 21 includes a page buffer 21A for performing data input / output to / from the flash memory.
- the storage capacity of this page buffer 21A is 2112 bytes (2048 bytes + 64 bytes).
- the page buffer 21A executes data input / output processing for the flash memory in units of one page corresponding to its own storage capacity.
- the storage capacity of the NAND flash memory 21 is, for example, 1 Gbit, 256 kByte
- the number of blocks (erase units) is 512.
- the NAND flash memory 21 is manufactured by using, for example, a 0.09 m process technology. In other words, the design rule of the NAND flash memory 21 is less than 0.1 m.
- FIG. 2 illustrates the case where the erase unit is a 256 kbyte block, but it is also practically effective to construct the erase unit to be, for example, a 16 kbyte block.
- each page has 528 bytes (512 bytes worth of data storage + 16 bytes of redundancy), and 32 pages are one erasure unit (16 kByte + 0.5 kByte (where k is 1024) ).
- the NAND flash memory 21 may be a binary memory that stores 1-bit information in one memory cell, or a multi-value memory that stores information of 2 bits or more in one memory cell.
- FIG. 3 is a diagram exemplifying commands issued by the host device 2 immediately before the initialization of the memory. Note that the card 1 and the host device 2 operate according to the operation voltage until the operation condition register capability of the memory 2 is acquired by the memory initialization command described later. During this time, card 1 must be able to operate with the operating voltage.
- the host device 2 issues a reset command CMDR.
- CMDR reset command
- each circuit force S of card 1 is reset.
- the host device 2 issues a voltage check command CMDV.
- This command is a command newly introduced in the present embodiment.
- the conventional card 1 does not recognize this voltage check command CMDV, and does not return a response to the host device 2 even if this command is supplied.
- the supported operating voltage (operating voltage range) can be mutually confirmed between the host device 2 and the card 1 by using the voltage check command CMDV. The mutual confirmation method will be described in detail later.
- the host device 2 issues an initialization command CMDIO to the card 1. After this, Memory 1 initialization command is supplied. Memory initialization will be described in the second embodiment.
- FIG. 4 shows the main parts of the contents of the voltage check command CMDV.
- the voltage check command CM DV has at least a check pattern portion CPS and a voltage range identification portion VOLS.
- the voltage range identification unit VOLS has a pattern that uniquely indicates whether the host device 2 supports low voltage operation or high voltage operation.
- the number of bits of the check pattern portion CPS and the voltage range identification portion VOLS can be arbitrarily set. However, it is desirable that the following conditions are satisfied. That is, as will be described later, the host device 2 and the card 1 recognize each other's operating voltage range by examining whether the bit pattern of the voltage range identifying unit VOLS matches or does not match. For this reason, the check pattern portion CPS can be set to about 8 bits and the voltage range identification portion VOLS can be set to about 4 bits, for example.
- the command section CM is provided with an index for identifying this command.
- CRC Cyclic Redundancy Check
- Card 1 can detect an error in the voltage check command CMDV using the error detection code.
- FIG. 5 shows a main part of the response content of the voltage check command CMDV.
- the response of the voltage check command CMDV has at least a check pattern part CPA and a voltage range identification part VOLA.
- Card 1 forms the same bit pattern as the voltage check command CMDV in the check pattern section CPA, forms the same bit pattern as the voltage range identification section VOLS in the voltage range identification section VOLA, and returns a response to the host device.
- the response may be provided with the same error detection code part ED as in the case of the voltage check command CMDV.
- the host device 2 can detect an error in the response of the voltage check command CMDV by comparing the force using the error detection code and whether the response has the same pattern as the command.
- FIG. 6 is a flowchart showing the operation voltage range check process when the host device 2 operates in the high voltage range. As shown in FIG. 6, in step ST1, the host device 2 issues the voltage check command CMDV described above to the card 1.
- step ST2 the host device 2 determines whether or not there is a response to the voltage check command CMDV. As described above, since the conventional card does not recognize the voltage check command CMD V, it does not issue a response to this command. Therefore, the host device 2 determines that the card 1 is a conventional card, that is, the processing can be continued by the high voltage range operation, and shifts to a memory initialization process. Memory initialization will be described in the second embodiment.
- the card 1 when the card 1 being initialized is a card according to the present embodiment, the card 1 returns the response shown in FIG. At this time, the card 1 first observes the bit pattern of the voltage range identification unit VOLS of the voltage check command CMDV. A response having the same bit pattern in the voltage range identification unit VOLA is returned.
- step ST3 the host device 2 confirms a match between the pattern of the voltage range identification unit VO LA in the response and the pattern of the voltage range identification unit VOLS in the voltage check command CMDV. When these matches are confirmed, the host device 2 knows that the card 1 is a new card capable of recognizing the voltage check command CMDV and supports the operating voltage range of the host device 2.
- the host device 2 confirms that the CRC check or the response bit pattern matches the command bit pattern. Thereby, it can be confirmed that the transfer of the voltage check command CMDV is reliable.
- the correctness of the response is confirmed using, for example, the pattern of the error detection code part ED in the response as a CRC code.
- the voltage range identification part VOLS and the voltage range identification part VOLA, and the check pattern parts CPS and CPA of the command and response respectively match. It is determined that the response is normal. If the response is determined to be normal, the voltage check process ends. Thereafter, the flow proceeds to memory initialization processing. This will be described in the second embodiment.
- FIG. 7 is a flowchart showing the operation voltage range check process when the operation voltage of the host device 2 is within the low voltage range.
- the only difference from the high voltage range operation is the following. That is, if there is no response from card 1 in step ST2, it means that card 1 is a conventional card, that is, a high voltage card. Therefore, the initialization process stops to prevent the host device 2 operating in the low voltage range from processing the conventional card.
- the card 1 and the host device 2 know the operating voltage range supported by the other party by exchanging newly provided commands. be able to. For this reason, subsequent initialization processing can be performed in normal operation according to the operating voltage range supported by both the card 1 and the host device 2.
- the host device 2 can detect this and stop the initialization process. As a result, useless processing such as initialization in an abnormal state and host malfunction can be avoided.
- the voltage check command CMDV has a check pattern, and the card 1 forms the same pattern as this check pattern during the response of the voltage check command CMDV. . For this reason, by comparing these check patterns, it is assured that the transfer of the voltage check command CMDV is reliable. For this reason, even in the bus mode where no code error detector is provided in each command, Error in the application can be detected.
- the second embodiment relates to a memory initialization method according to whether a memory mounted on a card is a large capacity memory or a small capacity memory.
- a card 11 according to the second embodiment of the present invention includes a large capacity memory 13 and a card controller 14.
- the host device 12 includes a command control unit 17.
- the command control unit 17 supports a memory initialization command according to the second embodiment to be described later, and a conventional capacity card (small capacity card). And large capacity cards are both supported.
- the content of the memory initialization command differs depending on where the memory arrives in the flowchart of the first embodiment.
- the host device 12 has a function to issue the voltage check command CMDV. Is also supported. If the force being initialized is a conventional card, this corresponds to case (3) above. In this case, the host device 1 2 issues a conventional memory initialization command.
- the card controller 14 of the card 1 receives this memory initialization command, and initializes the memory according to the conventional format.
- FIG. 8 shows the main part of the contents of a new memory initialization command according to the second embodiment of the present invention.
- the memory initialization command includes a first voltage identification unit V1S, a second voltage identification unit V2S, a capacity identification unit HCS, and a busy notification unit BS.
- the first voltage identification unit V1S is composed of, for example, a plurality of bits, and each bit corresponds to a voltage having an appropriate width (for example, 0. IV).
- the voltage range supported by the first voltage identification unit V1S is the same as the high voltage operation range of the first embodiment.
- the host device 12 sets the bit indicating the currently applied voltage to “1”.
- the second voltage identification unit V2S includes 1 bit. Multiple bits are also possible.
- This bit is set when the host device 12 is applying a voltage in the low voltage range.
- the width of the voltage covered by each bit of the second voltage identification unit V2S can be smaller than that of the first voltage identification unit V1S, for example, 0.05 V can do. By doing this, even if the operating voltage of the host device and card further decreases in the future, it will be possible to show its own operating voltage more finely.
- the voltage range supported by the second voltage identification unit V2S is the same as the low voltage operation range of the first embodiment.
- An intermediate voltage range VM is provided between the voltage range covered by the first voltage identifying unit V1S and the voltage range covered by the second voltage identifying unit V2S.
- the host device 12 does not support the voltage range corresponding to the intermediate voltage range portion VM, and therefore, each bit in the intermediate voltage range portion VM cannot be “1”! /.
- the card controller 14 has a voltage regulator.
- the voltage regulator determines whether the power supply voltage from the host device 12 is a high voltage or a low voltage, and converts this power supply voltage into the operating voltage of the card 11. At this time, if the two operating voltage ranges are continuous, for example, when a voltage approximately in the middle of the two operating voltage ranges is supplied, it is difficult to determine the voltage regulator. This results in slow operation Become. On the other hand, by providing an unused area, the voltage regulator can easily determine the range to which the supply voltage belongs.
- the capacity identification unit HCS has a pattern indicating whether the host device 12 supports only a small capacity, both small capacity and large capacity.
- the busy notification unit BS is set to 0 or 1 in the response, and is unchanged (for example, “0”) in the command.
- the new memory initialization command may have an error detection unit ED that has the same power as a CRC code.
- FIG. 9 shows a main part of the response contents of the memory initialization command according to the second embodiment.
- each part of the response of the memory initialization command has the same format as the command, and includes the first voltage identification unit V1A, the second voltage identification unit V2A, the capacity identification unit HCA, and the busy notification unit BA. Contains.
- the first voltage identification unit VIA has the same number of bits as the first voltage identification unit V1S in the command, and sets all the bits corresponding to the operation voltage supported by itself to, for example, “1”.
- the second voltage identification unit V2A has the same number of bits as the second voltage identification unit V2S in the command.
- the card 11 sets all bits corresponding to the operating voltage supported by the card 11 to “1”, for example.
- the capacity identification unit HCA indicates whether the card 11 is a small capacity card or a large capacity card.
- the busy notification unit BS forms a bit pattern indicating that while the memory is being initialized.
- FIG. 10 is a flowchart showing a memory initialization process according to the second embodiment of the present invention.
- FIG. 10 shows the continuation of A and B in FIG. 6 and FIG.
- At least the card 11 and the host device 12 support the issue of the voltage check command CMDV as a condition for issuing the new memory initialization command. If the card 11 is a large capacity card, it is necessary to issue a new memory initialization command.
- step ST11 the host device 2 issues a new memory initialization command shown in FIG.
- the capacity identification part HCS of this command is set to a bit pattern indicating that the large capacity card is supported.
- the voltage check command CMDV and the memory initialization command (new memory initialization command) are not issued. If the card being initialized is a conventional card, it corresponds to the case of (1) above, and the card 11 is initialized in the conventional small capacity format by the conventional memory initialization command.
- the capacity identification unit HCS should have a bit pattern that does not support large capacity.
- the card 11 that supports large capacity that is, the capacity identification unit HCS can recognize that the bit pattern power also does not support the large capacity of the host device 2. In this case, it corresponds to the case (2) above, and the card 11 does not return a response to the memory initialization command in order to stop the initialization process. This prevents large capacity cards from being accidentally initialized by a small capacity format.
- step ST12 the host device 12 determines whether or not there is a response to the new memory initialization command. If there is no response, the process ends. If there is a response, in step ST13, the host device 12 checks the bit pattern of the capacity identification unit HCA in the response.
- the card 11 being initialized is a new card and should support large capacity, so a bit pattern to that effect appears. In other words, this case corresponds to the case of (4) above.
- step ST14 the host device 12 issues a new memory initialization command again.
- step ST15 the host device 12 checks the bit pattern of the busy notification unit B A in the response.
- the host device 12 continues to issue a memory initialization command until this bit pattern force memory initialization is completed and a pattern indicating that is obtained.
- the initialization of the memory 13 is started, only a response is returned, and the card 11 continues to ignore the contents of the memory initialization command itself.
- the host device 12 performs a time-out check with respect to the time during which the memory 13 is being initialized.
- the processing proceeds to further processing (for example, acquisition of the ID of the card 11).
- information on a small capacity card or a large capacity card is provided in the memory initialization command. Using this information, the host device 12 and the card 11 can confirm whether or not the other party supports a large capacity. Only when both the host device 12 and the card 11 support a large capacity, the memory 13 is initialized with the large capacity. If either one does not support large capacity, the initialization process is canceled. Therefore, malfunction can be prevented even when old and new host devices and old and new cards are mixed.
Abstract
Description
Claims
Priority Applications (27)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/017627 WO2006057049A1 (ja) | 2004-11-26 | 2004-11-26 | カードおよびホスト機器 |
TW094100263A TW200617797A (en) | 2004-11-26 | 2005-01-05 | Card and host device |
JP2006520563A JP4620049B2 (ja) | 2004-11-26 | 2005-11-25 | メモリデバイスおよびホスト機器 |
EP18153178.1A EP3330895A1 (en) | 2004-11-26 | 2005-11-25 | Card and host device |
PCT/JP2005/021689 WO2006057340A1 (ja) | 2004-11-26 | 2005-11-25 | カードおよびホスト機器 |
CA2563281A CA2563281C (en) | 2004-11-26 | 2005-11-25 | Card and host device |
KR1020097006198A KR100919072B1 (ko) | 2004-11-26 | 2005-11-25 | 카드 및 호스트 기기 |
BRPI0510243-0A BRPI0510243B1 (pt) | 2004-11-26 | 2005-11-25 | "Cartão e dispositivo hospedeiro" |
EP05809616.5A EP1816590B1 (en) | 2004-11-26 | 2005-11-25 | Card and host device |
RU2006137709/09A RU2365996C2 (ru) | 2004-11-26 | 2005-11-25 | Карточка и ведущее устройство |
KR1020067022176A KR20070047735A (ko) | 2004-11-26 | 2005-11-25 | 카드 및 호스트 기기 |
CN2005800131327A CN1947130B (zh) | 2004-11-26 | 2005-11-25 | 卡与主装置 |
TW094141585A TW200638271A (en) | 2004-11-26 | 2005-11-25 | Card and host device |
US11/553,002 US7353993B2 (en) | 2004-11-26 | 2006-10-26 | Card and host device |
US12/043,005 US7549580B2 (en) | 2004-11-26 | 2008-03-05 | Card and host device |
US12/468,886 US7810727B2 (en) | 2004-11-26 | 2009-05-20 | Card and host device |
US12/861,114 US7891566B2 (en) | 2004-11-26 | 2010-08-23 | Card and host device |
US13/010,346 US8162216B2 (en) | 2004-11-26 | 2011-01-20 | Card and host device |
US13/422,916 US8286874B2 (en) | 2004-11-26 | 2012-03-16 | Card and host device |
US13/614,749 US8397990B2 (en) | 2004-11-26 | 2012-09-13 | Card and host device |
US13/772,016 US8596548B2 (en) | 2004-11-26 | 2013-02-20 | Card and host device |
US14/079,130 US8827167B2 (en) | 2004-11-26 | 2013-11-13 | Card and host device |
US14/457,720 US9052843B2 (en) | 2004-11-26 | 2014-08-12 | Card and host device |
US14/700,411 US9417798B2 (en) | 2004-11-26 | 2015-04-30 | Card and host device |
US15/456,857 USRE47543E1 (en) | 2004-11-26 | 2017-03-13 | Card and host device |
US16/449,605 USRE48772E1 (en) | 2004-11-26 | 2019-06-24 | Card and host device |
US17/477,045 USRE49643E1 (en) | 2004-11-26 | 2021-09-16 | Card and host device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/017627 WO2006057049A1 (ja) | 2004-11-26 | 2004-11-26 | カードおよびホスト機器 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006057049A1 true WO2006057049A1 (ja) | 2006-06-01 |
Family
ID=36497798
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/017627 WO2006057049A1 (ja) | 2004-11-26 | 2004-11-26 | カードおよびホスト機器 |
PCT/JP2005/021689 WO2006057340A1 (ja) | 2004-11-26 | 2005-11-25 | カードおよびホスト機器 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/021689 WO2006057340A1 (ja) | 2004-11-26 | 2005-11-25 | カードおよびホスト機器 |
Country Status (10)
Country | Link |
---|---|
US (14) | US7353993B2 (ja) |
EP (2) | EP1816590B1 (ja) |
JP (1) | JP4620049B2 (ja) |
KR (2) | KR100919072B1 (ja) |
CN (1) | CN1947130B (ja) |
BR (1) | BRPI0510243B1 (ja) |
CA (1) | CA2563281C (ja) |
RU (1) | RU2365996C2 (ja) |
TW (2) | TW200617797A (ja) |
WO (2) | WO2006057049A1 (ja) |
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US10466771B2 (en) | 2004-12-27 | 2019-11-05 | Toshiba Memory Corporation | Card and host apparatus |
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