WO2006058332A2 - Reduced channel pitch in semiconductor device - Google Patents
Reduced channel pitch in semiconductor device Download PDFInfo
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- WO2006058332A2 WO2006058332A2 PCT/US2005/043115 US2005043115W WO2006058332A2 WO 2006058332 A2 WO2006058332 A2 WO 2006058332A2 US 2005043115 W US2005043115 W US 2005043115W WO 2006058332 A2 WO2006058332 A2 WO 2006058332A2
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- WIPO (PCT)
- Prior art keywords
- layer
- sloped sidewalls
- patterned mask
- semiconductor device
- etching
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000003491 array Methods 0.000 description 4
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- 230000003247 decreasing effect Effects 0.000 description 4
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- 238000007796 conventional method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000003292 diminished effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- -1 silicon nitride Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions
- the present invention relates to semiconductor devices and methods for decreasing a feature size of semiconductor devices. More particularly, the present invention relates to semiconductor devices and method for forming semiconductor devices with channel arrays having decreased line/space feature size and increased area for current flow. BACKGROUND
- MOSFETs metal-oxide-semiconductor field effect transistors
- One problem is that the gate oxide thickness must be reduced in proportion to the channel length to control short-channel effects and maintain a good subthreshold turn-off slope. As the thickness of the gate oxide decreases, quantum mechanical tunneling becomes a factor which leads to increased gate leakage.
- One solution to this problem is to form a corner dominated semiconductor device, which for a given oxide thickness, results in a steep subthreshold slope. Such a device should also be engineered to ensure that the effective area of current flow is not diminished.
- FIGS. 1A-1C show a conventional method of forming a triangular channel array.
- the conventional triangular channel array is made by forming a lithographic line pattern 30 on a silicon layer 20.
- a first isotropic etch removes a portion of silicon layer 20 to form a plurality of structures 23 having sloped sidewalls.
- a selective oxidation forms an SiO 2 layer 40 on the sloped sidewalls of structures 23.
- lithographic line pattern 30 is removed and a second isotropic etch is performed.
- the second isotropic etch removes another portion of structures 23 to form additional sloped sidewalls that, together with the sloped sidewalls formed from the first isotropic etch, form a conventional parallel triangular wire array 25.
- Conventional methods for forming corner dominated semiconductor devices are limited to forming only two triangles for each lithographic line pattern 30.
- the pitch of the resultant wire channel array is limited to two times the width of the lithographic line pattern, also called the "critical dimension.”
- the present teachings include a method of forming a semiconductor device including forming a patterned mask layer on a first layer, wherein the patterned mask layer has a first line width.
- the first layer can then be etched to form a first plurality of sloped walls.
- a portion of the patterned mask can be removed so that the patterned mask layer has a second line width less than the first line width.
- the first layer can be etched to form a second plurality of sloped walls and the patterned mask layer can be removed.
- the first layer can then be etched to form a third plurality of sloped walls, wherein the first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls form an array of parallel triangular channels.
- the present teachings also include a method of forming a semiconductor device including forming a patterned mask layer on a silicon layer, wherein the patterned mask layer has a first line width.
- the silicon layer can be anisotropically etched to form a first plurality of sloped sidewalls.
- An oxide layer can then be formed on the first plurality of sloped sidewalls.
- the patterned mask layer can be etched so that the patterned mask layer has a second line width less than the first line width.
- the first silicon layer can be anisotropically etched to form a second plurality of sloped sidewalls.
- An oxide layer can be formed on the second plurality of sloped sidewalls and the patterned mask layer can be removed.
- the silicon layer can be anisotropically etched to form a third plurality of sloped sidewalls, wherein the first plurality sloped walls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls form a triangular wire channel array.
- the present teachings further include a method of forming a semiconductor device including forming a patterned mask layer on a silicon layer, wherein the patterned mask layer has a first line width.
- the silicon layer can be anisotropically etched to expose a first plurality of (111) planes and an oxide layer can be formed on the exposed first plurality of (111) planes.
- the patterned mask layer can then be etched to decrease the line width.
- the silicon layer can be anisotropically etching to expose a second plurality of (1 1 1) planes and an oxide layer can be formed on the exposed second plurality of (111) planes.
- the patterned mask layer can be removed and the silicon layer anisotropically etched to expose a third plurality of (111) planes, wherein the first plurality of
- the present teachings also include a semiconductor device including a first layer and a plurality of parallel triangular channels disposed on the first layer.
- the plurality of parallel triangular channels can have a pitch that is less than a critical dimension (CD).
- FIGS. IA-C depict cross-sectional views of a conventional method for forming two triangular wires for each lithographic line.
- FIG. 2 depicts a cross-sectional view of patterned mask in a method for forming triangular wire channels in accordance with example embodiments of the invention.
- FIG. 3 depicts a cross-sectional view of a first plurality of sloped sidewalls formed in a method for forming triangular wire channels in accordance with example embodiments of the invention.
- FIG. 4 depicts a cross-sectional view of reducing a lithographic line width of a patterned mask layer in a method for forming triangular wire channels in accordance with example embodiments of the invention.
- FIG. 5 depicts a cross-sectional view of a second plurality of sloped sidewalls formed in a method for forming triangular wire channels in accordance with example embodiments of the invention.
- FIG. 6 depicts a cross-sectional view of a parallel triangular wire channel array in accordance with example embodiments of the invention.
- FIG. 7 depicts a cross-sectional view of a gate structure with a parallel triangular wire channel array in accordance with example embodiments of the invention.
- itch refers to the center-to-center distance between adjacent wire channels in a wire channel array.
- FIGS. 2 to 7 depict example semiconductor devices with parallel triangular wire channel arrays and manufacturing methods to form semiconductor devices with parallel triangular wire channel arrays in accordance with various embodiments of the invention.
- the semiconductor devices formed by the example methods can increase the number of corners and the area over which current flows compared to conventional comer dominated devices. Further, the steep subthreshold voltage slope (due to improved gate electrostatics) permits the removal of dopants from the channel which in turn improves the carrier mobility, thus resulting in increased drive currents.
- First layer 220 can be, for example, silicon.
- First layer 220 can be formed on second layer 210.
- Second layer 210 can be, for example, a silicon layer or a buried oxide layer and, in various embodiments, second layer 210 can be formed on a substrate (not shown).
- Patterned mask layer 230 can be formed on first layer 220 and can have a critical dimension, labeled CD, as shown in FIG. 2.
- Patterned mask 230 can be, for example, a nitride, such as silicon nitride, an oxide, such as silicon oxide, or a silicon oxy -nitride, and can be patterned by lithography techniques known to one of ordinary skill in the art.
- a first etch can be performed to remove a portion of first layer 220.
- the first etch can be an anisotropic etch that removes a portion of first layer 220 to form a first plurality of sloped sidewalls.
- the first plurality of sloped sidewalls can form structures 221.
- the term "sloped sidewall" refers to a sidewall not at 90° relative to an top surface of second layer 210.
- the first anisotropic etch can use, for example, tetramthylammonium-hydroxide (TMAH) as an etchant.
- TMAH tetramthylammonium-hydroxide
- the etchant can comprise potassium hydroxide.
- an etch of first layer 220 comprising, for example, silicon (Si) can stop at an edge of patterned mask 230.
- etching of the silicon slows as the Si (111) planes are exposed in the first layer and, due to the slow etch rate of the Si (111) planes, essentially stops once the Si (111) planes are exposed.
- the first plurality of sloped sidewalls can be formed by the exposed Si (11 1) planes, each having an angle of about 54.7° relative to a top surface of second layer 210.
- An oxide mask 240 such as, for example, SiO 2 can then be formed on each of the first plurality of sloped sidewalls, i.e., the exposed Si (111) planes.
- a portion of patterned mask layer 230 can then be removed.
- a hot phosphoric acid etch can be used to remove a portion of patterned mask layer 230, for example, comprising silicon nitride to form a patterned mask layer 231, as shown in the cross-sectional view of FIG. 4.
- plasma etching, and reactive ion etching can be used to remove a portion of patterned mask layer 230.
- the portion of patterned mask layer 230 can be removed so that the lithographic line width of patterned mask layer 231 can be less than the CD of patterned mask layer 230.
- a second anisotropic etch can then be performed.
- the second etch can remove another portion of first layer 220. Because oxide mask 240 and patterned mask layer 231 resist etching, formation of a second plurality of sloped sidewalls can occur.
- the second plurality of sloped sidewalls can form a plurality of structures 222 and a plurality of triangular structures 225, as shown in FIG. 5.
- each of the sloped sidewalls of structures 222 and triangular structures 225 can be exposed (111) planes of silicon.
- the second etch can be an anisotropic etch using an etchant comprising, for example, TMAH.
- oxide masks 240 can be formed on the second plurality of sloped sidewalls of structures 222 and triangular structures 225.
- Patterned mask layer 232 can then be removed.
- a hot phosphoric acid etch can be used to remove patterned mask layer 232.
- plasma etching, and reactive ion etching can be used to remove patterned mask layer 232.
- a third etch can then be performed to remove a further portion of first layer 220. Because oxide masks 240 resist etching, formation of a third plurality of sloped sidewalls occurs.
- the third plurality of sidewalls in conjunction with the first plurality of sloped sidewalls and the second plurality of sloped sidewalls, form a plurality of triangular structures 225, as shown in the cross-sectional view of FIG. 6.
- each of the sloped sidewalls of the third plurality of sloped sidewalls can be exposed (111) planes of silicon.
- the third etch can be an anisotropic etch that uses, for example, an etchant comprising TMAH.
- a semiconductor device such as, for example, a MOSFET or a junction field effect transistor (JFET) can include a gate structure including a silicon wire channel array comprising a plurality of parallel triangular wire channels.
- FIG. 7 shows a cross-sectional view of a triangular wire channel MOSFET 300 including a plurality of parallel triangular wire channels 325, buried oxide layer 310, a gate oxide 360, and a gate 375.
- a base of each of the plurality of wire channels 325 can be about 15 nm and each of the base angles can be about 54.7°.
- wire channel 300 can be formed using patterned mask 230 having a CD of about 45 nm.
- the line patterns of the patterned mask can be separated from each other by about 15nm.
- a width of patterned mask 230 can be reduced to about 15 nm to form patterned mask 231.
- Wire channel array 300 can, for example, increase an effective width over which current flows compared to a convention wire channel array.
- wire channel array 300 can have an increased number of corners compared to a conventional wire channel array, thus enabling further scaling of device size down to about 10 nm.
- a pitch of wire channel array 300 can also be increased to CD/2.
- One of ordinary skill in the art will understand that the above dimensions for triangular wire channels 225 and 325 are example and that the dimensions can be varied as required for particular semiconductor device characteristics.
- gate lengths can be decreased to 30 nm or less and drain induced barrier lowering (DIBL) can be 50 mV/V or less.
- DIBL refers to the change in the threshold voltage as the drain voltage is increased by one volt. It can be measured, for example, by extracting a change in the threshold voltage (V T ) at high and low drain voltages, and by normalizing the threshold voltage shift by the difference between the high and low drain voltage values.
- the subthreshold voltage swing can be 70 mV/dec or less.
- the pitch of the triangular wire channel array can be further multiplied, for example, by increasing the CD of the lithographic line pattern elements and/or decreasing the distance between each lithographic line pattern element.
- the method can proceed as described above, except that the steps of forming an oxide layer on the sloped sidewalls, reducing the lithographic line width of the patterned mask layer, and anisotropically etching the silicon layer can be repeated as necessary to multiply the pitch of the semiconductor device as desired.
- the pitch of a triangular channel array can be further multiplied so that six triangular channels can be formed from each lithographic line pattern element. Referring to FIG. 8, a patterned mask 830 having a CD of about 50 nm can be formed.
- the line patterns of the patterned mask can be separated from each other by about 10 nm.
- oxide layers 840 can be formed on the first plurality of sloped sidewalls and a width of patterned mask 830 can be reduced to about 30 nm to form patterned mask 831 as shown in FIG. 8B.
- a second etch can be performed to form a second plurality of sloped sidewalls.
- the second plurality of sloped sidewalls, with the first plurality of sloped sidewalls, can form triangular structures 825 and structures 822. Referring to FIG.
- oxide layers 840 can be formed on the second plurality of sloped sidewalls and the width of patterned mask 831 can be reduced to about 10 nm to form patterned mask 832.
- a third etch can be performed to form a third plurality of sloped sidewalls.
- the third plurality of sloped sidewalls, with the first plurality of sloped sidewalls and the second plurality of sloped sidewalls, can form triangular structures 825 and structures 823.
- Oxide layers 840 can be formed on the third plurality of sloped sidewalls and patterned mask 832 can then be removed, as shown in FIG. 8D.
- a fourth etch can be performed to form a fourth plurality of sloped sidewalls.
- the fourth plurality of sloped sidewalls, with the first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls, can form triangular structures 825.
- triangular structures 825 can form a triangular wire channel array with each triangular wire channel having a base of about 10 nm and base angles of about 54.7°.
- the pitch of the triangular wire channel array can be further multiplied by, for example, increasing the CD of each of the lithographic line pattern elements and performing additional steps of reducing the width of the lithographic line pattern elements, forming additional sloped sidewalls, and forming oxide layers on the sloped sidewalls.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05852401A EP1829114A4 (en) | 2004-11-29 | 2005-11-29 | Reduced channel pitch in semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/997,936 US7208379B2 (en) | 2004-11-29 | 2004-11-29 | Pitch multiplication process |
US10/997,936 | 2004-11-29 |
Publications (2)
Publication Number | Publication Date |
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WO2006058332A2 true WO2006058332A2 (en) | 2006-06-01 |
WO2006058332A3 WO2006058332A3 (en) | 2007-02-01 |
Family
ID=36498630
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/043115 WO2006058332A2 (en) | 2004-11-29 | 2005-11-29 | Reduced channel pitch in semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (1) | US7208379B2 (en) |
EP (1) | EP1829114A4 (en) |
KR (2) | KR20090077851A (en) |
CN (1) | CN101111941A (en) |
WO (1) | WO2006058332A2 (en) |
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-
2005
- 2005-11-29 EP EP05852401A patent/EP1829114A4/en not_active Withdrawn
- 2005-11-29 KR KR1020097011426A patent/KR20090077851A/en not_active Application Discontinuation
- 2005-11-29 KR KR1020077014918A patent/KR101073739B1/en active IP Right Grant
- 2005-11-29 CN CNA2005800473803A patent/CN101111941A/en active Pending
- 2005-11-29 WO PCT/US2005/043115 patent/WO2006058332A2/en active Application Filing
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See also references of EP1829114A4 |
Also Published As
Publication number | Publication date |
---|---|
CN101111941A (en) | 2008-01-23 |
US20060113636A1 (en) | 2006-06-01 |
EP1829114A2 (en) | 2007-09-05 |
US7208379B2 (en) | 2007-04-24 |
KR20090077851A (en) | 2009-07-15 |
EP1829114A4 (en) | 2009-04-08 |
KR101073739B1 (en) | 2011-10-13 |
KR20070086807A (en) | 2007-08-27 |
WO2006058332A3 (en) | 2007-02-01 |
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