WO2006061122A1 - Method of and system for delay estimation with minimized finger allocation - Google Patents
Method of and system for delay estimation with minimized finger allocation Download PDFInfo
- Publication number
- WO2006061122A1 WO2006061122A1 PCT/EP2005/012725 EP2005012725W WO2006061122A1 WO 2006061122 A1 WO2006061122 A1 WO 2006061122A1 EP 2005012725 W EP2005012725 W EP 2005012725W WO 2006061122 A1 WO2006061122 A1 WO 2006061122A1
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- WO
- WIPO (PCT)
- Prior art keywords
- delay
- profile
- cluster
- path
- signal path
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7113—Determination of path profile
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70757—Synchronisation aspects with code phase acquisition with increased resolution, i.e. higher than half a chip
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
- H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
Definitions
- the present invention relates generally to digital wireless communications systems in which delays of multi-path components of a time-varying fading channel are to be estimated, such as, for example, systems using RAKE receivers in Code Division Multiple Access (CDMA) systems.
- CDMA Code Division Multiple Access
- the invention is particularly suitable for, but is not limited to, receivers that operate in fading environments and have limited processing resources, such as those in Wideband CDMA (WCDMA) terminals.
- WCDMA Wideband CDMA
- a physical channel between a transmitter and a receiver is formed by a radio link.
- a transmit antenna is not narrowly focused towards the receiver and, in addition to a possible direct path, many other propagation paths exist between the transmitter and the receiver.
- the propagation paths are often caused by reflections from surrounding objects. Rays with similar propagation distances combine at the receiver depending on an instantaneous phase relationship and form a distinct multi-path component.
- the effect of the combining depends on an instantaneous relationship of a carrier wavelength and distance differences and, in the case of destructive interference, the combining leads to a significant reduction in path-gain magnitude (i.e., fading).
- Performance of a CDMA receiver is oftentimes improved if signal energy carried by many multi-path components is utilized via a RAKE receiver.
- a number of multi-path components are each assigned a despreader having a reference copy of a spreading code that is delayed equally to a path delay of a corresponding multi-path signal component.
- Outputs of the despreaders i.e., RAKE fingers
- the RAKE receiver requires knowledge of the multi-path delays and channel- impulse-response values for as many signal paths as possible.
- SNR signal- to-noise ratio
- signal energy from as many physical paths as possible should be collected.
- tracking of as many different physical paths as possible i.e., higher utilized diversity
- BLER block error rate
- FIGURE 1 is a block diagram of a typical RAKE receiver.
- a RAKE receiver 100 includes a delay estimator block 102, a channel estimator block 104, and a RAKE despreader/combiner block 106. Received data are fed to the delay estimator block 102.
- the delay estimator block 102 evaluates an impulse response of a channel over a range of possible delays of the channel. A resulting delay profile, which may be a complex delay profile or a power delay profile, may then be subjected to peak detection and detected peak locations reported to the RAKE despreader/combiner block 106 as delay estimates for the multi-path components.
- the delay estimates are also used by the channel estimator block 104 to estimate corresponding complex channel coefficients by despreading a pilot sequence and possibly filtering results over time to reduce the effects of noise and interference.
- Channel parameters are estimated in collaboration between the delay estimator block 102, which determines temporal alignment of a despreader portion of the RAKE despreader/combiner block 106, and the channel estimator block 104, which estimates the complex coefficients to be used by a combiner portion of the RAKE despreader/combiner block 106.
- a signal-path delay-estimation method includes correlating a computed coarse delay profile of at least one detected signal path cluster with a waveform to yield a strongest correlated peak for each of the at least one detected signal path cluster. The method also includes, for each of the at least one detected signal path cluster, using the strongest correlated peak to determine an adjusted delay-profile phase, re-sampling the computed coarse delay profile in accordance with the adjusted delay-profile phase, and detecting signal-path-cluster edges using the re-sampled computed coarse delay profile.
- An article of manufacture for signal-path delay estimation includes at least one computer readable medium and processor instructions contained on the at least one computer readable medium.
- the processor instructions are configured to be readable from the at least one computer readable medium by at least one processor and thereby cause the at least one processor to operate as to correlate a computed coarse delay profile of at least one detected signal path cluster with a waveform to yield a strongest correlated peak for each of the at least one detected signal path cluster and, for each of the at least one detected signal path cluster, use the strongest correlated peak to determine an adjusted delay-profile phase, re-sample the computed coarse delay profile in accordance with the adjusted delay- profile phase, and detect signal-path-cluster edges using the re-sampled computed coarse delay profile.
- a signal-path delay-estimation system includes a delay estimator for correlating a computed delay profile of at least one detected signal path cluster with a waveform to yield a strongest correlated peak for each of the at least one detected signal path cluster.
- the delay estimator is also for, for each of the at least one detected signal path cluster, using the strongest correlated peak to determine an adjusted delay-profile phase, re-sampling the computed delay profile in accordance with the adjusted delay-profile phase, and detecting signal-path-cluster edges using the re-sampled computed delay profile.
- the system also includes a channel estimator inter-operably connected to an output of the delay estimator and a despreader/combiner inter-operably connected to an output of the channel estimator and the output of the delay estimator.
- FIGURE 1 previously described, is a block diagram of a typical RAKE receiver
- FIGURE 2 is a flow chart that illustrates a delay-estimation process.
- peak-detection-oriented DE Two approaches to delay estimation (DE) are as follows: 1) peak-detection-oriented DE; and 2) fixed-grid DE.
- peak-detection-oriented DE a precise position (i.e., a delay) of a particular multi-path component is estimated in order to tune a respective despreader precisely to the estimated delay.
- peak-detection-oriented DE involves evaluating a channel impulse response over an entire range of possible delays (i.e., delay spread) of the channel in question. A resulting complex delay profile (CDP) or power delay profile (PDP) may then be subjected to peak detection. The peak locations (di) are reported to the RAKE receiver as delay estimates.
- CDP complex delay profile
- PDP power delay profile
- PS path searchers
- a full search area i.e., maximal assumed delay spread
- reduced PS resolution e.g., 1 chip
- Additional densely-sampled windows of despreaders may be used that produce higher-resolution (e.g., 1/4 chip) estimates of certain areas of the PDP for precise reporting of delays.
- Fixed-grid DE is based on the principle that, in order to capture all available signal energy, it is not necessary to place RAKE fingers exactly on path positions. It is instead sufficient to lay a grid of fingers with a certain minimal spacing, equal to the Nyquist sampling rate of the received signal, over a delay-domain area where a dominant portion of the signal energy lies.
- T the grid spacing
- T c 3/4J c
- k an integer value.
- While fixed-grid DE does not attempt to estimate the precise delays of the individual components, the delay list at its output provides similar information to that provided by peak-detection-oriented DE.
- the delay list provided by either fixed-grid DE or peak- detection-oriented DE is used identically by subsequent RAKE-receiver blocks.
- Peak-detection-oriented DE provides an economical despreading arrangement if, for example, the channel consists of a single well-defined path. A location of the single path may then be detected relatively easily and precisely and a single RAKE finger may extract all available energy. In similar fashion, if the channel consists of several separated well- defined paths and the peak detection may be applied to each of them, peak-detection- oriented DE is quite economical.
- the channel if the channel consists of a closely-spaced cluster of paths, it may be difficult to identify individual path positions, since signal energy from the different paths typically overlaps due to side lobes of transmit/receive ("tx/rx") filters.
- tx/rx transmit/receive
- the physical-path delays may remain constant, multi-path fading and a constantly-changing complex combining pattern of neighboring paths often causes a constant fluctuation of the observed PDP; therefore, tracking of the apparently-changing, but actually physically-fixed, delay positions can be quite challenging.
- Resulting difficulties for a DE process oftentimes create a need for heuristic mechanisms to avoid various pathological behaviors.
- the heuristic mechanisms can serve to tune the DE process to special cases and reduce the general applicability of the process. If an attempt is made to catch a path with a single finger, and the finger is misplaced even by 1/4 chip or 1/2 chip, a significant portion of the path energy is lost, and the interference is increased.
- m + 1 fingers are needed.
- the number of necessary m + 1 fingers is always greater than for peak-detection-oriented DE, and may be as much as twice the number of fingers used in peak-detection-oriented DE if the delay profile contains only stand-alone paths. For an extended path cluster, the extra expenditure of fingers is negligible.
- a DE approach is used that allows non- peak-specific finger positions for multi-peak clusters, while avoiding mis-sampling and wasted fingers under single-path circumstances.
- a DE process applies fixed-grid finger placement to each PDP path cluster, while a grid offset is adjusted individually for each cluster, thereby allowing sampling-phase optimization for single-peak objects in the PDP, avoiding placement of unnecessary fingers, and maintaining robust coverage of extended clusters.
- a mechanism detects the proper sampling phase for a given cluster by correlating the PDP of the cluster with a single-path PDP or other waveform at various sampling offsets; if a peak is found in the filtering result, the fixed grid phase for the given cluster is adjusted without affecting the phase of the other clusters.
- Various embodiments of the invention allow handling of single-path-dominated clusters efficiently as single paths without requiring a heuristic decision operation on each signal cluster.
- FIGURE 2 is a flow chart that illustrates a delay-estimation process 200.
- T s an input data sampling period
- TJA TJA
- T c a CDMA chip period
- T 3TJ4
- the DE process 200 may report as many as P paths.
- the DE process 200 begins at step 202.
- the boundary detection performed at step 202 may be implemented as, for example, a thresholding operation requiring that a signal-path cluster element be greater than a pre-defined value, such as, for example, two times stronger than a PDP noise floor.
- step 204 a counter j is started at an initial value of zero.
- step 206 the counter j is incremented.
- step 208 a determination is made whether the counter j has exceeded the pre-defined value J, J being the number of previously-detected signal clusters from step 202. If, at step 208, it is not determined that the counter has exceeded /, execution proceeds to step 210.
- steps 210-218 are performed for j - 1 . . . / (i.e., for each signal path cluster).
- steps 210-218 are illustrated in FIG. 2 as being performed sequentially, those having ordinary skill in the art will appreciate that steps 210-218 may also be performed in parallel without departing from principles of the invention.
- the signal path cluster under consideration i.e., signal path cluster j
- the waveform may be, for example, a single-path PDP waveform or the response of a filter implementing the inverse of a single-path pulse shaping operation.
- step 212 execution proceeds to step 214.
- step 214 the PDP of clustery is
- step 214 execution proceeds to step 216.
- step 218 execution proceeds to step 218.
- step 218 a position list Dj ] and a corresponding -S-
- PDP value list G g k , , k ' and ⁇ *... ⁇ ht * are reported for the cluster ;. From step 218, execution returns to step 206.
- step 208 If, at step 208, it is determined that j > J, execution proceeds to step 220.
- the PDP generation may be performed for the original fixed grid positions kT at all times in order to simplify, for example, a hardware implementation, as the re-sampling provides the necessary shift per cluster.
- the correlation may be done rarely, for example, every N-th DE update cycles, where N is chosen so as to limit path movement/drift during the NT DE slots to a distance less than T S ⁇ where T DE is the time corresponding to a DE update cycle.
- the grid phase correction is helpful if a clear correlation peak exists (i.e., a single defined peak exists in the cluster), while in the absence of a clear peak near the edge of the cluster, the correction does not necessarily noticeably improve the finger-allocation economy. Therefore, in some embodiments, processing resources may be saved by an implementation that performs the re-sampling and edge re- detection only if a correlation peak is found at a cluster edge. Furthermore, in some embodiments of the invention, a procedure targeting only single-path objects in the PDP for re-sampling may skip all processing for clusters wider than the single-path PDP waveform.
- a CDP may be used instead of a PDP, in which case the power of each delay profile element is found by multiplying the complex coefficient by its complex conjugate.
- Edge detection criteria and threshold values other than those described above may be used without departing from principles of the invention.
- the PDP may be computed for the adjusted delay positions; if so, no PDP re-sampling is needed in many cases.
- Correlation peak detection periods may be equal to or different from the DE update period. Different criteria for processing individual PDP clusters may be used.
- Various embodiments of the present invention may be implemented in, for example, hardware, software (e.g., carried out by a processor that executes computer-readable instructions), or a combination thereof.
- the computer-readable instructions may be program code loaded in a memory such as, for example, Random Access Memory (RAM), or from a storage medium such as, for example, Read Only Memory (ROM).
- RAM Random Access Memory
- ROM Read Only Memory
- a processor may be operative to execute software adapted to perform a series of steps in accordance with principles of the present invention.
- the software may be adapted to reside upon a computer-readable medium such as, for example, a magnetic disc within a disc drive unit.
- the computer-readable medium may also include a flash memory card, EEROM based memory, bubble memory storage, ROM storage, etc.
- the software adapted to perform steps according to principles of the present invention may also reside, in whole or in part, in static or dynamic main memories or in firmware within a processor (e.g., within microcontroller, microprocess
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05825754.4A EP1825604B1 (en) | 2004-12-08 | 2005-11-29 | Method of and system for delay estimation with minimized finger allocation |
JP2007544773A JP4838262B2 (en) | 2004-12-08 | 2005-11-29 | Method and system for estimating delay with minimal finger assignment |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/007,687 US7372895B2 (en) | 2004-12-08 | 2004-12-08 | Method of and system for delay estimation with minimized finger allocation |
US11/007,687 | 2004-12-08 |
Publications (1)
Publication Number | Publication Date |
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WO2006061122A1 true WO2006061122A1 (en) | 2006-06-15 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2005/012725 WO2006061122A1 (en) | 2004-12-08 | 2005-11-29 | Method of and system for delay estimation with minimized finger allocation |
Country Status (6)
Country | Link |
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US (1) | US7372895B2 (en) |
EP (1) | EP1825604B1 (en) |
JP (1) | JP4838262B2 (en) |
KR (1) | KR20070087645A (en) |
CN (1) | CN101116256A (en) |
WO (1) | WO2006061122A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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DE602004024280D1 (en) * | 2004-01-05 | 2010-01-07 | St Microelectronics Nv | Method for suppressing false echoes in a rake receiver |
JP4555332B2 (en) * | 2005-02-25 | 2010-09-29 | 日本電気株式会社 | Transmission path estimation apparatus, CDMA reception apparatus, and transmission path estimation method |
AU2010324545A1 (en) * | 2009-11-27 | 2012-07-19 | Cohda Wireless Pty Ltd | Extracting parameters from a communications channel |
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Also Published As
Publication number | Publication date |
---|---|
JP4838262B2 (en) | 2011-12-14 |
JP2008523668A (en) | 2008-07-03 |
EP1825604B1 (en) | 2013-10-02 |
KR20070087645A (en) | 2007-08-28 |
EP1825604A1 (en) | 2007-08-29 |
US7372895B2 (en) | 2008-05-13 |
US20060120440A1 (en) | 2006-06-08 |
CN101116256A (en) | 2008-01-30 |
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