WO2006065698A3 - Sense amplifier circuitry and architecture to write data into and/or read data from memory cells - Google Patents

Sense amplifier circuitry and architecture to write data into and/or read data from memory cells Download PDF

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Publication number
WO2006065698A3
WO2006065698A3 PCT/US2005/044791 US2005044791W WO2006065698A3 WO 2006065698 A3 WO2006065698 A3 WO 2006065698A3 US 2005044791 W US2005044791 W US 2005044791W WO 2006065698 A3 WO2006065698 A3 WO 2006065698A3
Authority
WO
WIPO (PCT)
Prior art keywords
read
memory cells
sense amplifier
circuitry
data
Prior art date
Application number
PCT/US2005/044791
Other languages
French (fr)
Other versions
WO2006065698A2 (en
WO2006065698A8 (en
Inventor
William Kenneth Waller
Eric Carman
Original Assignee
William Kenneth Waller
Eric Carman
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by William Kenneth Waller, Eric Carman filed Critical William Kenneth Waller
Publication of WO2006065698A2 publication Critical patent/WO2006065698A2/en
Publication of WO2006065698A8 publication Critical patent/WO2006065698A8/en
Publication of WO2006065698A3 publication Critical patent/WO2006065698A3/en

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065Differential amplifiers of latching type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/20DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4099Dummy cell treatment; Reference voltage generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4013Memory devices with multiple cells per bit, e.g. twin-cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016Memory devices with silicon-on-insulator cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14Dummy cell management; Sense reference voltage generators

Abstract

A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or 're-store' the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array. The sense amplifier circuitry of this embodiment restores and/or refreshes data in an entire row of volatile and/or destructive read type memory cells in parallel. This architecture may minimize, enhance and/or improve write back and read latency parameters, relative to at least architecture employing multiplexer circuitry. Also, data that has been read, sampled and/or sensed by the sense amplifier circuitry during a read operation may be modified before being written back to one or more of the memory cells of the selected row of the array of memory cells.
PCT/US2005/044791 2004-12-13 2005-12-12 Sense amplifier circuitry and architecture to write data into and/or read data from memory cells WO2006065698A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63570904P 2004-12-13 2004-12-13
US60/635,709 2004-12-13

Publications (3)

Publication Number Publication Date
WO2006065698A2 WO2006065698A2 (en) 2006-06-22
WO2006065698A8 WO2006065698A8 (en) 2006-08-17
WO2006065698A3 true WO2006065698A3 (en) 2006-10-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/044791 WO2006065698A2 (en) 2004-12-13 2005-12-12 Sense amplifier circuitry and architecture to write data into and/or read data from memory cells

Country Status (2)

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US (2) US7301838B2 (en)
WO (1) WO2006065698A2 (en)

Families Citing this family (272)

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US7301838B2 (en) 2007-11-27
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US7486563B2 (en) 2009-02-03
WO2006065698A8 (en) 2006-08-17

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