WO2006075725A3 - Manufacturing method for semiconductor chips and semiconductor wafer - Google Patents

Manufacturing method for semiconductor chips and semiconductor wafer Download PDF

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Publication number
WO2006075725A3
WO2006075725A3 PCT/JP2006/300409 JP2006300409W WO2006075725A3 WO 2006075725 A3 WO2006075725 A3 WO 2006075725A3 JP 2006300409 W JP2006300409 W JP 2006300409W WO 2006075725 A3 WO2006075725 A3 WO 2006075725A3
Authority
WO
WIPO (PCT)
Prior art keywords
teg
regions
semiconductor
protective sheet
semiconductor wafer
Prior art date
Application number
PCT/JP2006/300409
Other languages
French (fr)
Other versions
WO2006075725A2 (en
Inventor
Kiyoshi Arita
Teruaki Nishinaka
Original Assignee
Matsushita Electric Ind Co Ltd
Kiyoshi Arita
Teruaki Nishinaka
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, Kiyoshi Arita, Teruaki Nishinaka filed Critical Matsushita Electric Ind Co Ltd
Priority to EP06711691A priority Critical patent/EP1839333A2/en
Priority to KR1020077012170A priority patent/KR101179283B1/en
Publication of WO2006075725A2 publication Critical patent/WO2006075725A2/en
Publication of WO2006075725A3 publication Critical patent/WO2006075725A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. And, a protective sheet is stuck to the semiconductor wafer, then plasma etching is performed, and the TEG in a state where it remains in the dividing region and stuck to the protective sheet is removed together with the protective sheet by peeling off the protective sheet, thereby the device-formation-regions are divided into individual pieces, and the semiconductor chips are manufactured.
PCT/JP2006/300409 2005-01-12 2006-01-10 Manufacturing method for semiconductor chips and semiconductor wafer WO2006075725A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06711691A EP1839333A2 (en) 2005-01-12 2006-01-10 Manufacturing method for semiconductor chips and semiconductor wafer
KR1020077012170A KR101179283B1 (en) 2005-01-12 2006-01-10 Manufacturing method for semiconductor chips and semiconductor wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005-004860 2005-01-12
JP2005004860A JP4338650B2 (en) 2005-01-12 2005-01-12 Manufacturing method of semiconductor chip

Publications (2)

Publication Number Publication Date
WO2006075725A2 WO2006075725A2 (en) 2006-07-20
WO2006075725A3 true WO2006075725A3 (en) 2007-02-08

Family

ID=36591380

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/300409 WO2006075725A2 (en) 2005-01-12 2006-01-10 Manufacturing method for semiconductor chips and semiconductor wafer

Country Status (7)

Country Link
US (1) US7989803B2 (en)
EP (1) EP1839333A2 (en)
JP (1) JP4338650B2 (en)
KR (1) KR101179283B1 (en)
CN (1) CN100505211C (en)
TW (1) TW200636842A (en)
WO (1) WO2006075725A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4840174B2 (en) * 2007-02-08 2011-12-21 パナソニック株式会社 Manufacturing method of semiconductor chip
US8658436B2 (en) * 2010-04-19 2014-02-25 Tokyo Electron Limited Method for separating and transferring IC chips
US8802545B2 (en) * 2011-03-14 2014-08-12 Plasma-Therm Llc Method and apparatus for plasma dicing a semi-conductor wafer
US9343365B2 (en) * 2011-03-14 2016-05-17 Plasma-Therm Llc Method and apparatus for plasma dicing a semi-conductor wafer
US8877610B2 (en) * 2011-06-20 2014-11-04 Infineon Technologies Ag Method of patterning a substrate
US10186458B2 (en) * 2012-07-05 2019-01-22 Infineon Technologies Ag Component and method of manufacturing a component using an ultrathin carrier
KR102104334B1 (en) * 2013-09-04 2020-04-27 삼성디스플레이 주식회사 Method for manufacturing organic light emitting diode display
JP6315470B2 (en) * 2014-09-10 2018-04-25 株式会社ディスコ Split method
JP2016058578A (en) * 2014-09-10 2016-04-21 株式会社ディスコ Division method
WO2019106846A1 (en) * 2017-12-01 2019-06-06 日立化成株式会社 Semiconductor device manufacturing method, resin composition for temporary fixation material, laminated film for temporary fixation material
JP6934573B2 (en) * 2018-08-01 2021-09-15 平田機工株式会社 Transport device and control method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329700B1 (en) * 1998-10-13 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor wafer and semiconductor device
US20020111028A1 (en) * 2001-02-13 2002-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device as well as reticle and wafer used therein
JP2002231659A (en) * 2001-02-05 2002-08-16 Hitachi Ltd Method for manufacturing semiconductor device
US20020192928A1 (en) * 2001-06-13 2002-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor chip and its manufacturing method
JP2003234312A (en) * 2002-02-07 2003-08-22 Hitachi Ltd Method for manufacturing semiconductor device

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
JPS6035514A (en) 1983-08-08 1985-02-23 Hitachi Micro Comput Eng Ltd Photolithographic pattern
JPH05326696A (en) 1992-05-25 1993-12-10 Sanyo Electric Co Ltd Semiconductor wafer
JP3434593B2 (en) 1994-10-20 2003-08-11 株式会社日立製作所 Method for manufacturing semiconductor device
JP4301584B2 (en) * 1998-01-14 2009-07-22 株式会社ルネサステクノロジ Reticle, exposure apparatus using the same, exposure method, and semiconductor device manufacturing method
JP3065309B1 (en) * 1999-03-11 2000-07-17 沖電気工業株式会社 Method for manufacturing semiconductor device
JP2000340746A (en) * 1999-05-26 2000-12-08 Yamaha Corp Semiconductor device
JP2001060568A (en) 1999-08-20 2001-03-06 Seiko Epson Corp Method of manufacturing semiconductor device
JP3726711B2 (en) * 2001-05-31 2005-12-14 セイコーエプソン株式会社 Semiconductor device
JP3966168B2 (en) 2002-11-20 2007-08-29 松下電器産業株式会社 Manufacturing method of semiconductor device
US6897128B2 (en) * 2002-11-20 2005-05-24 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device, plasma processing apparatus and plasma processing method
JP3991872B2 (en) 2003-01-23 2007-10-17 松下電器産業株式会社 Manufacturing method of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329700B1 (en) * 1998-10-13 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor wafer and semiconductor device
JP2002231659A (en) * 2001-02-05 2002-08-16 Hitachi Ltd Method for manufacturing semiconductor device
US20020111028A1 (en) * 2001-02-13 2002-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device as well as reticle and wafer used therein
US20020192928A1 (en) * 2001-06-13 2002-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor chip and its manufacturing method
JP2003234312A (en) * 2002-02-07 2003-08-22 Hitachi Ltd Method for manufacturing semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2002, no. 12 12 December 2002 (2002-12-12) *
PATENT ABSTRACTS OF JAPAN vol. 2003, no. 12 5 December 2003 (2003-12-05) *

Also Published As

Publication number Publication date
JP2006196573A (en) 2006-07-27
KR101179283B1 (en) 2012-09-03
CN101103454A (en) 2008-01-09
US7989803B2 (en) 2011-08-02
EP1839333A2 (en) 2007-10-03
KR20070102663A (en) 2007-10-19
US20080128694A1 (en) 2008-06-05
WO2006075725A2 (en) 2006-07-20
CN100505211C (en) 2009-06-24
TW200636842A (en) 2006-10-16
JP4338650B2 (en) 2009-10-07

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