WO2006076087A3 - METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS - Google Patents

METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS Download PDF

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Publication number
WO2006076087A3
WO2006076087A3 PCT/US2005/043555 US2005043555W WO2006076087A3 WO 2006076087 A3 WO2006076087 A3 WO 2006076087A3 US 2005043555 W US2005043555 W US 2005043555W WO 2006076087 A3 WO2006076087 A3 WO 2006076087A3
Authority
WO
WIPO (PCT)
Prior art keywords
hfsin
forming
interfacial layer
metal
fet applications
Prior art date
Application number
PCT/US2005/043555
Other languages
French (fr)
Other versions
WO2006076087A2 (en
Inventor
Alessandro C Callegari
Martin M Frank
Rajarao Jammy
Dianne L Lacey
Fenton R Mcfeely
Sufi Zafar
Original Assignee
Ibm
Alessandro C Callegari
Martin M Frank
Rajarao Jammy
Dianne L Lacey
Fenton R Mcfeely
Sufi Zafar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Alessandro C Callegari, Martin M Frank, Rajarao Jammy, Dianne L Lacey, Fenton R Mcfeely, Sufi Zafar filed Critical Ibm
Priority to JP2007551254A priority Critical patent/JP5160238B2/en
Priority to EP05826298A priority patent/EP1836732B1/en
Priority to CN2005800465277A priority patent/CN101401211B/en
Priority to AT05826298T priority patent/ATE526684T1/en
Publication of WO2006076087A2 publication Critical patent/WO2006076087A2/en
Publication of WO2006076087A3 publication Critical patent/WO2006076087A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.
PCT/US2005/043555 2005-01-13 2005-12-02 METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS WO2006076087A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007551254A JP5160238B2 (en) 2005-01-13 2005-12-02 Method for forming HfSiN metal for n-FET applications
EP05826298A EP1836732B1 (en) 2005-01-13 2005-12-02 Semiconductor structure comprising a HfSiN metal gate and method of forming the same
CN2005800465277A CN101401211B (en) 2005-01-13 2005-12-02 Semiconductor structure used for n-FET application
AT05826298T ATE526684T1 (en) 2005-01-13 2005-12-02 SEMICONDUCTOR STRUCTURE HAVING A HFSIN METALLIC GATE AND MANUFACTURING METHOD

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/035,369 2005-01-13
US11/035,369 US20060151846A1 (en) 2005-01-13 2005-01-13 Method of forming HfSiN metal for n-FET applications

Publications (2)

Publication Number Publication Date
WO2006076087A2 WO2006076087A2 (en) 2006-07-20
WO2006076087A3 true WO2006076087A3 (en) 2008-11-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/043555 WO2006076087A2 (en) 2005-01-13 2005-12-02 METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS

Country Status (7)

Country Link
US (3) US20060151846A1 (en)
EP (1) EP1836732B1 (en)
JP (1) JP5160238B2 (en)
CN (2) CN101789370B (en)
AT (1) ATE526684T1 (en)
TW (1) TW200636870A (en)
WO (1) WO2006076087A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060151846A1 (en) * 2005-01-13 2006-07-13 International Business Machines Corporation Method of forming HfSiN metal for n-FET applications
JP2006245461A (en) * 2005-03-07 2006-09-14 Sony Corp Semiconductor device and its manufacturing method
US7301219B2 (en) * 2005-06-06 2007-11-27 Macronix International Co., Ltd. Electrically erasable programmable read only memory (EEPROM) cell and method for making the same
JP4455427B2 (en) * 2005-06-29 2010-04-21 株式会社東芝 Semiconductor device and manufacturing method thereof
US7425497B2 (en) * 2006-01-20 2008-09-16 International Business Machines Corporation Introduction of metal impurity to change workfunction of conductive electrodes
US7611979B2 (en) 2007-02-12 2009-11-03 International Business Machines Corporation Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks
US7648868B2 (en) * 2007-10-31 2010-01-19 International Business Machines Corporation Metal-gated MOSFET devices having scaled gate stack thickness
EP2123789A1 (en) * 2008-05-15 2009-11-25 Eifeler Werkzeuge GmbH A method of producing hard coatings
US8350341B2 (en) 2010-04-09 2013-01-08 International Business Machines Corporation Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG)
US8633534B2 (en) * 2010-12-22 2014-01-21 Intel Corporation Transistor channel mobility using alternate gate dielectric materials
US8916427B2 (en) * 2013-05-03 2014-12-23 Texas Instruments Incorporated FET dielectric reliability enhancement
KR102392059B1 (en) * 2013-07-29 2022-04-28 삼성전자주식회사 Semiconductor device and method of fabricating the same
CN106158601A (en) * 2015-03-26 2016-11-23 比亚迪股份有限公司 The gate dielectric layer structure of SiC base device and the forming method of gate dielectric layer
CN105448742B (en) * 2015-12-30 2019-02-26 东莞市义仁汽车租赁有限公司 The method of gate medium is prepared on a kind of carbofrax material
US10446400B2 (en) * 2017-10-20 2019-10-15 Samsung Electronics Co., Ltd. Method of forming multi-threshold voltage devices and devices so formed
CN110993603A (en) * 2019-12-09 2020-04-10 中国科学院微电子研究所 Semiconductor structure and forming method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050026459A1 (en) * 2003-07-31 2005-02-03 Tokyo Electron Limited Method of forming uniform ultra-thin oxynitride layers
US20050258500A1 (en) * 2004-05-24 2005-11-24 Texas Instruments, Incorporated Refractory metal-based electrodes for work function setting in semiconductor devices

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861356B2 (en) * 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US6313539B1 (en) * 1997-12-24 2001-11-06 Sharp Kabushiki Kaisha Semiconductor memory device and production method of the same
US6413386B1 (en) * 2000-07-19 2002-07-02 International Business Machines Corporation Reactive sputtering method for forming metal-silicon layer
JP2003069011A (en) * 2001-08-27 2003-03-07 Hitachi Ltd Semiconductor device and method of manufacturing the same
US20030111678A1 (en) * 2001-12-14 2003-06-19 Luigi Colombo CVD deposition of M-SION gate dielectrics
US6797525B2 (en) * 2002-05-22 2004-09-28 Agere Systems Inc. Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process
AU2003273328A1 (en) * 2002-09-18 2004-04-08 Infineon Technologies Ag Nitride and polysilicon interface with titanium layer
US6858524B2 (en) * 2002-12-03 2005-02-22 Asm International, Nv Method of depositing barrier layer for metal gates
CN1263147C (en) * 2002-12-09 2006-07-05 旺宏电子股份有限公司 Structure and manufacture of ROM with tunneling dielectric layer of high dielectric constant
US6803611B2 (en) * 2003-01-03 2004-10-12 Texas Instruments Incorporated Use of indium to define work function of p-type doped polysilicon
JP2004221467A (en) * 2003-01-17 2004-08-05 Fujitsu Ltd Semiconductor device, and manufacturing method thereof
US6852645B2 (en) * 2003-02-13 2005-02-08 Texas Instruments Incorporated High temperature interface layer growth for high-k gate dielectric
JP4489368B2 (en) * 2003-03-24 2010-06-23 株式会社日立製作所 Semiconductor device and manufacturing method thereof
JP2005005603A (en) * 2003-06-13 2005-01-06 Toshiba Corp Semiconductor device and its manufacturing method
WO2005013348A2 (en) * 2003-07-31 2005-02-10 Tokyo Electron Limited Formation of ultra-thin oxide and oxynitride layers by self-limiting interfacial oxidation
US6974779B2 (en) * 2003-09-16 2005-12-13 Tokyo Electron Limited Interfacial oxidation process for high-k gate dielectric process integration
JP3790242B2 (en) * 2003-09-26 2006-06-28 株式会社東芝 Semiconductor device and manufacturing method thereof
US7351626B2 (en) * 2003-12-18 2008-04-01 Texas Instruments Incorporated Method for controlling defects in gate dielectrics
US7737051B2 (en) * 2004-03-10 2010-06-15 Tokyo Electron Limited Silicon germanium surface layer for high-k dielectric integration
JP2005317647A (en) * 2004-04-27 2005-11-10 Toshiba Corp Semiconductor device and its fabrication process
US8399934B2 (en) * 2004-12-20 2013-03-19 Infineon Technologies Ag Transistor device
US7282773B2 (en) * 2004-09-14 2007-10-16 Advanced Micro Devices Inc. Semiconductor device with high-k dielectric layer
US20060068603A1 (en) * 2004-09-30 2006-03-30 Tokyo Electron Limited A method for forming a thin complete high-permittivity dielectric layer
US7361608B2 (en) * 2004-09-30 2008-04-22 Tokyo Electron Limited Method and system for forming a feature in a high-k layer
JP2006114747A (en) * 2004-10-15 2006-04-27 Seiko Epson Corp Method for manufacturing semiconductor device
US20060151846A1 (en) * 2005-01-13 2006-07-13 International Business Machines Corporation Method of forming HfSiN metal for n-FET applications

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050026459A1 (en) * 2003-07-31 2005-02-03 Tokyo Electron Limited Method of forming uniform ultra-thin oxynitride layers
US20050258500A1 (en) * 2004-05-24 2005-11-24 Texas Instruments, Incorporated Refractory metal-based electrodes for work function setting in semiconductor devices

Also Published As

Publication number Publication date
ATE526684T1 (en) 2011-10-15
JP2008530770A (en) 2008-08-07
EP1836732A2 (en) 2007-09-26
JP5160238B2 (en) 2013-03-13
CN101789370B (en) 2012-05-30
TW200636870A (en) 2006-10-16
US7521346B2 (en) 2009-04-21
EP1836732A4 (en) 2009-07-01
CN101789370A (en) 2010-07-28
US20060151846A1 (en) 2006-07-13
US20080245658A1 (en) 2008-10-09
US20080038905A1 (en) 2008-02-14
CN101401211B (en) 2012-03-21
WO2006076087A2 (en) 2006-07-20
CN101401211A (en) 2009-04-01
EP1836732B1 (en) 2011-09-28

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