WO2006088527A3 - A semiconductor substrate processing method - Google Patents

A semiconductor substrate processing method Download PDF

Info

Publication number
WO2006088527A3
WO2006088527A3 PCT/US2005/042863 US2005042863W WO2006088527A3 WO 2006088527 A3 WO2006088527 A3 WO 2006088527A3 US 2005042863 W US2005042863 W US 2005042863W WO 2006088527 A3 WO2006088527 A3 WO 2006088527A3
Authority
WO
WIPO (PCT)
Prior art keywords
coordinate system
semiconductor substrate
substrate processing
offset
processing method
Prior art date
Application number
PCT/US2005/042863
Other languages
French (fr)
Other versions
WO2006088527A2 (en
Inventor
Alger C Pike
Original Assignee
Revera Inc
Alger C Pike
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Revera Inc, Alger C Pike filed Critical Revera Inc
Priority to EP05847786A priority Critical patent/EP1844489A2/en
Priority to JP2007552120A priority patent/JP2008530772A/en
Publication of WO2006088527A2 publication Critical patent/WO2006088527A2/en
Publication of WO2006088527A3 publication Critical patent/WO2006088527A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

According to one aspect of the invention, a semiconductor substrate processing apparatus and a method for processing semiconductor substrates are provided. The method may include providing a semiconductor substrate having a surface and a plurality of features on the surface, each feature being positioned on the surface at a first respective point in a first coordinate system, plotting the position of each feature at a second respective point in a second coordinate system; and generating a translation between the first and the second coordinate systems. The generating of the translation may include calculating an offset between the first and the second coordinate systems. The calculating of the offset may include calculating an offset distance between a reference point of the first coordinate system and a reference point of the second coordinate system and calculating an offset angle between an axis of the first coordinate system and an axis of the second coordinate system.
PCT/US2005/042863 2005-01-20 2005-11-28 A semiconductor substrate processing method WO2006088527A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05847786A EP1844489A2 (en) 2005-01-20 2005-11-28 A semiconductor substrate processing method
JP2007552120A JP2008530772A (en) 2005-01-20 2005-11-28 Semiconductor substrate processing method and apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/040,329 2005-01-20
US11/040,329 US7720631B2 (en) 2005-01-20 2005-01-20 Semiconductor substrate processing method and apparatus

Publications (2)

Publication Number Publication Date
WO2006088527A2 WO2006088527A2 (en) 2006-08-24
WO2006088527A3 true WO2006088527A3 (en) 2006-12-21

Family

ID=36914344

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/042863 WO2006088527A2 (en) 2005-01-20 2005-11-28 A semiconductor substrate processing method

Country Status (5)

Country Link
US (2) US7720631B2 (en)
EP (2) EP1844489A2 (en)
JP (1) JP2008530772A (en)
KR (1) KR20070115894A (en)
WO (1) WO2006088527A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7720631B2 (en) 2005-01-20 2010-05-18 Revera, Incorporated Semiconductor substrate processing method and apparatus
US7399963B2 (en) * 2005-09-27 2008-07-15 Revera Incorporated Photoelectron spectroscopy apparatus and method of use
US7539552B2 (en) * 2006-10-09 2009-05-26 Advanced Micro Devices, Inc. Method and apparatus for implementing a universal coordinate system for metrology data
US8185242B2 (en) * 2008-05-07 2012-05-22 Lam Research Corporation Dynamic alignment of wafers using compensation values obtained through a series of wafer movements
US9080948B2 (en) * 2013-03-14 2015-07-14 International Business Machines Corporation Dynamic peak tracking in X-ray photoelectron spectroscopy measurement tool
US9513119B2 (en) * 2013-03-15 2016-12-06 The United States Of America, As Represented By The Secretary Of The Navy Device and method for multifunction relative alignment and sensing
US10522380B2 (en) * 2014-06-20 2019-12-31 Applied Materials, Inc. Method and apparatus for determining substrate placement in a process chamber
KR101740480B1 (en) * 2015-05-29 2017-06-08 세메스 주식회사 Teaching method and substrate treating apparatus using the same
US10984524B2 (en) * 2017-12-21 2021-04-20 Advanced Ion Beam Technology, Inc. Calibration system with at least one camera and method thereof
US10796940B2 (en) 2018-11-05 2020-10-06 Lam Research Corporation Enhanced automatic wafer centering system and techniques for same
CN114466728A (en) * 2019-07-26 2022-05-10 朗姆研究公司 Integrated adaptive positioning system and routines for automated wafer handling robot teaching and health check
CN112530823B (en) * 2020-10-30 2024-02-06 普冉半导体(上海)股份有限公司 Method for detecting coordinate deviation in electronic bitmap in wafer test process

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088175A (en) * 1994-06-17 1996-01-12 Nikon Corp Aligner and align method
US5805866A (en) * 1994-02-10 1998-09-08 Nikon Corporation Alignment method
US5808910A (en) * 1993-04-06 1998-09-15 Nikon Corporation Alignment method
US20040258514A1 (en) * 2002-06-12 2004-12-23 Ivo Raaijmakers Semiconductor wafer position shift measurement and correction

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088175B2 (en) 1989-03-07 1996-01-29 富士電機株式会社 Resin mold type induction
US20010049589A1 (en) * 1993-01-21 2001-12-06 Nikon Corporation Alignment method and apparatus therefor
US5806866A (en) * 1996-07-11 1998-09-15 Fleischer; Jeff Cargo enhancing method and apparatus
EP1016126B1 (en) * 1997-03-31 2018-12-26 Nanometrics Incorporated Optical inspection module and method for detecting particles and defects on substrates in integrated process tools
JP3867402B2 (en) * 1998-05-29 2007-01-10 株式会社日立製作所 Semiconductor device inspection analysis method
EP1125113A1 (en) * 1998-10-29 2001-08-22 Applied Materials, Inc. Method and apparatus for improved defect detection
WO2002088683A1 (en) * 2001-04-30 2002-11-07 The Board Of Trustees Of The University Of Illinois Method and apparatus for characterization of ultrathin silicon oxide films using mirror-enhanced polarized reflectance fourier transform infrared spectroscopy
US20030045098A1 (en) * 2001-08-31 2003-03-06 Applied Materials, Inc. Method and apparatus for processing a wafer
TWI229243B (en) * 2002-09-20 2005-03-11 Asml Netherlands Bv Lithographic marker structure, lithographic projection apparatus comprising such a lithographic marker structure and method for substrate alignment using such a lithographic marker structure
US7720631B2 (en) 2005-01-20 2010-05-18 Revera, Incorporated Semiconductor substrate processing method and apparatus
US7388213B2 (en) * 2005-09-23 2008-06-17 Applied Materials, Inc. Method of registering a blank substrate to a pattern generating particle beam apparatus and of correcting alignment during pattern generation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808910A (en) * 1993-04-06 1998-09-15 Nikon Corporation Alignment method
US5805866A (en) * 1994-02-10 1998-09-08 Nikon Corporation Alignment method
JPH088175A (en) * 1994-06-17 1996-01-12 Nikon Corp Aligner and align method
US20040258514A1 (en) * 2002-06-12 2004-12-23 Ivo Raaijmakers Semiconductor wafer position shift measurement and correction

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 05 31 May 1996 (1996-05-31) *

Also Published As

Publication number Publication date
EP1844489A2 (en) 2007-10-17
US7720631B2 (en) 2010-05-18
WO2006088527A2 (en) 2006-08-24
EP1876634A2 (en) 2008-01-09
US20060190916A1 (en) 2006-08-24
US20100228374A1 (en) 2010-09-09
JP2008530772A (en) 2008-08-07
EP1876634A3 (en) 2009-12-09
US7996178B2 (en) 2011-08-09
KR20070115894A (en) 2007-12-06

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