WO2006090126A3 - Aligned logic cell grid and interconnect routing architecture - Google Patents

Aligned logic cell grid and interconnect routing architecture Download PDF

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Publication number
WO2006090126A3
WO2006090126A3 PCT/GB2006/000573 GB2006000573W WO2006090126A3 WO 2006090126 A3 WO2006090126 A3 WO 2006090126A3 GB 2006000573 W GB2006000573 W GB 2006000573W WO 2006090126 A3 WO2006090126 A3 WO 2006090126A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic cell
aligned
cell grid
routing
pitch
Prior art date
Application number
PCT/GB2006/000573
Other languages
French (fr)
Other versions
WO2006090126A2 (en
Inventor
Shannon Vance Morton
Original Assignee
Icera Inc
Shannon Vance Morton
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icera Inc, Shannon Vance Morton filed Critical Icera Inc
Priority to JP2007556650A priority Critical patent/JP4773466B2/en
Priority to EP06709809A priority patent/EP1861801A2/en
Publication of WO2006090126A2 publication Critical patent/WO2006090126A2/en
Publication of WO2006090126A3 publication Critical patent/WO2006090126A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Abstract

A method (150) for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell (12) is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch (24) of the interconnect layout and a transistor pitch (14) of the logic cell. The cell grid is aligned with the resized routing pitch (124) which provides efficient routing density and transistor performance, minimises excess transistor area and wire routing waste while maximising cell packing density.
PCT/GB2006/000573 2005-02-24 2006-02-17 Aligned logic cell grid and interconnect routing architecture WO2006090126A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007556650A JP4773466B2 (en) 2005-02-24 2006-02-17 Arranged logic cell grid and interconnect routing structure
EP06709809A EP1861801A2 (en) 2005-02-24 2006-02-17 Aligned logic cell grid and interconnect routing architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/066,041 2005-02-24
US11/066,041 US7287237B2 (en) 2005-02-24 2005-02-24 Aligned logic cell grid and interconnect routing architecture

Publications (2)

Publication Number Publication Date
WO2006090126A2 WO2006090126A2 (en) 2006-08-31
WO2006090126A3 true WO2006090126A3 (en) 2006-12-07

Family

ID=36927791

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2006/000573 WO2006090126A2 (en) 2005-02-24 2006-02-17 Aligned logic cell grid and interconnect routing architecture

Country Status (5)

Country Link
US (1) US7287237B2 (en)
EP (1) EP1861801A2 (en)
JP (1) JP4773466B2 (en)
TW (1) TWI413213B (en)
WO (1) WO2006090126A2 (en)

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US20060281221A1 (en) * 2005-06-09 2006-12-14 Sharad Mehrotra Enhanced routing grid system and method
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8448102B2 (en) * 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8214778B2 (en) 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7401310B1 (en) * 2006-04-04 2008-07-15 Advanced Micro Devices, Inc. Integrated circuit design with cell-based macros
US7735041B2 (en) * 2006-08-03 2010-06-08 Chipx, Inc. Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8607180B2 (en) * 2012-05-09 2013-12-10 Lsi Corporation Multi-pass routing to reduce crosstalk
US10541243B2 (en) 2015-11-19 2020-01-21 Samsung Electronics Co., Ltd. Semiconductor device including a gate electrode and a conductive structure
KR20180070322A (en) 2016-12-16 2018-06-26 삼성전자주식회사 Integrated circuit for multiple patterning lithography, computing system and computer-implemented method for designing integrated circuit
US10916498B2 (en) 2018-03-28 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for logic circuit
KR102373540B1 (en) 2018-04-19 2022-03-11 삼성전자주식회사 Integrated circuit including standard cell and method and system for fabricating the same
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
US11755808B2 (en) * 2020-07-10 2023-09-12 Taiwan Semiconductor Manufacturing Company Limited Mixed poly pitch design solution for power trim

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Publication number Priority date Publication date Assignee Title
US5754826A (en) * 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
US20020007478A1 (en) * 2000-07-17 2002-01-17 Li-Chun Tien Routing definition to optimize layout design of standard cells

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Also Published As

Publication number Publication date
US7287237B2 (en) 2007-10-23
JP4773466B2 (en) 2011-09-14
US20060195810A1 (en) 2006-08-31
TWI413213B (en) 2013-10-21
JP2008532132A (en) 2008-08-14
EP1861801A2 (en) 2007-12-05
TW200636915A (en) 2006-10-16
WO2006090126A2 (en) 2006-08-31

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