WO2006090650A1

WO2006090650A1 - Method for processing wafer

Info

Publication number: WO2006090650A1
Application number: PCT/JP2006/302868
Authority: WO
Inventors: Kyouyuu Yasuda
Original assignee: Jsr Corporation
Priority date: 2005-02-23
Filing date: 2006-02-17
Publication date: 2006-08-31
Also published as: TW200723382A; JPWO2006090650A1

Abstract

A method for processing a wafer adaptable to a variety of wafers having complex structure by solving problems of conventional processes that the wafer strength lowers and the wafer support thermally deteriorates after wet polishing, a polished wafer is liable to crack when it is separated from the support, and testing at wafer level is difficult after thinning. The method for processing a wafer is characterized in that an adhesive composition principally comprising a compound having a molecular weight of 5,000 or less is interposed, as a fixing agent, between the wafer surface on which a semiconductor element is formed and the support, the wafer and the support are brought into close contact by thermally fusing the composition and then bonded fixedly by cooling, the back of the wafer is polished to thin the wafer to a thickness of 20-100 μm, and then the wafer and the support are separated by thermally fusing the composition.

Description

Specification

Wafer processing method

Technical field

[0001] The present invention relates to a series of wafer processing methods in which the back surface of a wafer having a semiconductor element formed on the front surface is polished to reduce the thickness of the wafer, and the wafer is divided into semiconductor chips. More specifically, by adopting an adhesion method that can firmly fix the wafer to the support even under high temperature conditions in the heat treatment during or after polishing, and can easily peel off the wafer after processing, The present invention also relates to a wafer processing method capable of reducing the thickness of a wafer having a complicated internal structure to a thickness of 100 μm or less even for a large-area wafer.

Background art

[0002] Technology for stacking and mounting a plurality of semiconductor chips that meet demands for higher functionality and larger capacity of semiconductor chips has been developed and put into practical use. As such a technique, for example, a technique of stacking a plurality of memory chips can be cited, and as a result, the storage capacity can be increased as a whole.

As a technique for stacking a plurality of semiconductor chips in this way, for example, as described in JP-A-2001-0153218 (Patent Document 1), a through via structure is formed inside a wafer to form a gap between chips. There have been proposed a method of performing this wiring and a method of taking out the wiring with a gold wire and laminating the electrode pad force at the periphery of the wafer.

[0003] Recently, the increase in memory capacity, miniaturization, and integration of functions has progressed rapidly, the number of wafers has increased, and 10 layers have been approaching. In response to this trend, thinning of wafers has progressed accordingly, and a thickness of less than 100 m has been required for 300 mmφ wafers.

Thinning a wafer is a series of processes in which the wafer surface is first protected and supported with back grind tape 1) · Polishing, then pasted with dicing tape, and the wafer is cut into semiconductor chips. It has been implemented.

[0004] In a series of processes for making such a wafer into semiconductor chips, the focus is now placed on the process after wet grinding using gunshot particles. The process of removing is mainly studied. For example, a wet etching method in which the ground back surface is chemically etched using an etchant containing nitric acid and hydrofluoric acid, a dry etching method using an etching gas, and a back surface of the ground semiconductor wafer is freed from a barrel. Various attempts have been made, such as polishing using a polishing method and dry polishing with a felt grindstone.

[0005] Further, when the stacking of semiconductor chips progresses in this way, whether the stacked semiconductor chips are non-defective products or defective products affects the yield of the stacked body. Since the yield increases with the number of stacked layers, the testing process that determines whether a semiconductor chip is good or defective before stacking is regarded as important.

In the conventional testing process, the method of testing each semiconductor chip individually has been the mainstream, but in recent years, a method of batch testing on a wafer basis has been proposed and put into practical use. However, in order to improve the yield of the laminated body, it is most effective to test immediately before stacking, that is, after thinning and dicing, so it is difficult to handle thinned wafers. It is a difficult situation to do.

Patent Document 1: JP 2001-53218 A

Disclosure of the invention

Problems to be solved by the invention

[0006] The following points have been pointed out as problems in the conventional process for further thinning of semiconductor wafers! Speak.

(1) Only wet grinding that uses an abrasive can leave fine scratches on the wafer, resulting in insufficient wafer strength after processing, cracking during handling, and chipping during dicing.

(2) Attempts have been made to remove the scratches (grind strain layer) generated by wet grinding by dry polishing! / Wearing force The heat generated by dry polishing can cause thermal degradation of the wafer support. This is especially true for area wafers.

(3) Support strength of the wafer after thinning, the thinner the wafer, the worse the balance between the strength of the wafer itself and the adhesive strength with the support, and the easier it is to crack. This is especially true for large-area wafers because the area to be peeled off is large. (4) Since testing at the wafer level cannot be performed after thinning, defects in thin-wall processing and dicing cage greatly affect the yield of the chip stack.

[0007] Therefore, an object of the present invention is to provide a wafer thinning process that can solve the above-mentioned problems in the conventional processes and can cope with wafers having various and complicated structures. is there.

Means for solving the problem

[0008] The inventors of the present invention have conducted intensive studies to solve the above problems. As a result, when the back surface of the roughly ground semiconductor wafer is polished and thinned to 20-: LOO m, a composition containing as a main component a compound having a molecular weight of 1000 or less is used as a fixing agent. By fixing the (element forming surface) and the support and selecting the materials and processes according to the temperature environment of the wafer, the dicing method, the wafer surface structure, the required adhesion strength, etc. I found it to be solved.

[0009] For example, in a conventional method of thinning a wafer using a dicing tape after thinning the wafer, a low melting point fixing agent that can be easily attached to the dicing tape is selected and used. As the grinding strain layer removal method, it is preferable to use the CMP method wet polishing and chemical etching method, which do not easily raise the wafer temperature, and the reactive ion etching (RIE) method, which can control the wafer temperature! /.

[0010] On the other hand, in the "tip dicing" method in which a cutting groove having a predetermined thickness is formed in advance before grinding, the fixing agent is thoroughly impregnated into the cutting groove, so that the permeability is good. Select and use a fixative with a low melt viscosity. In this case, because of the ability to remove this fixing agent in the polishing process, CMP type wet polishing and physical polishing with a felt grindstone are preferred! Similarly, when processing a wafer having a complicated wafer structure with unevenness, specifically, a wafer having a via structure penetrating in the film thickness direction, a wafer having a bump structure for wiring connection, and the like. Penetration, low melt viscosity, and fixatives are preferred.

[0011] The present invention is based on the above findings, and is specifically as follows.

The wafer processing method according to the present invention uses as a main component a compound having a molecular weight of 1000 or less as a fixing agent for fixing the wafer and the support between the wafer surface on which the semiconductor element is formed and the support. The adhesive composition contained is interposed, and the composition is heated and melted. After the substrate and the support are brought into close contact with each other, the wafer and the support are bonded and fixed by cooling, and the wafer is thinned by polishing the rear surface of the wafer, and the composition is heated and melted to heat the wafer and the support. It is characterized by peeling.

[0012] The compound having a molecular weight of 1000 or less preferably has crystallinity. The compound having a molecular weight of 1000 or less is preferably a compound having a steroid skeleton and Z or a hydroxyl group in the molecule or a derivative thereof. Furthermore, the compound having a molecular weight of 1000 or less preferably has a melting temperature of 50 to 300 ° C. and a melting temperature width of the composition of 30 ° C. or less.

In the wafer processing method according to the present invention, in the step of polishing the back surface of the wafer, the thickness of the wafer can be reduced to 20 to: LOO μm.

Further, when the adhesive strength at 25 ± 2 ° C of the above composition is A (MPa) and the adhesive strength at a temperature 20 ° C lower than the melting temperature of the composition is B (MPa), the adhesive strength A And B preferably satisfies the following formula (1).

0 <A-B <0.5 (MPa) (1)

The composition is preferably in the form of a tablet.

[0014] The wafer may have a semiconductor element formed in a region partitioned by a plurality of die cinder streets on the surface, or a cutting groove may be formed in the dicing street. In this case, it is possible to reduce the thickness to a semiconductor chip until the above-mentioned cutting groove is exposed, and to separate the support body force in units of the semiconductor chip.

The wafer is a wafer in which a hole having a predetermined depth is formed on the surface, the inner wall of the hole is covered with an insulating film, and the conductive electrode material is embedded in the hole covered with the insulating film. It may also have a protruding electrode for conduction.

[0015] The wafer may be a wafer on which at least one selected from a structure, a wiring, and an element force is formed on the back surface.

In the wafer processing method of the present invention, after the wafer is thinned, the polished surface may be further processed to form at least one selected from the structure, wiring, and element force. The invention's effect

[0016] According to the present invention, the back surface of the roughly ground wafer is polished to reduce the thickness to 20 to: LOO / zm. For example, the following effects can be obtained.

(1) Because the heat resistance of the fixing agent is better than when using a conventional tape support

The burden imposed on the cooling mechanism during polishing is reduced.

(2) Because of the high hardness of the adhesive layer, there is less chipping when dicing after wafer thinning.

(3) Since a hard support can be used, even a large area wafer does not warp, and the thinned wafer can be easily peeled off.

(4) Since the crystalline composition used in the present invention has a very low melt viscosity, it can follow the shape of a wafer having a complicated shape, and the thin wall of the wafer having a complicated shape, which has been difficult with a conventional tape support. Can be realized.

Brief Description of Drawings

FIG. 1 is a model diagram of the Ueno / Cake method performed in Example 1 of the present invention.

FIG. 2 is an SEM image of a nodal bump formed in Example 2 of the present invention.

FIG. 3 is a model diagram of the Ueno / Cake method performed in Example 2 of the present invention.

FIG. 4 is a model diagram of a wafer used in Example 4 of the present invention.

FIG. 5 is a schematic view showing a method for measuring adhesive strength in Examples.

Explanation of symbols

1'Wafer

2. • Semiconductor elements

3 · SUS substrate

4 · 'Fixing agent

5 'Dry film resist

6

7 • Nonda Knoop

8 • Cutting groove (80 m)

9 'glass substrate

10 '' 'Immobilizing agent

11 '''Insulating resin film 12 · · · Wafer piece (3mm mouth, 70 μmj?)

13 · · · Wafer piece (5mm mouth, 70 μmj?)

14 · · · Cutting grooves

15 ··· Via (50 m mouth, depth 80 μm)

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the wafer processing method according to the present invention will be described in detail.

In the wafer processing method of the present invention, the wafer surface on which the semiconductor element is formed and the support are bonded and fixed using a specific fixing agent, and the wafer back surface is ground and polished to reduce the thickness.

The fixing agent used in the present invention is an adhesive composition containing, as a main component, a compound having crystallinity in order to impart cohesive force to the composition, preferably a tablet-like adhesive composition, The compound should have a molecular weight of 1000 or less, preferably 150 to 800, more preferably 200 to 600. When the molecular weight of the compound exceeds the above range, the solubility of the compound in the solvent becomes low, and peeling and washing with the solvent may be insufficient.

[0020] The melting temperature of the above compound is 50 to 300 ° C, preferably 55 to 250 ° C, more preferably 100 to 200 ° C. Here, the melting temperature refers to the peak temperature in the main melting peak curve measured with a differential scanning calorimeter (DSC). When the melting temperature of the compound is in the above range, the heat-resistant temperature at the time of adhesion can be improved.

Further, the above compound does not damage the wiring and insulating film formed on the semiconductor wafer, does not become a contamination source, and does not denature the adhesive when melted. A neutral compound that does not have an active functional group such as a group, and an alkali metal or the like that diffuses into the medium and adversely affects insulation (for example, Na, K, Ca, (Fe, Cu, Ni, Cr, Al, etc.) is desirably subjected to a metal-free treatment until the total metal content becomes lOOppm or less, preferably ΙΟρρm or less. However, this does not apply to those containing metal oxides in a stable form.

[0021] Examples of such compounds include 1, 3, 5-tri-trobenzene and 2, 3, 6-tri-trophenol. The ability to mention -tro compounds such as 2, 4, 5-tri-tolutoluene, etc. N element from the viewpoint of high handling safety, excellent heat resistance during melting, and low coloring Organic compounds that only contain H and O elements are preferred. Specific examples include aromatic compounds, aliphatic compounds, and alicyclic compounds as exemplified below. Examples of the aromatic compounds include 9H-xanthene, benzofuran-3 (2H) -one, 1,5-diphenyl-2,4-pentagen-1-one, di-2-naphthyl ether, cis-1,8 -Terpine, 2,3-dimethylnaphthalene, 1,2-naphthalenediol, di-1-naphthylmethane, biphenyl-2,2'-diol, di-1-naphthyl ether, bis (diphenylmethyl) ether, 9, 10-dihydroanthracene, 2, 3, 5, 6-tetramethyl-p-benzoquinone, 2, 6-dimethylnaphthalene, syringaldehyde, vanillyl alcohol, 1,3-diphenylisobenzofuran, 2, 3'- Dihydroxybenzophenone, isohydrobenzoin, 4,4'-dimethylbiphenyl, 1,3-naphthalenediol, 4-phenanthrol, 3,3-diphenylphthalide, pentamethylphenol, hexenylbenzene, 3, 4-dihydro Cibenzophenone, 2, 4-dihydroxybenzaldehyde, p-hydroxybenzophenone, 4, 5, 9, 10-tetrahydropyrene, 2, 3, 4-trihydroxybenzophenone, hematoxylin, 2-isopropyl-5-methylhydroquinone 1,9-diphenyl-1,3,4,8-nonatetraen-5-one, 9-phenylfluorene, 1,4,5-naphthalenetriol, 1-anthrol, 1,4-diphenyl-1 , 3-butadiene, galvinoxyl, pyrene, 9-phenylanthracene, triphenylmethanol, 1,1'-binaphthyl, m-xylene-2,4,6-triol, 4,4'-methylenediphenol, Hexamethylbenzene, dibenzo-18-crown-6, diphenoquinone, biphenol-4-ol, 1H-phenalene, 10-hydroxycyantron, flavonol, benzoanthrone, 9H-xanthen-9-one, te Raphenylfuran, 2-methylanthraquinone, 4-hydroxy-1-naphthaldehyde, 1,7-naphthalenediol, 2,5-diethoxy-p-benzoquinone, curcumin, 2,2'-binaphthyl, 1,8-dihydroxy Anthraquinone, 1,4-naphthalenediol, 1-hydroxyanthraquinone, 3,4-dihydroxyanthrone, 0-terfel, m-terfel, p-terfel, 4,4'-dihydroxybenzophenone , Anthracene, 2,4,6-trihydroxyacetophenone, 1,8-anthracenediol, tetraphenylethylene, 1,7-dihydroxy-9-xanthenone, 2,7-dimethylanthracene, epicatechin, naringen, 2-antolol, 1,5-naphthalenedio , Benzylidenephthalide, 2-phenylnaphthalene, cis-decahydro-2-naphthol (cisoid), (2R, 3R) -2, 3-bis (diphenylphosphino) butane, trans-1, 2-dibenzoy Ruethylene, trans-1, 4-diphenyl-2-butene-1, 4-dione, bis (2-hydroxyethyl) terephthalate, fluoranthene, biphenylene, isovanillin, fluorene, 9-anthrol, p- Hue-rangeacetate, trans-stilbene, biphenyl-3,3 diol, 2,5-dihydroxybenzophenone, pinol hydrate, benzoin, hydrobenzoin, 1,2-bis (diphenylphosphino) ethane, 2, 4- Dihydroxybenzophenone, 1,8-naphthalenediol, 1,2-naphthoquinone, 2,4'-dihydroxybenzophenone, 5-hydroxy-1,4-naphthoquinone, 1-phenanthrol, anthrone, 9- Luolenol, triphenylphosphine oxide, benzo [a] anthracene, 1,2-anthracenediol, 2,3-naphthalenediol, 2,4,6-trihydroxybenzophenone, di-2-naphthyl ketone 3,3'-dihydroxybenzophenone, arbutin, 1, 2, 3, 5-benzenetetraol, diphenylquinomethane, 2-phenanthol, 2, 3, 4-trihydroxyacetophenone, capsanthin, 1,3,5-triphenylbenzen, 3,4,5-trihydroxybenzophenone, benzo [a] pyrene, triphenylmethylperoxide, hexestrol, 1,1,2,2-tetraphenyl -Lu-1,2-ethanediol, 1,8-dihydroxy-3-methylanthraquinone, camphorquinone, 2, 2 ', 5, 6 and tetrahydroxybenzophenone, esculin, 3,4'-dihydroxybenzophe Non, 2, 4, 5-trihydroxyacetophenone, 9, 10-phenanthrenequinone, 1, 1, 2, 2-tetraphenylethane, rutin, (-)-hesberetine, 2, 3 ', 4 , 4 ', 6-Pentahydroxybenzophenone, 7-Hydroxycoumarin, cQ-Hesperetin, Ninhydrin, Triptycene, Fluorescine, Talycene, Jetylstilbestol, Dibenzo [a, h] anthracene, Pentacene, 1, Examples include 6-dihydroxyanthraquinone, 3,4 ′, 5,7-tetrahydroxyflavone, 2,6-anthracenediol, and genistein.

Examples of the aliphatic compounds include ribitol, D-arabitol, furyl, γ-carotene, j8-carotene, cantharidin, pentaerythritol, trans, trans-1, 4-diacetoxybutadiene, D-glucitol, D -Mannitol, idose, decanal, α-carotene, 2,4,6-trimethylphloroglucinol, galactitol, echirin, echlenine, trans-1, 2-cyclobentanediol, manol, 1-heptadecanol, 1-octadecanol , Examples include 1-icosanol, dihydroxyacetone, _{テル} -terbineol, 1-hexacosanol, 1-hentriacontanol, and stearone.

Examples of the alicyclic compounds include coprostanol, timosterol, ergocalciferol, j8-sitosterol, lanosterol, 11-deoxycorticosterone, cholestanonore, cholesterol, and testosterone, enolegostero-nore, Stigmasterol, estradiol, conoleticosterone, epicholestanol, androsterone, 17α-hydroxy-11-deoxycorticosterone, gitoxigenin, epicoprostanol, calcipherol, progesterone, dehydroepiandrosterone , 7-dehydrocholesterol, agnosterol, 11-dehydrocorticosterone, prednisolone, digitoxigenin, estrone, / 3-estradiol, cortisone, D-fructose (α-open, D-lyxose a form), D-lyxose (13 form), isomaltose, D-talose (13 form), D-talose (a form), D-allose (beta form), D-mannose (beta form), D-mannose ((X form), D-xylose ((X form) D-galactose (13 form), L-fucose (a form), D-glucose (a form), 2-deoxy-D-glucose, manoletotri Aose, D-altro-heptulose, L-arabinose (pyranose α-opened, D-arabinose, caffe stall, L-arabinose (viranose 13 form), D-galactose (a form), lycopene, alkvin, sucrose, freedelin, cis- 1,3,5-cyclohexanetriol, D-inositol, rutin, diosgenin, tigogenin, zeaxanthin, myo-inositol, cellobiose, gibberellin A3, hematein, bellin, D-fructose (j8 open, D-altrose (Form 13), dibenzo-24-crown-8, methyl-D-darcoviranoside (beta form), D-digitalose, salinomycin, methyl-D-galactopyranoside (form a), a, a-trehalose, Bixin (all trans form), palatinose, trans-1, 4-terpine, D-quinobose (alpha form), D—glycero— D—galacto—heptose, D—fucose (open, D—glucose (j8 open, D) — Manno— heprose, D-glycero- D-gluco-heptose, sophorose, sanoresasapogenin, L-sorbose, D-altro-3-heptulose, twistin, (+)-borneol, inositol, (-)-iso Borneol, L-arabinose (furanose form), L-galactose (alpha form), alpha-santonin, methyl-D-galactopyranoside (j8 form), cyclopentadecanone, δ-valerolataton, ci s-2- Methylcyclohexanol Following chemical formula (1) to the compound represented by (8), and the like.

Among the above compounds, from the viewpoint of tablet processability, cholesterol, coprostano monole, timostero monore, enorego cano referonore, β-sitostero monore, lanostero monore 11-deoxycorticosterone, cholestanol, testosterone, ergosterol, stigmasterol, estradiol, conoleticosterone, epicolestanol, androsterone, 17-hydroxy-11-deoxycorticosterone, Gitoxigenin, epicoprostanol, calcipherol, progesterone, dehydroepiandrosterone, 7-dehydrocholesterol, agnostellonore, 11-dehydroconorticosterone, prednisolone, digitoxigenin, estrone, j8-estradiol, cortisone and above Compounds having a steroid skeleton such as compounds represented by chemical formulas (1) to (8); trans-1, 2_cyclobentandiol, manol, 1-heptadecanol, 1-octadecanol, 1-icosanol, γ- Te Pineoru, Kisakosanoru to 1, the water acid group-containing compounds such as 1-hen triacontanol; and derivatives thereof, 0 Terufueniru, m- Terufuwe - le, P- Tel phenyl, Bifue two Le is particularly preferred. The ester derivative is not preferable because it may become acidic when thermally decomposed with a low melting point and may erode the adhesive surface.

[0027] The above compound may be used alone or in combination of two or more. The content in the adhesive composition is 70% by weight or more, preferably 80% by weight or more, particularly preferably. Is used so that it becomes 90% by weight or more. If the content is lower than the above range, the melting temperature may not be sharp, and the melt viscosity may increase.

The adhesive composition containing the above compound as a main component has a melting temperature range of 1 to 30 ° C, preferably 1 to 20 ° C, particularly preferably 1 to 10 ° C. It is characterized by melt viscosity at the melting temperature of ^ 0.001-0. lPa's, preferably 0.001-0.05 Pa's, particularly preferably 0.001-0. OlPa's. To do. Here, the melting temperature range refers to the difference between the starting point temperature and the ending point temperature in the main melting peak curve measured by a differential scanning calorimeter (DSC). When the melting temperature range and the melt viscosity are in the above ranges, the external force applied when the wafer is also peeled off can be reduced, and the ease of peeling is improved.

[0028] Since the melting temperature range and melt viscosity of the composition strongly depend on the melting temperature range and melt viscosity of the compound, it is desirable to use a compound having a narrow melting temperature range and a low melt viscosity. That is, the main component compound has a melting temperature of 50 to 300 ° C, a melting temperature range of 1 to 30 ° C, and a melt viscosity at the melting temperature of 0.0001-0.lPa's. Is preferred.

[0029] In addition, it is preferable to purify the compound in order to narrow the melting temperature range of the compound, reduce the melt viscosity, and further reduce the amount of free metal ions. As a method for purifying a compound, for example,

(a) a method of increasing the purity by dissolving the compound in a solvent, gradually distilling off the solvent and recrystallization, and

(b) A method in which the metal content is reduced by dissolving the compound in a solvent and bringing the solution into contact with an ion exchange resin to remove free metal.

[0030] The immobilizing agent used in the present invention is used to adjust the wettability and adhesion to the substrate, or to adjust the melt viscosity of the adhesive composition and to improve the tableting processability of the composition. Therefore, a surface tension adjusting agent such as a nonionic surfactant or a release agent can be added within a range without impairing the intended function, if necessary.

Examples of nonionic surfactants that can be added include fluorine surfactants having a fluorinated alkyl group such as a perfluoroalkyl group, and polyether alkyl surfactants having an oxyalkyl group. Silicone mold release agent can be used as the mold release agent.

[0031] Examples of the fluorosurfactant include C F CONHC H.

9 19 12 25, C F SO NH

8 17 2 I (C H O) H, “F-top EF301, EF303, EF352” (manufactured by Shin-Akita Kasei Co., Ltd.),

2 4 6

“Megafuck F171, F173” (Dainippon Ink Co., Ltd.), “Asahi Guard AG710” (Asahi Glass Co., Ltd.), “Florard FC—170C, FC430, FC431” (Sumitomo 3EM) )), "Surflon S-382, SC101, SC102, SC103, SC104, SC105, SC106" (Asahi Glass Co., Ltd.), ": BM-1000, 1100" (B. M — Chemie), “Schsego-Fluor” (Schwegmann), “FS1265” (manufactured by Toray Dowco-Nungsircon Co., Ltd.), and the like.

[0032] Examples of the polyether alkyl surfactants include polyoxyethylene alkyl ether, polyoxyethylene alkyl ether, polyoxyethylene alkyl ether, polyoxyethylene fatty acid ester, sorbitan fatty acid ester, and polyoxyethylene alkyl ether. Lioxyethylene sorbitan fatty acid ester, oxyethyleneoxypropylene block Examples include a copolymer. Specifically, “Emargen 105, 430, 810, 920”, “Leodol SP-40S, TW—ΙΛ20, Emanol 3199, 4110”, “Exel P-40S, Bridge 30, 52” 72, 92 ”,“ Alassell 20, Emazole 320, Queen 20, 60, Merge 45 ”(above, manufactured by Kao Corporation),“ No-Ball 55 ”(manufactured by Sanyo Chemical Co., Ltd.), Commercial products such as “SH-28PA, i-190, i-193, SZ-6032, SF-8428” (above, manufactured by Toray Industries Co., Ltd.) can be used.

[0033] Examples of nonionic surfactants other than the above include polyoxyethylene fatty acid esters, polyoxyethylene sorbitan fatty acid esters, polyalkylene oxide block copolymers, and the like. Specifically, “CHEMISTAT 2500 "Sanyo Kasei Kogyo Co., Ltd.", "SN-EX9228" (San Nopco Co., Ltd.), "Nonaru 530" (Toho Chemical Co., Ltd.), etc. can be used.

[0034] In addition, for compositions having a high melting temperature exceeding 150 ° C, dimethyl silicone oil KF 965 (manufactured by Shin-Etsu Chemical), SH200 (manufactured by Dow Silicone), methyl-fell silicone oil KF54, KF50 (Shin-Etsu) A low-volatility silicone oil with excellent heat resistance, such as chemicals, can also be used effectively and can be used.

The surface tension adjusting agent can be used in an amount of 0.1 to 50 parts by weight, preferably 1 to 30 parts by weight with respect to 100 parts by weight of the compound. If the amount used exceeds the above range, there is a problem that the hardness of the adhesive at room temperature is too low, or the tackiness is too high, making tableting difficult. On the other hand, if the amount is less than the above range, the effect of improving wettability and Z or adhesion may not be exhibited!

[0035] The immobilizing agent is a metal oxide such as aluminum oxide, zirconium oxide, titanium oxide, or silicon oxide, if necessary, in order to control the gap between the substrates to be bonded. Alternatively, fine particles having a narrow particle size distribution such as polystyrene cross-linked particles (for example, “Micropearl SPN, SPS series” manufactured by Sekisui Chemical Co., Ltd.), etc., are 0.01 to: L0 wt%, preferably 0 It may be contained in the range of 01 to 5% by weight. When the content exceeds the above range, there may be a problem that when the particles are melted, the fine particles that are difficult to spread in the surface of the adherend aggregate to cause a problem that the gap between the substrates cannot be controlled. If it is low, the effect of controlling the gap may not appear. [0036] The adhesive strength of the adhesive composition is 0.5 MPa or more, preferably 1 MPa or more, particularly preferably 5 MPa or more at 25 ± 2 ° C. If the adhesive strength is lower than the above range, the bonded surface may be partially peeled depending on the processing conditions after bonding, and the in-plane uniformity of processing may be impaired.

Further, when the adhesive strength at 25 ± 2 ° C. of the adhesive composition is A (MPa) and the adhesive strength at a temperature 20 ° C. lower than the melting temperature of the composition is B (MPa), the adhesive strength is By satisfying the relational expression of degree A and B force 0 <AB <0.5 (MPa), it is possible to maintain a good adhesive state in a wide range below the melting temperature where the temperature dependence of the adhesive strength is small. The measurement method and conditions will be described later.

[0037] <Immobilization method>

In the wafer processing method of the present invention, the adhesive composition (fixing agent) is heated and melted and applied to a wafer or the like, the wafer and the support are bonded together, and then cooled, The wafer and the support are bonded and fixed.

In order to apply the adhesive composition to a wafer or the like, “melting temperature + 2 ° C.” to “melting temperature + 50 ° C.”, preferably “melting temperature + 2 ° C.” to “melting temperature” of the composition. It can be applied by heating to + 30 ° C, particularly preferably in the range of “melting temperature + 5 ° C” to “melting temperature + 20 ° C”. If the heating temperature is lower than the above range, the spread of the adhesive in the adherend surface may be insufficient and adhesion unevenness may occur. If the heating temperature exceeds the above range, volatilization or decomposition of the adhesive partially proceeds. In some cases, desired adhesive properties cannot be obtained.

[0038] The amount of the fixing agent applied can be arbitrarily selected according to the size of the adhesive surface of the wafer or the like to be used and the degree of adhesion required in the processing step. It is desirable to apply in an amount such that the thickness force is 0.01 μm to 2 mm, preferably 0.5 μm to 1 mm, more preferably 0.1 μm to 0.5 mm. If the thickness of the adhesive layer is less than the above range, it may not be sufficiently adhered, and if it exceeds the above range, the adhesive strength may be reduced, peeling off from the adhesive surface, and material failure of the adhesive may occur. The thickness of the adhesive layer can be adjusted by the amount of the adhesive and the pressure at the time of bonding.

[0039] As a method of bonding the wafer and the support,

(i) Applying an adhesive composition to one or both of the wafer and the support, To paste the person, and

(ii) A method of bonding the wafer and the support by interposing a tablet-like adhesive composition between the wafer and the support and then heating in that state to melt the adhesive composition Is mentioned. The method (ii) is preferably performed under a reduced pressure of 200 Torr or less in order to remove bubbles in the adhesive and make the thickness of the adhesive layer constant.

[0040] After bonding the wafer and the support as described above, the wafer is cooled to a melting temperature or lower, preferably "melting temperature 20 ° C" or lower, particularly preferably "melting temperature 40 ° C" or lower. As a result, the wafer and the support are firmly bonded.

The processing of the wafer fixed on the support as described above is lower than the melting temperature of the adhesive composition used!ことが It is preferable to carry out at temperature ヽ.

[0041] <Peeling method>

In the wafer processing method of the present invention, the wafer (including a semiconductor chip) is peeled from the support after the wafer processing described later. In this peeling step, at least one of the wafer and the support is heated to a temperature equal to or higher than the melting temperature of the used adhesive composition, so that the adhesive composition is melted and the wafer is peeled off from the support. be able to.

[0042] If the adhesive remains on the peeled surface, it can be removed by washing with a solvent capable of dissolving the adhesive composition. Such a solvent is not particularly limited as long as it can dissolve the adhesive composition. For example,

Alcohols such as isopropanol, butanol, hexanol, ethanol, methanol, ethylene glycol, diethylene glycol, propylene glycol, dipropylene glycol, phenol, t-amyl alcohol, cyclohexanol;

n-pentane, cyclopentane, n-xane, cyclohexane, n-heptane, cycloheptane, n-octane, cyclooctane, n-decane, cyclodecane, dicyclopentagen hydride, benzene, toluene, xylene, durene, indene Hydrocarbon solvents such as, decalin, tetralin, tetrahydronaphthalene, decahydronaphthalene, squalane, ethylbenzene, t-butylbenzene and trimethylbenzene;

Ketones such as acetone, methyl ethyl ketone, methyl isobutyl ketone, cyclopentanone, cyclohexanone; ethyl ether, ethylene glycol dimethyl ether, ethyl Ethers such as ethylene glycol dimethyl ether, diethylene glycol dimethyl ether, diethylene glycol dimethyl ether, tetrahydrofuran, dioxane, etc .; ethyl acetate, butyl acetate, butyl butyrate, ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ethinoate acetate , Ethylene glycol monoacetate, diethylene glycol monomethinoate etherate acetate, diethylene glycol monoethinoate etherate acetate, propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, dipropylene glycol monomethyl ether acetate Esters such as dipropylene glycol monoethyl ether acetate; Beauty,

Polar solvents such as dimethylformamide, dimethylacetamide, N-methylpyrrolidone, hexamethylphosphomide, dimethyl sulfoxide, γ-butyrolatatone, blackform, methylene chloride, and photoresist stripping solutions can be used.

Among these, isopropanol, ethanol, methanol, acetone, methyl ethyl ketone, and tetrahydrofuran are preferable. The above solvents may be used alone or in combination of two or more.

Examples of the cleaning method include a method of immersing a wafer in a cleaning solution and a method of spraying a cleaning solution on the wafer. The temperature of the cleaning liquid is not particularly limited, but is preferably 20 to 80. C, more preferably 30 to 50 ° C.

[0044] The material of the support used in the present invention is not particularly limited. However, when used in a semiconductor process, a material having no eluted metal is preferable. For example, a ceramic substrate such as silicon carbide or alumina, or a metal substrate such as silicon or stainless steel can be preferably used. In order to make the molten adhesive composition easily spread uniformly on the support, it is also preferable to apply the above-mentioned surfactant on the support surface or to form a fine groove pattern or the like in advance.

[0045] A fine groove pattern on the support can be formed using a photosensitive resin or by plating. From the viewpoint of resistance at high temperatures and repeated use, a pattern formed by a plating method is preferred. If the pattern shape is controlled to the pattern height according to the bonding film thickness, noturn can be used as a pillar for bonding gap control. The in-plane accuracy can be easily improved. Furthermore, by setting the in-plane pattern design according to the flow direction of the adhesive composition (the center force also flows toward the periphery, etc.), bubbles during bonding and wetting into the surface spread. Can also be controlled.

[0046] <Processing process>

The wafer bonded to the support is set on the back grinder together with the support, and is roughly ground until the wafer thickness reaches about 100 m. Thereafter, the grinding strain layer generated by grinding is removed, and the resulting layer is covered to a desired thickness of 20 to: L 00 / z m. The rough grinding method at this time can be a known method without any particular limitation. The grinding strain can be removed by selecting force such as felt grinding wheel method, plasma etching method, CMP method and chemical etching method.

[0047] The felt grindstone used in the felt grindstone method is produced, for example, by impregnating a felt material described in JP-A-2002-28311, JP-A-2002-283212, etc. with abrasive grains. A grindstone can be used suitably.

In the above plasma etching method, the apparatus shown in JP-A-6-338479, Table 98/016950, JP-A-2003-100718, JP-A-2003-229418, etc. is used, and CF, Ettin such as CF and CF (octafluorocyclopentene)

4 4 8 5 8

It can be performed using ggus. As a plasma etching method, the reactive ion etching (RIE) method capable of controlling the temperature of the wafer and anisotropic etching is preferred in terms of processing speed and less temperature applied to the wafer.

[0048] The CMP method is a method used for flatness even during element formation. When polishing the back surface, by switching to a simple slurry in which silicon fine particles are dispersed in water to eliminate contaminated ions as much as possible, Polishing can be performed.

The chemical etching method is performed using about 40-50% KOH solution, HFZ nitric acid mixed solution, etc. as the etching solution, and it is made into an apparatus like “GL-210S” manufactured by SEZ. I'll do it.

[0049] The processing until the wafer that has been polished to a desired thickness is mounted as a semiconductor chip varies depending on the application of the semiconductor chip. The present invention supports a process that could not be achieved in the past. It becomes possible to perform it in a state of being bonded to the body. One of such processes An example is shown below.

(1) A resist pattern is formed on the polished surface, and the wafer is etched using the resist pattern as a mask to form desired structures such as cavities, holes (including through holes), protrusions, grooves, etc. on the wafer and the back surface. .

[0050] (2) An organic film layer is applied to the polished surface and baked to form an ion-contamination preventing film on the polished surface.

(3) The wafer is diced without being attached to the dicing tape by selecting a fixing agent having a desired hardness and adhesive strength.

(4) A through-via is used as an inspection electrode, and a wafer level burn-in test is performed after thinning.

[0051] (5) When a wafer in which cutting grooves are formed in die cinder street by tip dicing is thinned until the cutting grooves are exposed in accordance with the above-described processing method, and the semiconductor chip that has been cut into pieces is melted with the fixing adhesive. At the same time, it is picked up and mounted on the package substrate using the fixing agent remaining on the chip as an underfill agent or a chip bonding agent.

<Wafer>

The semiconductor wafer used in the wafer etching method of the present invention is not particularly limited, and a semiconductor wafer suitable for the calorie method can be used for the application, and has a large area or various complicated structures on the surface. You may have.

[0052] For example, the process (5) includes a semiconductor element formed in a region partitioned by a plurality of die cinder streets, and the die cinder streets are cut corresponding to the thickness of the semiconductor chip. A semiconductor wafer having grooves formed by tip dicing can be used.

In the process (4), a hole having a predetermined depth is formed on the surface, the inner wall of the hole is covered with an insulating film, and a conductive electrode material is embedded in the hole covered with the insulating film. In addition, a semiconductor wafer can be used.

[0053] Further, the semiconductor wafer may have conductive bump electrodes, for example, nodal bumps, formed on the surface.

[Example]

Hereinafter, the present invention will be described in more detail based on examples in which several powers of the above-described examples are practiced. As will be apparent, the present invention is not limited to these examples.

[0054] The compounds used in the following examples are compounds that have been purified by deionization treatment by adding 20 parts by weight of ion-exchanged resin in advance and stirring and mixing for 10 hours. The metal contents of Na, K, Ca, Fe, Cu, Ni, Cr, and Al were confirmed to be less than lppm. The melting temperature, melting temperature range, melt viscosity, and adhesive strength were measured as follows.

[0055] <Melting temperature and melting temperature range>

Using a differential scanning calorimeter (“RDC220” manufactured by Seiko), the value in air at 2 ° C. Zmin was measured. The peak temperature of the main melting peak curve was defined as the melting temperature, and the temperature difference between the start point and end point of the melting peak curve was defined as the melting temperature width.

Using an E-type viscometer (manufactured by Toki Sangyo Co., Ltd.), the measurement was performed at the melting temperature.

[0056] <Adhesive strength>

The adhesive strength unique to each adhesive composition is: adhesive strength A (MPa) at 25 ° C at 2 ° C and adhesive strength B (MPa) at a temperature 20 ° C lower than the melting temperature of the adhesive composition. Measurement was performed as follows to determine the difference in adhesive strength (A−B).

As shown in Fig. 5, 650 / zm thick silicon wafer piece (50mm x 12mm) and 0.7mm thick non-alkali glass piece (50mm x 12mm) were polished on the surface of silicon wafer (V in the product state) Prepare test specimens (adhesive area: 12 mm x 12 mm, adhesive thickness: 10 m) using the adhesive composition as the adhesive surface, and connect the ends of the test piece vertically. The steel sheet was pulled up and down with a constant load, and the tensile shear strength was measured when both substrates were peeled off. The value was taken as the adhesive strength. The silicon wafer (baresilicon) and non-alkali glass (“# 1737” manufactured by Corning Co., Ltd.) used for preparing the test specimens were previously cleaned by RCA [W. Kern, DAPuotinen, RCA Review, 31 , pl87 (1970)]. Specifically, silicon wafer is SC-1 solution (H 0: NH OH: H 2 O = 5: 1: 1) 80. 10 in C tank

2 4 2 2

The organic matter contamination and metal contamination were removed for about a minute, and this was washed with ultrapure water. Next, using a solution of HF: H 2 O = 1: 50, the silicon oxide film formed on the silicon wafer in the previous process is

twenty two

Removed. After this, it is washed again with ultrapure water, and further SC-2 solution (H 0: HC1: HO = 6: 1 : 1) Residual metal contamination was removed in an 80 ° C bath, washed with ultrapure water and dried.

[0057] The measurement was performed using a Tensilon type tensile tester at a tensile speed of 1. 67 X 10 " ⁴ m / s at a predetermined temperature. To keep the test piece at the predetermined temperature, the ribbon was not touched. A glass tube wrapped around a heater (heater for sample heating) was placed, and the ribbon heater was heated and controlled by the temperature controller so that the temperature of the thermocouple attached to the test specimen reached the specified temperature. The figure shows the test piece for measuring the adhesive strength from the top, and the figure on the lower left shows the test piece with the lateral force.The silicon unit actually used in each example, the substrate, The adhesive strength when adhering was measured in the same manner.

[Example 1]

Cholesterol (Molecular weight; 386.7, Melting temperature: 150 ° C, Melting temperature range; 1 ° C, Melt viscosity; Adhesive strength A at 2 mPa's, 25 ° C and Adhesive strength B at 130 ° C; 0 2MPa) 0.354g was weighed into a columnar pressure molding machine with a diameter of 10mm, and 200kg'cm- ² pressure was applied for 3 minutes to obtain a cylindrical tablet with a diameter of 10mm and a thickness of 5.5mm.

[0059] The obtained tablet is placed on a 6-inch silicon wafer (thickness: 650 / zm) on which a plurality of semiconductor elements are formed, and a square SUS substrate having a thickness of 0.7 mm and a side of 20 cm is placed thereon, Placed in a vacuum oven. The SUS substrate used as the support was a substrate obtained by spin-coating a 5% isopropyl alcohol solution of hexamethyldisilazane, drying it, and subjecting the surface to hydrophobic treatment. When the vacuum oven (lOTorr) was heated to 160 ° C at a rate of l ° CZmin, the tablet melted and became liquid at a wafer temperature of about 148 ° C. At this point, when vacuum suction was stopped and degassing of the melted cholesterol under the reduced pressure of lOTorr for 2 minutes, cholesterol spread over the entire wafer surface. Vacuum oven force When the attached sample was taken out, the sample was cooled rapidly, so that cholesterol crystallized immediately and the two substrates were firmly bonded. A 6-inch silicon wafer with the same specifications as above and a SUS substrate were bonded together to produce a test piece similar to that shown in FIG. 5, and the tensile shear strength was measured. The bond strength was 5 MPa (25 ° C).

[0060] Next, using a commercially available polishing apparatus, the back surface of the wafer bonded to the SUS substrate was rough-polished, and then polished by a felt grindstone method using “Polisher DFP8140” manufactured by Disco Corporation to reduce the wafer thickness. 100 / zm. After polishing, do not touch the polished surface of the wafer adhered to the SUS substrate. Life film resist was laminated to form a 50 m hole pattern. During this time, stress was applied to the lamination temperature (100 ° C), alkali development and drying (120 ° C), wafers, supports and fixing agents, but the wafer was firmly adhered to the support.

[0061] Next, RI using CF as an etching gas with a 50 μm hole pattern as a mask

Four

By E, a through hole reaching the wafer surface was formed. After that, the SUS substrate is heated to melt the fixing agent, and the wafer is removed from the support, washed by immersing it in 40 ° C isopropyl alcohol for 1 minute, and has a through-hole with a back surface force vacant 100 m I got Thoroughly.

[0062] When the obtained wafer is diced into small pieces and the through hole is not formed and the defect rate of the semiconductor chip is compared with the case where the through hole is not formed, the defect rate is reduced even when a new back surface processing is performed to provide the through hole. There was no change. Figure 1 shows a model diagram of the above-mentioned caching method.

(Example 2)

In Example 1, instead of the 6-inch silicon wafer on which the semiconductor elements were formed, a thick-film resist ("THB series" manufactured by JSR Corporation) was used to apply solder bumps (Fig. 2) with a height of 65 μm to the wafer surface. A 6-inch wafer with a concavo-convex pattern, which is formed at intervals of 100 m and further formed with cutting grooves (5 mm square) with a depth of 80 m by pre-dicing, is replaced by the above chemical formula (8) (Molecular weight; 404.7, melting temperature: 223 ° C, melting temperature range: 1 ° C, melt viscosity; ImPa's. 5 g, release agent “KF54” (manufactured by Shin-Etsu Silicone) 0.15 g, A mixture with fine particles of silicon silicate silicon particles (manufactured by Shionogi & Co., Ltd., average particle size; 2; ζ ΐη) 0.09g (melting temperature; 223 ° C, melting temperature range; 1 ° C, melt viscosity; lmPa's, the difference between the adhesive strength A at 25 ° C and the adhesive strength B at 203 ° C; 0.3 MPa A wafer was bonded to the glass substrate in the same manner as in Example 1 except that a glass substrate was used instead of and the heating temperature of the vacuum oven was 240 ° C. When observed, the fixing agent uniformly penetrated into the groove portion of the pattern, and bubbles were not observed, and the 6-inch silicon wafer with the same concavo-convex pattern and the glass substrate were adhered to each other as shown in FIG. The same test piece was prepared and the adhesive strength was measured. The tensile shear strength was 4.5 MPa (25 ° C).

Next, after grinding and polishing the wafer to a thickness of 100 m in the same manner as in Example 1, “Polisher DFP8140J made by Sco Co., Ltd. was used to polish the felt to a thickness of 70 μm. During the polishing, the wafer was firmly fixed without peeling off the crow substrate force of the support.

In order to protect the polished surface with an insulating film, a photosensitive insulating film CiSR (“WPR1100”) 2 / zm was applied to the polished surface by spin coating, and the dicing groove was removed by exposure-development. Next, a wafer piece thinned to a thickness of 70 m and further cut into 3 mm squares was placed thereon. The laminate is heated to 240 ° C to melt the immobilizing agent, and with the insulating film “WP Rl 100” as an adhesive, a 5 mm square wafer piece (70 μm thickness) with solder bumps and a 3 mm square wafer piece ( 70 μm thick) was removed from the support.

[0064] A small piece in which a 3 mm square wafer piece was laminated on a 5 mm square wafer piece was immersed in a 40 ° C tantalum alcohol for 3 minutes to remove the fixing agent. The non-bumper bump formed on the 5mm square wafer maintained its initial state and did not drop off. Figure 3 shows a model diagram of the process.

(Example 3)

The wafer thinned to 100 m in Example 1 and formed with through-holes was directly set in a dicing apparatus (“DAD321” manufactured by Disco Corporation) to form dicing grooves in units of semiconductor elements. At this point, the semiconductor chip was fixed to the SUS substrate with a fixing agent that would not peel off in small pieces. Next, the SUS substrate was heated to 170 ° C, and the semiconductor chips were individually picked up with vacuum tweezers and separated from the SUS substrate as the support, and immersed in 40 ° C isopropanol for 3 minutes to remain attached to the device surface. The immobilizing agent was removed.

[0065] In the case where the chipping defect of the cut edge portion of the surface (semiconductor element surface) of each semiconductor chip was performed using a normal dicing tape ("Riva Alpha No. 3193M" manufactured by Nitto Denko Corporation) In comparison, the defect rate was reduced by about 30%.

(Example 4)

As shown in Fig. 4, the 6-inch silicon wafer on which the semiconductor device of Example 1 was formed was further drilled with a 50 m hole and a depth of 80 m, and a silicon nitride film was formed on the hole wall and device surface. , Via holes filled with copper plating and 20 via structures around the 3mm mouth element at equal intervals Formed. Polish this wafer to 100 m as in Example 1 and polish it uniformly on the front surface using a reactive ion etching system “RIE-10NR” manufactured by Samco. Etching was performed to a thickness of m. The thinned wafer was put together with the support (SUS substrate) in a clean oven adjusted under a nitrogen atmosphere and held at 140 ° C for 20 hours, but the wafer was held without any damage to the support.

[0066] The above results show that the wafer level burn-in test is normally performed at 125 ° C. Therefore, if a previously formed through copper wiring is used as a test terminal of a semiconductor element, the thinned state, that is, the chip immediately before mounting It shows that the operation test in the state can be performed.

(Example 5)

1-octadecanol 1.5 g (molecular weight; 270.5, melting temperature; 60 ° C., melting temperature range) as a fixing agent of a 6-inch wafer with a concavo-convex pattern and a glass substrate used in Example 2 1 ° C, melt viscosity; 1.5 mPa 's, bonded to each other by using the difference between adhesive strength A at 25 ° C and adhesive strength B at 40 ° C (0. IMPa). For bonding, a tablet-shaped immobilizing agent is placed on the wafer, placed in a vacuum oven, heated to 80 ° C with lOTorr, and then the distance between the wafer bottom and the glass substrate bottom is 1425 m [= 75 m + wafer thickness (650 μm) + glass substrate thickness (700 μm)] Each substrate was held and returned to normal pressure and cooled to solidify the immobilizing agent. When the surface roughness of the glass substrate was observed by microscopic observation of the concave / convex pattern of the wafer, the immobilizing agent uniformly penetrated into the groove portion of the pattern, and no bubbles were observed.

[0067] In the same manner as in Example 1, the bonded sample was roughly ground on the back surface of the wafer so that the wafer thickness was 50 m, and then polished with a disc grinder "Polisher DFP8140" using a felt grindstone method. The wafer thickness was 30 m. On the polished surface, a 5mm square dicing groove provided in advance on a 6-inch wafer appeared, and it was confirmed that the groove was filled with a fixing agent.

The thinned sample with the glass substrate down was placed on a hot plate and heated to 80 ° C. The chip divided into 5 mm squares can be easily picked up with vacuum tweezers, and the edge of the chip is not chipped, and the state is maintained.

[0068] (Comparative Example 1) A knock grind tape (“BGE-164VC” manufactured by Toyo Adtec Co., Ltd.) was applied to the surface of a 6-inch wafer with a concavo-convex pattern used in Example 2, and grinding and polishing were performed in the same manner as in Example 5 to reduce the wafer thickness to 30. m. When the polished surface was observed, there were many defects at the edge of the 5 mm square dicing groove provided in advance, and there was abrasive residue in the groove. The chip that was cut into 5 mm squares could not be peeled off with vacuum tweezers, and the chip broke when trying to remove it.

[0069] (Comparative Example 2)

The same as in Example 5, using a 6-inch wafer and glass substrate with the same uneven pattern as in Example 5 and using a water-soluble silicone wax having a melting temperature of 45 ° C. (“KF6004” manufactured by Shin-Etsu Chemical Co., Ltd.) as a fixing agent. Then, both substrates were bonded together by heating under vacuum. When observing the groove portion of the concave / convex pattern of the wafer from the glass substrate surface, bubbles were observed, but when the polished surface after grinding and polishing in the same procedure as in Example 5 was observed, the dicing groove portion There was a gap, and the chip edge part of that part was chipped. In addition, since KF6004 is water-soluble, there was a portion where KF6004 in the dicing groove was partially dissolved and separated by cleaning the polished surface. In order to protect the polished surface with an insulating film, a photosensitive insulating film QSR (“WPR1100”) 2 μm was applied to the polished surface by spin coating, and the immobilizing agent dissolved in WPR1100 and spin-coated. Chips were scattered during coating.

[0070] From Comparative Examples 1 and 2, the conventional method cannot obtain a chip thinned to a thickness of 30 μm in high yield, and the polished surface is additionally processed, for example, the back surface of the chip is an insulating film. I couldn't protect it with

Claims

The scope of the claims

[1] An adhesive composition containing, as a main component, a compound having a molecular weight of 1000 or less as a fixing agent for fixing the wafer and the support between the wafer surface on which the semiconductor element is formed and the support. Intervene,

The composition is heated and melted to bring the wafer and the support into close contact, and then cooled to bond and fix the unit and the support,

By thinning the backside of the wafer,

Heat-melting the composition to separate the wafer and the support

A wafer processing method.

[2] The wafer processing method according to [1], wherein the compound is a compound having a steroid skeleton or a hydroxyl group in the molecule or a derivative thereof.

[3] The wafer processing method according to [1], wherein the compound is a compound having a steroid skeleton and a hydroxyl group in the molecule or a derivative thereof.

[4] The melting temperature at the melting peak value measured with a differential scanning calorimeter of the above compound is 50 to 300 ° C., and the starting point of the melting peak value measured with the differential scanning calorimeter of the above composition is 2. The wafer processing method according to claim 1, wherein a melting temperature range represented by a temperature difference at the end point is 30 ° C. or less.

[5] The wafer processing method according to [1], wherein in the step of polishing the back surface of the wafer, the wafer is thinned to 20 to L00 m.

[6] When the adhesive strength at 25 ± 2 ° C of the above composition is A (MPa) and the adhesive strength at a temperature 20 ° C lower than the melting temperature of the composition is B (MPa), the adhesive strength 2. The wafer processing method according to claim 1, wherein A and B satisfy the following formula (1).

0 <A-B <0.5 (MPa) (1)

[7] The wafer processing method according to [1], wherein the composition is in the form of a tablet.

8. The wafer processing method according to claim 1, wherein the wafer has on its surface a semiconductor element formed in a region partitioned by a plurality of die cinder streets.

[9] The cutting groove according to claim 8, wherein a cutting groove is formed in the die cinder street. The wafer processing method described.

10. The wafer processing method according to claim 9, wherein the wafer is thinned by polishing until the cutting groove is exposed, and is cut into semiconductor chips, and the support force is peeled off in units of the semiconductor chips.

[11] The wafer is a wafer in which a hole having a predetermined depth is formed on the surface, an inner wall of the hole is covered with an insulating film, and a conductive electrode material is embedded in the hole covered with the insulating film. The wafer processing method according to claim 1, wherein:

12. The wafer processing method according to claim 1, wherein the wafer has a protruding electrode for conduction.

[13] The wafer according to claim 1, wherein after the wafer is thinned by the polishing, the polished surface is further processed to form at least one selected from a structure, a wiring, and an element. Processing method.