WO2006091283A3 - Memory device and method having multiple internal data buses and memory bank interleaving - Google Patents

Memory device and method having multiple internal data buses and memory bank interleaving Download PDF

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Publication number
WO2006091283A3
WO2006091283A3 PCT/US2006/001153 US2006001153W WO2006091283A3 WO 2006091283 A3 WO2006091283 A3 WO 2006091283A3 US 2006001153 W US2006001153 W US 2006001153W WO 2006091283 A3 WO2006091283 A3 WO 2006091283A3
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WO
WIPO (PCT)
Prior art keywords
data buses
banks
coupled
write data
read data
Prior art date
Application number
PCT/US2006/001153
Other languages
French (fr)
Other versions
WO2006091283A2 (en
Inventor
Joseph M Jeddeloh
Original Assignee
Micron Technology Inc
Joseph M Jeddeloh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Joseph M Jeddeloh filed Critical Micron Technology Inc
Priority to EP06718248A priority Critical patent/EP1866769A4/en
Priority to JP2007557019A priority patent/JP4843821B2/en
Priority to KR1020077021995A priority patent/KR100908760B1/en
Publication of WO2006091283A2 publication Critical patent/WO2006091283A2/en
Publication of WO2006091283A3 publication Critical patent/WO2006091283A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A memory device and method receives write data through a unidirectional downstream bus (30) and outputs read data through a unidirectional upstream bus (32). The downstream bus (30) is coupled to a pair of internal write data bus (46a, b), and the upstream bus (32) is coupled to a pair of internal read data buses (48a, b). A first set of multiplexers (70a) selectively couple each of the internal write data buses to any of a plurality of banks of memory cells. Similarly, a second set of multiplexers (70b) selectively couple each of the banks of memory cells to any of the internal read data buses. Write data can be coupled to one of the banks concurrently with coupling read data from another of the banks. Also, write data may be concurrently coupled from respective write data buses to two different banks, and read data may be concurrently coupled from two different banks to respective read data buses.
PCT/US2006/001153 2005-02-23 2006-01-11 Memory device and method having multiple internal data buses and memory bank interleaving WO2006091283A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06718248A EP1866769A4 (en) 2005-02-23 2006-01-11 Memory device and method having multiple internal data buses and memory bank interleaving
JP2007557019A JP4843821B2 (en) 2005-02-23 2006-01-11 Memory device and method having multiple internal data buses and memory bank interleaving
KR1020077021995A KR100908760B1 (en) 2005-02-23 2006-01-11 Method and memory device having multiple internal data buses and memory bank interleaving

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/064,543 US7209405B2 (en) 2005-02-23 2005-02-23 Memory device and method having multiple internal data buses and memory bank interleaving
US11/064,543 2005-02-23

Publications (2)

Publication Number Publication Date
WO2006091283A2 WO2006091283A2 (en) 2006-08-31
WO2006091283A3 true WO2006091283A3 (en) 2009-04-23

Family

ID=36914190

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/001153 WO2006091283A2 (en) 2005-02-23 2006-01-11 Memory device and method having multiple internal data buses and memory bank interleaving

Country Status (7)

Country Link
US (2) US7209405B2 (en)
EP (1) EP1866769A4 (en)
JP (1) JP4843821B2 (en)
KR (1) KR100908760B1 (en)
CN (1) CN101310339A (en)
TW (1) TW200639635A (en)
WO (1) WO2006091283A2 (en)

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Also Published As

Publication number Publication date
EP1866769A2 (en) 2007-12-19
US20060250879A1 (en) 2006-11-09
WO2006091283A2 (en) 2006-08-31
JP2008532140A (en) 2008-08-14
EP1866769A4 (en) 2011-11-02
JP4843821B2 (en) 2011-12-21
KR20070107163A (en) 2007-11-06
TW200639635A (en) 2006-11-16
CN101310339A (en) 2008-11-19
KR100908760B1 (en) 2009-07-22
US7209405B2 (en) 2007-04-24
US20060190671A1 (en) 2006-08-24
US7260015B2 (en) 2007-08-21

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