WO2006100641A2

WO2006100641A2 - Static random access memory cells with shared contacts

Info

Publication number: WO2006100641A2
Application number: PCT/IB2006/050865
Authority: WO
Inventors: Christophe Couderc
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-03-24
Filing date: 2006-03-21
Publication date: 2006-09-28
Also published as: WO2006100641A3

Abstract

A semiconductor device for a SRAM cell, the device having an active region (110) and a gate head (106), and a shared contact (30) therebetween for connection to a common supply voltage. The contact (30) is formed as an elongate, substantially rectangular, contact by means of an optical proximity connection (OPC) technique. An end of the contact (30) overlaying the gate head (106) is provided with a lateral extension (30a) (by means of phase shifting the mask used to form the contact) so as to extend the surface contact area between the lateral extension (30a) and the gate head (106).

Description

Static Random Access Memory Cells with Shared Contacts

FIELD OF THE INVENTION

This invention relates generally to a semiconductor device for use in, for example, a static random access memory cell with shared contacts between the poly- silicon gate and active layers.

BACKGROUND OF THE INVENTION

A static random access memory (SRAM) is a memory chip that requires power to hold its content, i.e. it retains data bits in its memory as long as power is being supplied. It is made up of a flip-flop circuit that lets current flow through one side or the other, based on which one of two select transistors is activated. Unlike dynamic random access memory (DRAM), SRAM does not require refresh circuitry for periodically refreshing the cells. SRAM also provides faster access to data than DRAM. However, it also takes up more space, uses more power and tends to be more expensive. SRAM is commonly used for a computer's cache memory and as part of the random access memory digital-to-analogue converter on a video card, for example.

Figure 1 of the drawings illustrates a commonly used six-transistor (6T) SRAM cell. A first inverter 10 comprising a P-channel transistor 12 and an N-channel transistor 14, and a second inverter 20 comprising a P-channel transistor 22 and an N-channel transistor 24 which are interconnected in a known fashion to form a latch. A first N-channel select transistor 16 couples the latch to a first bit line BLB and a second N-channel select transistor 18 couples the latch to a second bit line BL. The gates of the N-channel select transistors 16, 18 are coupled to a word line WL. Referring to Figure 2 of the drawings, a known structure of a semiconductor device used in an SRAM cell, as described in US Patent Application Publication No. US 2002/0195686 Al, comprises a semiconductor substrate 100 formed with an isolation layer 102 for isolating an active region 110. A gate insulation layer 108 is provided on the substrate and then a poly-silicon layer 106 is provided over the entire surface of the semiconductor substrate, including the gate insulation layer 108, thereby forming a gate electrode layer. The gate electrode layer is then patterned to form a couple of gate patterns 104 crossing a top part of a desired region of the gate insulation layer 108 having on each side conventional spacers 11, and an etch stopping layer 17 is formed over the entire surface. Next, an interlayer insulation layer 19 is formed over the entire surface of the semiconductor substrate, including the etch stopping layer 17, and the interlayer insulation layer 19 and the etch stopping layer 17 are continuously patterned to form a contact hole 23, which exposes a portion of the gate layer 104 and the neighboring active region 110. The contact hole 23 are filled with a metal to form a shared contact 30, as shown in Figure 3 of the drawings, for connecting the poly-silicon layer 106 and active areas 110 to the same supply voltage.

In prior art arrangements, the shared contact 30 is of rectangular shape. However, printing the contact 30 in this manner results in a very sensitive process in terms of overlay between the poly-silicon layer (i.e. the gate electrode layer) and contact layers. In the case of misalignment, the prior art configuration results in failure of SRAM cells because the poly- silicon layer and contact layers will not be in contact with each other due to the relatively small overlay area therebetween.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an SRAM cell, and method of fabricating the same, wherein the overlay area between the poly- silicon layer and contact layers is increased, thereby improving electrical connection therebetween and reducing the risk of failure of the SRAM cell. In accordance with the present invention, there is provided a method of fabricating a semiconductor device comprising a semiconductor substrate having an active region and a gate layer defining at least one gate head adjacent said active region, the method comprising forming an elongate shared contact overlaying said gate head and said active region adjacent thereto, and forming a laterally extended region in respect of an end portion of said shared contact overlaying said gate head so as to extend the overlay area thereof relative to said gate head.

Thus, the method proposed by the present invention involves extending the end portion of an elongate contact overlaying the gate layer, preferably being formed by means of a conventional optical proximity correction technique, so as to increase its surface area and, therefore, the contact area of the contact relative to the gate head. In a preferred embodiment, the lateral extension is formed, following optical proximity correction treatment, by shifting a mask used to form the contact relative to the gate head such that the edge of the contact overlaying the gate head is shifted laterally, so as to achieve the desired lateral extension. The present invention extends to a semiconductor device fabricated in accordance with a method as defined above, and comprising a semiconductor substrate having an active region and a gate layer defining at least one gate head adjacent said active region, and further comprising an elongate shared contact overlaying the gate head and adjacent active region for connection to a common supply voltage, an end of said contact having a laterally extended portion relative to longitudinal edge thereof so as to extend the overlay area thereof relative to said gate head. The present invention extends further to a SRAM cell comprising one or more semiconductor devices as defined above.

These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiments described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which:

Figure 1 is a circuit diagram illustrating the configuration of a conventional six- transistor SRAM cell;

Figure 2 is a schematic cross-sectional diagram illustrating the structure of a conventional SRAM cell having a shared contact between poly-silicon and active layers; Figure 3 is a schematic plan view of a conventional SRAM cell having a shared contact between poly-silicon and active layers;

Figures 4a and 4b are schematic cross-sectional views illustrating a fabrication method according to an exemplary embodiment of the invention;

Figure 5 is a plan view of an elongate shared contact formed in accordance with a method according to an exemplary embodiment of the present invention; and

Figures 6a, 6b and 6c are schematic views illustrating an elongate shared contact, including lateral extension, fabricated in accordance with a method according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Figure 4a shows a simplified cross-sectional view of a substrate 100 having a transistor device 104 fabricated thereon. In this example, the transistor device 104 is formed between shallow trench isolation (STI) regions 102 which are used to isolate neighboring transistors throughout an integrated circuit design. During the fabrication of the transistor device 104, a gate oxide 108 and a poly-silicon gate 106 are formed, before an impurity implant 112 is performed. As is well known in the art, the impurity implants 112 are performed to form diffusion regions 110a, 110b (i.e. active regions 110) which will function as either a source or a drain depending on the wiring of the transistor device 104. During the design of the poly- silicon gate 106, a mask design is created such that the poly- silicon gate will extend over the entire width of the transistor device. Unfortunately due to optical proximity effects, the ideal mask design that is used to define the poly- silicon gate 106 will experience optical proximity shrinking, rounding and even alignment tolerances, and such optical proximity shrinking is a commonplace problem in the design of sub-micron technology devices, often significantly impacting transistor device functionality. Thus, to combat this known optical proximity effect, a number of optical proximity correction (OPC) software tools have been proposed to add (or subtract) correction features in respect of desired locations following a complete analysis of the mask by the software to suggest locations for correction features. Similarly, as shown in figure 4b, another mask design is created to print the poly- silicon/active layer shared contacts 30 for connection to the same supply voltage and printing the contact 30 in this manner results in a very sensitive process in terms of overlay between the poly-silicon and contact layers. In case of misalignment (caused, for example, by the above-mentioned optical proximity effects), the resultant configuration may very well be responsible for the failure of SRAM cells because the poly- silicon and metal layers will remain un-contacted due to the very small overlay area between them.

Thus, once again, OPC techniques are employed to negate any undesirable distortion effects during pattern transfer. OPC works by making small changes to the integrated circuit (IC) layout that anticipate these distortions. To compensate for line-end shortening, the line is extended using a hammerhead shape that results in a line in the resist that is much closer to the intended layout. To compensate for corner rounding, serif shapes are added to (or subtracted from) corners to produce corners in the configuration that are much closer to the ideal layout. However, it has been determined that, even with conventional OPC correction techniques, there is still a significant risk that the poly-silicon and metal layers will remain un-contacted due to the very small overlay area between them. Also, if line-end reduction on the poly- silicon lines is too high, the risk that there will be no overlay between the poly- silicon and contact layers is high. This leads, on the one hand, to a very sensitive process in terms of overlay but also a sensitive process in terms of the process window as critical dimension (CD) variation (and mainly CD reductions) lead to a greater risk of non-contacted layers.

Thus, it is proposed in accordance with the present invention to resolve this process sensitivity by changing the shape of the printed contact 30 from a straight trench over the poly-silicon head 106 and the active area 110 to a curved trench contact having a "bean" like shape at the poly-silicon head 106 in order to increase the overlay area between the poly- silicon and active layers 106, 110. The curved "bean" shape is achieved in accordance with an exemplary embodiment of the present invention by employing OPC techniques in respect of the contact so as to improve electrical connection between the poly-silicon and active layers 106, 110 of the device.

Conventional OPC treatment used during printing of the shared contact 30 results in an elongate, substantially rectangular contact, as shown in Figure 5 of the drawings. In this exemplary embodiment of the present invention, the above-mentioned object is achieved by modifying the post-OPC contact polygons so that the overlay printed area between poly- silicon and contact layers 106, 30 is increased, and the resultant shared contact 30 is the result of the conventional OPC solution and a lateral extension (i.e. the area 30a) of the contact 30 over the poly-silicon head 106.

Thus, referring to Figures 6a and 6b of the drawings, the several contours illustrate the printed results when the contact 30 on the poly- silicon head 106 is extended with, for example, a 5nm step, and it can be clearly seen that there is a significant improvement in terms of overlay between the contact and poly-silicon layers 30, 106. Moreover, there is an enhancement in terms of the length of the contact 30. As can be more clearly seen in Figure 6c of the drawings, the substantially rectangular contact resulting from the conventional solution is denoted by reference numeral 30 and the lateral extension with (in this case) a 35nm extend is defined by the outermost contour and is denoted by reference numeral 30a. It will be appreciated that, for example, generating a lateral extension by a single 5nm step will not increase the overlay area by much, whereas using, say, 20 nm or even 35 nm steps will increase the overlay area significantly and result in the advantages afforded by the present invention. The overlay margin created by the procedure proposed by the present invention enhances the electrical connection between the active and poly-silicon layers of a semiconductor device so as to reduce the process sensitivity to overlay. The process window is thereby also increased. The modification proposed by the present invention to conventional Optical Proximity Correction treatment may be applied to CMOS065 technology development for the shared contact so that the layer-to-layer process sensitivity can be decreased. More generally, the present invention is envisaged to be particularly, but not necessarily exclusively, useful for SRAM cells designed for CMOS090 nodes and smaller. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice- versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of fabricating a semiconductor device comprising a semiconductor substrate (100) having an active region (110) and a gate layer (104) defining at least one gate head (106) adjacent said active region (110), the method comprising:

- forming an elongate shared contact (30) overlaying said gate head (106) and said active region (110) adjacent thereto, and

- forming a laterally extended region (30a) in respect of an end portion of said shared contact (30) overlaying said gate head (106) so as to extend the overlay area thereof relative to said gate head (106).

2. A method according to claim 1, wherein said shared contact (30) is formed by means of an optical proximity connection technique.

3. A method according to claim 2, wherein said lateral extension (30a) is formed, following said optical proximity connection, by shifting a mask used to form said contact (30) relative to the gate head (106).

4. A semiconductor device comprising a semiconductor substrate (100) having an active region (110) and a gate layer (104) defining at least one gate head (106) adjacent said active region (110), and further comprising an elongate shared contact (30) overlaying the gate head (106) and adjacent active region (110) for connection to a common supply voltage, an end of said contact (30) having a laterally extended portion (30a) relative to longitudinal edge thereof so as to extend the overlay area thereof relative to said gate head.

5. A SRAM cell comprising one of more semiconductor devices according to claim 4.