WO2006117683A3 - Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction - Google Patents

Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction Download PDF

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Publication number
WO2006117683A3
WO2006117683A3 PCT/IB2006/001529 IB2006001529W WO2006117683A3 WO 2006117683 A3 WO2006117683 A3 WO 2006117683A3 IB 2006001529 W IB2006001529 W IB 2006001529W WO 2006117683 A3 WO2006117683 A3 WO 2006117683A3
Authority
WO
WIPO (PCT)
Prior art keywords
graphics
display system
silicon chip
system employing
employing multiple
Prior art date
Application number
PCT/IB2006/001529
Other languages
French (fr)
Other versions
WO2006117683A2 (en
Inventor
Reuven Bakalash
Offir Remez
Efi Fogel
Original Assignee
Lucid Information Technology Ltd
Reuven Bakalash
Offir Remez
Efi Fogel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/883,104 priority Critical patent/US20090096798A1/en
Priority to JP2007552758A priority patent/JP2008538620A/en
Priority to CA002595085A priority patent/CA2595085A1/en
Priority to CN200680002976A priority patent/CN101849227A/en
Priority to EP06765491A priority patent/EP1846834A2/en
Application filed by Lucid Information Technology Ltd, Reuven Bakalash, Offir Remez, Efi Fogel filed Critical Lucid Information Technology Ltd
Publication of WO2006117683A2 publication Critical patent/WO2006117683A2/en
Priority to US12/077,072 priority patent/US20090027383A1/en
Priority to US12/231,295 priority patent/US20090128550A1/en
Priority to US12/231,304 priority patent/US8284207B2/en
Priority to US12/231,296 priority patent/US20090179894A1/en
Publication of WO2006117683A3 publication Critical patent/WO2006117683A3/en
Priority to US13/646,710 priority patent/US20130120410A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00—Indexing scheme for image generation or computer graphics
    • G06T2210/52—Parallel processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Abstract

A high performance graphics processing and display system architecture realized on a monolithic silicon chip, supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.
PCT/IB2006/001529 2003-11-19 2006-01-25 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction WO2006117683A2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US11/883,104 US20090096798A1 (en) 2005-01-25 2006-01-25 Graphics Processing and Display System Employing Multiple Graphics Cores on a Silicon Chip of Monolithic Construction
JP2007552758A JP2008538620A (en) 2005-01-25 2006-01-25 Graphics processing and display system using multiple graphics cores on a monolithic silicon chip
CA002595085A CA2595085A1 (en) 2005-01-25 2006-01-25 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
CN200680002976A CN101849227A (en) 2005-01-25 2006-01-25 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
EP06765491A EP1846834A2 (en) 2005-01-25 2006-01-25 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US12/077,072 US20090027383A1 (en) 2003-11-19 2008-03-14 Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US12/231,296 US20090179894A1 (en) 2003-11-19 2008-08-29 Computing system capable of parallelizing the operation of multiple graphics processing pipelines (GPPLS)
US12/231,295 US20090128550A1 (en) 2003-11-19 2008-08-29 Computing system supporting parallel 3D graphics processes based on the division of objects in 3D scenes
US12/231,304 US8284207B2 (en) 2003-11-19 2008-08-29 Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations
US13/646,710 US20130120410A1 (en) 2003-11-19 2012-10-07 Multi-pass method of generating an image frame of a 3d scene using an object-division based parallel graphics rendering process

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US64714605P 2005-01-25 2005-01-25
US60/647,146 2005-01-25
US11/340,402 US7812844B2 (en) 2004-01-28 2006-01-25 PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application
US11/340,402 2006-01-25

Related Parent Applications (3)

Application Number Title Priority Date Filing Date
US10/579,682 Continuation-In-Part US7808499B2 (en) 2003-11-19 2004-11-19 PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
PCT/IL2004/001069 Continuation-In-Part WO2005050557A2 (en) 2003-11-19 2004-11-19 Method and system for multiple 3-d graphic pipeline over a pc bus
US57968207A Continuation-In-Part 2003-11-19 2007-03-23

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/340,402 Continuation-In-Part US7812844B2 (en) 2003-11-19 2006-01-25 PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application
US12/077,072 Continuation-In-Part US20090027383A1 (en) 2003-11-19 2008-03-14 Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition

Publications (2)

Publication Number Publication Date
WO2006117683A2 WO2006117683A2 (en) 2006-11-09
WO2006117683A3 true WO2006117683A3 (en) 2009-05-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/001529 WO2006117683A2 (en) 2003-11-19 2006-01-25 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction

Country Status (6)

Country Link
US (19) US7812844B2 (en)
EP (1) EP1846834A2 (en)
JP (1) JP2008538620A (en)
CN (1) CN101849227A (en)
CA (1) CA2595085A1 (en)
WO (1) WO2006117683A2 (en)

Families Citing this family (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1890660A (en) 2003-11-19 2007-01-03 路西德信息技术有限公司 Method and system for multiple 3-d graphic pipeline over a PC bus
US9363481B2 (en) * 2005-04-22 2016-06-07 Microsoft Technology Licensing, Llc Protected media pipeline
US7423651B2 (en) * 2005-10-13 2008-09-09 V. R. Technology Co., Ltd. Single-chip multi-output graphic system
US7483032B1 (en) * 2005-10-18 2009-01-27 Nvidia Corporation Zero frame buffer
US7705850B1 (en) * 2005-11-08 2010-04-27 Nvidia Corporation Computer system having increased PCIe bandwidth
US7948497B2 (en) * 2005-11-29 2011-05-24 Via Technologies, Inc. Chipset and related method of processing graphic signals
US7546574B2 (en) * 2005-12-02 2009-06-09 Gauda, Inc. Optical proximity correction on hardware or software platforms with graphical processing units
US7685371B1 (en) * 2006-04-19 2010-03-23 Nvidia Corporation Hierarchical flush barrier mechanism with deadlock avoidance
US7659901B2 (en) * 2006-07-24 2010-02-09 Microsoft Corporation Application program interface for programmable graphics pipeline
US7969443B2 (en) * 2006-08-01 2011-06-28 Nvidia Corporation System and method for dynamically processing content being communicated over a network for display purposes
US7961192B2 (en) * 2006-08-01 2011-06-14 Nvidia Corporation Multi-graphics processor system and method for processing content communicated over a network for display purposes
US9275430B2 (en) 2006-12-31 2016-03-01 Lucidlogix Technologies, Ltd. Computing system employing a multi-GPU graphics processing and display subsystem supporting single-GPU non-parallel (multi-threading) and multi-GPU application-division parallel modes of graphics processing operation
US11714476B2 (en) 2006-12-31 2023-08-01 Google Llc Apparatus and method for power management of a computing system
US7940261B2 (en) * 2007-01-10 2011-05-10 Qualcomm Incorporated Automatic load balancing of a 3D graphics pipeline
EP1990774A1 (en) * 2007-05-11 2008-11-12 Deutsche Thomson OHG Renderer for presenting an image frame by help of a set of displaying commands
GB0715000D0 (en) * 2007-07-31 2007-09-12 Symbian Software Ltd Command synchronisation
US7982742B2 (en) * 2007-09-06 2011-07-19 Dell Products L.P. System and method for an information handling system having an external graphics processor system for operating multiple monitors
GB0723536D0 (en) * 2007-11-30 2008-01-09 Imagination Tech Ltd Multi-core geometry processing in a tile based rendering system
KR100980449B1 (en) * 2007-12-17 2010-09-07 한국전자통신연구원 Method and system for rendering of parallel global illumination
KR100969322B1 (en) 2008-01-10 2010-07-09 엘지전자 주식회사 Data processing unit with multi-graphic controller and Method for processing data using the same
US8477143B2 (en) 2008-03-04 2013-07-02 Apple Inc. Buffers for display acceleration
US8289333B2 (en) * 2008-03-04 2012-10-16 Apple Inc. Multi-context graphics processing
WO2009118731A2 (en) 2008-03-27 2009-10-01 Rocketick Technologies Ltd Design simulation using parallel processors
US8319782B2 (en) * 2008-07-08 2012-11-27 Dell Products, Lp Systems and methods for providing scalable parallel graphics rendering capability for information handling systems
KR101607495B1 (en) * 2008-07-10 2016-03-30 로케틱 테크놀로지즈 리미티드 Efficient parallel computation of dependency problems
US9032377B2 (en) 2008-07-10 2015-05-12 Rocketick Technologies Ltd. Efficient parallel computation of dependency problems
US7930519B2 (en) * 2008-12-17 2011-04-19 Advanced Micro Devices, Inc. Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit
US8248535B2 (en) * 2009-02-18 2012-08-21 Csr Technology Inc. System and method for a versatile display pipeline architecture for an LCD display panel
US9336028B2 (en) * 2009-06-25 2016-05-10 Apple Inc. Virtual graphics device driver
US9142057B2 (en) 2009-09-03 2015-09-22 Advanced Micro Devices, Inc. Processing unit with a plurality of shader engines
US8400458B2 (en) * 2009-09-09 2013-03-19 Hewlett-Packard Development Company, L.P. Method and system for blocking data on a GPU
US20110212761A1 (en) * 2010-02-26 2011-09-01 Igt Gaming machine processor
US8798386B2 (en) * 2010-04-22 2014-08-05 Broadcom Corporation Method and system for processing image data on a per tile basis in an image sensor pipeline
US20120159090A1 (en) * 2010-12-16 2012-06-21 Microsoft Corporation Scalable multimedia computer system architecture with qos guarantees
US20120218277A1 (en) * 2011-02-25 2012-08-30 ST-Ericcson SA Display list mechanism and scalable display engine structures
US8786619B2 (en) 2011-02-25 2014-07-22 Adobe Systems Incorporated Parallelized definition and display of content in a scripting environment
US9128748B2 (en) 2011-04-12 2015-09-08 Rocketick Technologies Ltd. Parallel simulation using multiple co-simulators
US9886899B2 (en) * 2011-05-17 2018-02-06 Ignis Innovation Inc. Pixel Circuits for AMOLED displays
US9092267B2 (en) * 2011-06-20 2015-07-28 Qualcomm Incorporated Memory sharing in graphics processing unit
US10013731B2 (en) * 2011-06-30 2018-07-03 Intel Corporation Maximizing parallel processing in graphics processors
JP5361962B2 (en) * 2011-08-25 2013-12-04 株式会社東芝 Graphics processing unit and information processing apparatus
US10217270B2 (en) 2011-11-18 2019-02-26 Intel Corporation Scalable geometry processing within a checkerboard multi-GPU configuration
US9619855B2 (en) 2011-11-18 2017-04-11 Intel Corporation Scalable geometry processing within a checkerboard multi-GPU configuration
WO2014084419A1 (en) * 2012-11-29 2014-06-05 Lee Eun-Suk Computer capable of providing set content through screen while power is off
CN103064657B (en) * 2012-12-26 2016-09-28 深圳中微电科技有限公司 Realize the method and device applying parallel processing on single processor more
US9348602B1 (en) 2013-09-03 2016-05-24 Amazon Technologies, Inc. Resource allocation for staged execution pipelining
KR102244620B1 (en) 2014-09-05 2021-04-26 삼성전자 주식회사 Method and apparatus for controlling rendering quality
WO2016074166A1 (en) * 2014-11-12 2016-05-19 Intel Corporation Live migration of virtual machines from/to host computers with graphics virtualization
US20180081847A1 (en) * 2015-03-27 2018-03-22 Intel Corporation Dynamic configuration of input/output controller access lanes
US9622182B2 (en) * 2015-04-17 2017-04-11 Suunto Oy Embedded computing device
US10796397B2 (en) * 2015-06-12 2020-10-06 Intel Corporation Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices
US11295506B2 (en) 2015-09-16 2022-04-05 Tmrw Foundation Ip S. À R.L. Chip with game engine and ray trace engine
JP6766495B2 (en) * 2016-07-21 2020-10-14 富士通株式会社 Programs, computers and information processing methods
KR20180038793A (en) * 2016-10-07 2018-04-17 삼성전자주식회사 Method and apparatus for processing image data
KR102644276B1 (en) * 2016-10-10 2024-03-06 삼성전자주식회사 Apparatus and method for processing graphic
CN106648547A (en) * 2016-12-12 2017-05-10 中国航空工业集团公司西安航空计算技术研究所 Distributed unified management method for GPU graphic state parameters
JP6550418B2 (en) * 2017-04-03 2019-07-24 エンパイア テクノロジー ディベロップメント エルエルシー online game
US10872394B2 (en) * 2017-04-27 2020-12-22 Daegu Gyeongbuk Institute Of Science And Technology Frequent pattern mining method and apparatus
EP3676710A4 (en) * 2017-08-31 2021-07-28 Rail Vision Ltd System and method for high throughput in multiple computations
US11301951B2 (en) * 2018-03-15 2022-04-12 The Calany Holding S. À R.L. Game engine and artificial intelligence engine on a chip
CN112005218B (en) * 2018-04-28 2024-01-30 华为技术有限公司 Method, device and system for distributing power of image processor
CN110032597B (en) * 2018-11-30 2023-04-11 创新先进技术有限公司 Visual processing method and device for operation behaviors of application program
CN109408456B (en) * 2018-12-07 2023-08-29 中国地质大学（武汉） S905D chip and STM32 chip based cooperative hardware circuit
US11625884B2 (en) 2019-06-18 2023-04-11 The Calany Holding S. À R.L. Systems, methods and apparatus for implementing tracked data communications on a chip
CN110335190A (en) * 2019-06-20 2019-10-15 合肥芯碁微电子装备有限公司 Direct-write type lithography machine data expanding method based on CUDA
US11475601B2 (en) * 2019-10-21 2022-10-18 Google Llc Image decoding during bitstream interruptions
CN111221771B (en) * 2019-11-18 2023-04-28 天津津航计算技术研究所 GPU blade device suitable for VPX framework
CN111045623B (en) * 2019-11-21 2023-06-13 中国航空工业集团公司西安航空计算技术研究所 Method for processing graphics commands in multi-GPU splicing environment
CN110895788A (en) * 2019-11-29 2020-03-20 上海众链科技有限公司 System for enhancing graphic processing capability and external device
CN113129205A (en) * 2019-12-31 2021-07-16 华为技术有限公司 Electronic equipment and computer system
US11263718B2 (en) 2020-02-03 2022-03-01 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against in interleaved screen regions before rendering
US11170461B2 (en) 2020-02-03 2021-11-09 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis while rendering
US11508110B2 (en) 2020-02-03 2022-11-22 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
US11514549B2 (en) 2020-02-03 2022-11-29 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by generating information in one rendering phase for use in another rendering phase
US11321800B2 (en) * 2020-02-03 2022-05-03 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by region testing while rendering
US11080814B1 (en) 2020-02-03 2021-08-03 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using prior frame information
US11120522B2 (en) * 2020-02-03 2021-09-14 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by subdividing geometry
CN111491059B (en) * 2020-04-09 2021-08-10 上海众链科技有限公司 Image rendering enhancement system and method
CN112419147B (en) * 2020-04-14 2023-07-04 上海哔哩哔哩科技有限公司 Image rendering method and device
US11315209B2 (en) * 2020-05-08 2022-04-26 Black Sesame Technolgies Inc. In-line and offline staggered bandwidth efficient image signal processing
CN115117045A (en) * 2021-03-19 2022-09-27 上海寒武纪信息科技有限公司 Packaging frame for chip, processing method and related product
US11662798B2 (en) 2021-07-30 2023-05-30 Advanced Micro Devices, Inc. Technique for extended idle duration for display to improve power consumption
KR20240032993A (en) * 2021-08-11 2024-03-12 애플 인크. Logic slot to hardware slot mapping for graphics processors
CN113849448A (en) * 2021-09-28 2021-12-28 联想(北京)有限公司 Electronic equipment
CN115100022B (en) * 2022-08-23 2022-12-06 芯动微电子科技(珠海)有限公司 Graphic processing method and system

Family Cites Families (226)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104923B2 (en) 1988-12-28 1995-11-13 工業技術院長 Parallel image display processing method
US5392391A (en) * 1991-10-18 1995-02-21 Lsi Logic Corporation High performance graphics applications controller
CA2073516A1 (en) 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
JPH07325934A (en) 1992-07-10 1995-12-12 Walt Disney Co:The Method and equipment for provision of graphics enhanced to virtual world
JP3199205B2 (en) 1993-11-19 2001-08-13 株式会社日立製作所 Parallel processing unit
US5495419A (en) 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
US5734874A (en) * 1994-04-29 1998-03-31 Sun Microsystems, Inc. Central processing unit with integrated graphics functions
EP0693737A3 (en) 1994-07-21 1997-01-08 Ibm Method and apparatus for managing multiprocessor graphical workload distribution
US5745762A (en) 1994-12-15 1998-04-28 International Business Machines Corporation Advanced graphics driver architecture supporting multiple system emulations
US5687357A (en) 1995-04-14 1997-11-11 Nvidia Corporation Register array for utilizing burst mode transfer on local bus
US5754866A (en) 1995-05-08 1998-05-19 Nvidia Corporation Delayed interrupts with a FIFO in an improved input/output architecture
US5909595A (en) 1995-05-15 1999-06-01 Nvidia Corporation Method of controlling I/O routing by setting connecting context for utilizing I/O processing elements within a computer system to produce multimedia effects
US5623692A (en) 1995-05-15 1997-04-22 Nvidia Corporation Architecture for providing input/output operations in a computer system
US5758182A (en) 1995-05-15 1998-05-26 Nvidia Corporation DMA controller translates virtual I/O device address received directly from application program command to physical i/o device address of I/O device on device bus
US5794016A (en) 1995-12-11 1998-08-11 Dynamic Pictures, Inc. Parallel-processor graphics architecture
US5838756A (en) * 1996-01-08 1998-11-17 Kabushiki Kaisha Toshiba Radiation computed tomography apparatus
KR100269106B1 (en) 1996-03-21 2000-11-01 윤종용 Multiprocessor graphics system
WO1998007266A1 (en) 1996-08-14 1998-02-19 Northern Telecom Limited Internet-based telephone call manager
US5797016A (en) * 1996-10-29 1998-08-18 Cheyenne Software Inc. Regeneration agent for back-up software
US5977997A (en) * 1997-03-06 1999-11-02 Lsi Logic Corporation Single chip computer having integrated MPEG and graphical processors
US6118462A (en) 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
US6169553B1 (en) 1997-07-02 2001-01-02 Ati Technologies, Inc. Method and apparatus for rendering a three-dimensional scene having shadowing
US6201545B1 (en) 1997-09-23 2001-03-13 Ati Technologies, Inc. Method and apparatus for generating sub pixel masks in a three dimensional graphic processing system
US6856320B1 (en) 1997-11-25 2005-02-15 Nvidia U.S. Investment Company Demand-based memory system for graphics applications
US6337686B2 (en) 1998-01-07 2002-01-08 Ati Technologies Inc. Method and apparatus for line anti-aliasing
US6496187B1 (en) 1998-02-17 2002-12-17 Sun Microsystems, Inc. Graphics system configured to perform parallel sample to pixel calculation
US6473089B1 (en) 1998-03-02 2002-10-29 Ati Technologies, Inc. Method and apparatus for a video graphics circuit having parallel pixel processing
US6259460B1 (en) 1998-03-26 2001-07-10 Silicon Graphics, Inc. Method for efficient handling of texture cache misses by recirculation
US7038692B1 (en) 1998-04-07 2006-05-02 Nvidia Corporation Method and apparatus for providing a vertex cache
JP3497988B2 (en) * 1998-04-15 2004-02-16 株式会社ルネサステクノロジ Graphic processing apparatus and graphic processing method
US6092124A (en) 1998-04-17 2000-07-18 Nvidia Corporation Method and apparatus for accelerating the rendering of images
US6184908B1 (en) 1998-04-27 2001-02-06 Ati Technologies, Inc. Method and apparatus for co-processing video graphics data
US6212617B1 (en) 1998-05-13 2001-04-03 Microsoft Corporation Parallel processing method and system using a lazy parallel data type to reduce inter-processor communication
US6477687B1 (en) 1998-06-01 2002-11-05 Nvidia U.S. Investment Company Method of embedding RAMS and other macrocells in the core of an integrated circuit chip
US6646639B1 (en) 1998-07-22 2003-11-11 Nvidia Corporation Modified method and apparatus for improved occlusion culling in graphics systems
US6636215B1 (en) 1998-07-22 2003-10-21 Nvidia Corporation Hardware-assisted z-pyramid creation for host-based occlusion culling
US7023437B1 (en) 1998-07-22 2006-04-04 Nvidia Corporation System and method for accelerating graphics processing using a post-geometry data stream during multiple-pass rendering
US7068272B1 (en) 2000-05-31 2006-06-27 Nvidia Corporation System, method and article of manufacture for Z-value and stencil culling prior to rendering in a computer graphics processing pipeline
US6415345B1 (en) 1998-08-03 2002-07-02 Ati Technologies Bus mastering interface control system for transferring multistream data over a host bus
US6191800B1 (en) 1998-08-11 2001-02-20 International Business Machines Corporation Dynamic balancing of graphics workloads using a tiling strategy
AU5688199A (en) 1998-08-20 2000-03-14 Raycer, Inc. System, apparatus and method for spatially sorting image data in a three-dimensional graphics pipeline
US6492987B1 (en) 1998-08-27 2002-12-10 Ati Technologies, Inc. Method and apparatus for processing object elements that are being rendered
US6188412B1 (en) 1998-08-28 2001-02-13 Ati Technologies, Inc. Method and apparatus for performing setup operations in a video graphics system
US6591347B2 (en) * 1998-10-09 2003-07-08 National Semiconductor Corporation Dynamic replacement technique in a shared cache
US6292200B1 (en) 1998-10-23 2001-09-18 Silicon Graphics, Inc. Apparatus and method for utilizing multiple rendering pipes for a single 3-D display
US6731407B1 (en) 1998-11-02 2004-05-04 Seiko Epson Corporation Image processing method and device
US6323866B1 (en) * 1998-11-25 2001-11-27 Silicon Integrated Systems Corp. Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system
US6362825B1 (en) 1999-01-19 2002-03-26 Hewlett-Packard Company Real-time combination of adjacent identical primitive data sets in a graphics call sequence
US6477683B1 (en) 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6753878B1 (en) 1999-03-08 2004-06-22 Hewlett-Packard Development Company, L.P. Parallel pipelined merge engines
JP3169933B2 (en) 1999-03-16 2001-05-28 四国日本電気ソフトウェア株式会社 Parallel drawing device
US6535209B1 (en) 1999-03-17 2003-03-18 Nvidia Us Investments Co. Data stream splitting and storage in graphics data processing
US6288418B1 (en) 1999-03-19 2001-09-11 Nvidia Corporation Multiuse input/output connector arrangement for graphics accelerator integrated circuit
US6333744B1 (en) 1999-03-22 2001-12-25 Nvidia Corporation Graphics pipeline including combiner stages
US6181352B1 (en) 1999-03-22 2001-01-30 Nvidia Corporation Graphics pipeline selectively providing multiple pixels or multiple textures
US6577320B1 (en) 1999-03-22 2003-06-10 Nvidia Corporation Method and apparatus for processing multiple types of pixel component representations including processes of premultiplication, postmultiplication, and colorkeying/chromakeying
DE19917092A1 (en) 1999-04-15 2000-10-26 Sp3D Chip Design Gmbh Accelerated method for grid forming of graphic basic element in order beginning with graphic base element instruction data to produce pixel data for graphic base element
US6442656B1 (en) 1999-08-18 2002-08-27 Ati Technologies Srl Method and apparatus for interfacing memory with a bus
US6578068B1 (en) 1999-08-31 2003-06-10 Accenture Llp Load balancer in environment services patterns
US6352479B1 (en) 1999-08-31 2002-03-05 Nvidia U.S. Investment Company Interactive gaming server and online community forum
US6657635B1 (en) 1999-09-03 2003-12-02 Nvidia Corporation Binning flush in graphics data processing
US7002577B2 (en) 1999-12-06 2006-02-21 Nvidia Corporation Clipping system and method for a single graphics semiconductor platform
US6870540B1 (en) 1999-12-06 2005-03-22 Nvidia Corporation System, method and computer program product for a programmable pixel processing model with instruction set
US6844880B1 (en) 1999-12-06 2005-01-18 Nvidia Corporation System, method and computer program product for an improved programmable vertex processing model with instruction set
US6452595B1 (en) 1999-12-06 2002-09-17 Nvidia Corporation Integrated graphics processing unit with antialiasing
US6573900B1 (en) 1999-12-06 2003-06-03 Nvidia Corporation Method, apparatus and article of manufacture for a sequencer in a transform/lighting module capable of processing multiple independent execution threads
US6417851B1 (en) 1999-12-06 2002-07-09 Nvidia Corporation Method and apparatus for lighting module in a graphics processor
US6353439B1 (en) 1999-12-06 2002-03-05 Nvidia Corporation System, method and computer program product for a blending operation in a transform module of a computer graphics pipeline
US6198488B1 (en) 1999-12-06 2001-03-06 Nvidia Transform, lighting and rasterization system embodied on a single semiconductor platform
US6473086B1 (en) 1999-12-09 2002-10-29 Ati International Srl Method and apparatus for graphics processing using parallel graphics processors
US6557065B1 (en) 1999-12-20 2003-04-29 Intel Corporation CPU expandability bus
US6760031B1 (en) 1999-12-31 2004-07-06 Intel Corporation Upgrading an integrated graphics subsystem
US6864984B2 (en) 2000-03-16 2005-03-08 Fuji Photo Film Co., Ltd. Measuring method and apparatus using attenuation in total reflection
US6975319B1 (en) 2000-03-24 2005-12-13 Nvidia Corporation System, method and article of manufacture for calculating a level of detail (LOD) during computer graphics processing
US6831652B1 (en) 2000-03-24 2004-12-14 Ati International, Srl Method and system for storing graphics data
US20030132291A1 (en) 2002-01-11 2003-07-17 Metrologic Instruments, Inc. Point of sale (POS) station having bar code reading system with integrated internet-enabled customer-kiosk terminal
US6741243B2 (en) 2000-05-01 2004-05-25 Broadcom Corporation Method and system for reducing overflows in a computer graphics system
US6725457B1 (en) 2000-05-17 2004-04-20 Nvidia Corporation Semaphore enhancement to improve system performance
US6633296B1 (en) 2000-05-26 2003-10-14 Ati International Srl Apparatus for providing data to a plurality of graphics processors and method thereof
US6728820B1 (en) 2000-05-26 2004-04-27 Ati International Srl Method of configuring, controlling, and accessing a bridge and apparatus therefor
US6789154B1 (en) 2000-05-26 2004-09-07 Ati International, Srl Apparatus and method for transmitting data
US6670958B1 (en) 2000-05-26 2003-12-30 Ati International, Srl Method and apparatus for routing data to multiple graphics devices
US6662257B1 (en) 2000-05-26 2003-12-09 Ati International Srl Multiple device bridge apparatus and method thereof
US6690372B2 (en) 2000-05-31 2004-02-10 Nvidia Corporation System, method and article of manufacture for shadow mapping
US6724394B1 (en) 2000-05-31 2004-04-20 Nvidia Corporation Programmable pixel shading architecture
US6593923B1 (en) 2000-05-31 2003-07-15 Nvidia Corporation System, method and article of manufacture for shadow mapping
US6532013B1 (en) 2000-05-31 2003-03-11 Nvidia Corporation System, method and article of manufacture for pixel shaders for programmable shading
US6664963B1 (en) 2000-05-31 2003-12-16 Nvidia Corporation System, method and computer program product for programmable shading using pixel shaders
JP2002008060A (en) 2000-06-23 2002-01-11 Hitachi Ltd Data processing method, recording medium and data processing device
US6801202B2 (en) 2000-06-29 2004-10-05 Sun Microsystems, Inc. Graphics system configured to parallel-process graphics data using multiple pipelines
US7405734B2 (en) 2000-07-18 2008-07-29 Silicon Graphics, Inc. Method and system for presenting three-dimensional computer graphics images using multiple graphics processing units
US6959110B1 (en) 2000-08-17 2005-10-25 Nvidia Corporation Multi-mode texture compression algorithm
US7116331B1 (en) 2000-08-23 2006-10-03 Intel Corporation Memory controller hub interface
US6842180B1 (en) 2000-09-20 2005-01-11 Intel Corporation Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor
US6885378B1 (en) * 2000-09-28 2005-04-26 Intel Corporation Method and apparatus for the implementation of full-scene anti-aliasing supersampling
US6502173B1 (en) 2000-09-29 2002-12-31 Ati Technologies, Inc. System for accessing memory and method therefore
US6532525B1 (en) 2000-09-29 2003-03-11 Ati Technologies, Inc. Method and apparatus for accessing memory
US6828980B1 (en) 2000-10-02 2004-12-07 Nvidia Corporation System, method and computer program product for z-texture mapping
US6731298B1 (en) 2000-10-02 2004-05-04 Nvidia Corporation System, method and article of manufacture for z-texture mapping
JP3580789B2 (en) 2000-10-10 2004-10-27 株式会社ソニー・コンピュータエンタテインメント Data communication system and method, computer program, recording medium
US6961057B1 (en) 2000-10-12 2005-11-01 Nvidia Corporation Method and apparatus for managing and accessing depth data in a computer graphics system
US6362997B1 (en) 2000-10-16 2002-03-26 Nvidia Memory system for use on a circuit board in which the number of loads are minimized
US6636212B1 (en) 2000-11-14 2003-10-21 Nvidia Corporation Method and apparatus for determining visibility of groups of pixels
US6778181B1 (en) 2000-12-07 2004-08-17 Nvidia Corporation Graphics processing system having a virtual texturing array
US7027972B1 (en) 2001-01-24 2006-04-11 Ati Technologies, Inc. System for collecting and analyzing graphics data and method thereof
US7358974B2 (en) 2001-01-29 2008-04-15 Silicon Graphics, Inc. Method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video
US6888580B2 (en) 2001-02-27 2005-05-03 Ati Technologies Inc. Integrated single and dual television tuner having improved fine tuning
US7130316B2 (en) 2001-04-11 2006-10-31 Ati Technologies, Inc. System for frame based audio synchronization and method thereof
US6542971B1 (en) 2001-04-23 2003-04-01 Nvidia Corporation Memory access system and method employing an auxiliary buffer
US6664960B2 (en) 2001-05-10 2003-12-16 Ati Technologies Inc. Apparatus for processing non-planar video graphics primitives and associated method of operation
US6700583B2 (en) 2001-05-14 2004-03-02 Ati Technologies, Inc. Configurable buffer for multipass applications
WO2002101497A2 (en) 2001-06-08 2002-12-19 Nvidia Corporation System, method and computer program product for programmable fragment processing in a graphics pipeline
US6894687B1 (en) 2001-06-08 2005-05-17 Nvidia Corporation System, method and computer program product for vertex attribute aliasing in a graphics pipeline
US6697064B1 (en) 2001-06-08 2004-02-24 Nvidia Corporation System, method and computer program product for matrix tracking during vertex processing in a graphics pipeline
JP2003030641A (en) 2001-07-19 2003-01-31 Nec System Technologies Ltd Plotting device, parallel plotting method therefor and parallel plotting program
US6828987B2 (en) 2001-08-07 2004-12-07 Ati Technologies, Inc. Method and apparatus for processing video and graphics data
US6778189B1 (en) 2001-08-24 2004-08-17 Nvidia Corporation Two-sided stencil testing system and method
US6744433B1 (en) 2001-08-31 2004-06-01 Nvidia Corporation System and method for using and collecting information from a plurality of depth layers
US6704025B1 (en) 2001-08-31 2004-03-09 Nvidia Corporation System and method for dual-depth shadow-mapping
US6989840B1 (en) 2001-08-31 2006-01-24 Nvidia Corporation Order-independent transparency rendering system and method
US6947047B1 (en) 2001-09-20 2005-09-20 Nvidia Corporation Method and system for programmable pipelined graphics processing with branching instructions
US6938176B1 (en) 2001-10-05 2005-08-30 Nvidia Corporation Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle
US6999076B2 (en) 2001-10-29 2006-02-14 Ati Technologies, Inc. System, method, and apparatus for early culling
US7091971B2 (en) 2001-10-29 2006-08-15 Ati Technologies, Inc. System, method, and apparatus for multi-level hierarchical Z buffering
US6677953B1 (en) 2001-11-08 2004-01-13 Nvidia Corporation Hardware viewport system and method for use in a graphics pipeline
US20030117971A1 (en) 2001-12-21 2003-06-26 Celoxica Ltd. System, method, and article of manufacture for profiling an executable hardware model using calls to profiling functions
US6683614B2 (en) 2001-12-21 2004-01-27 Hewlett-Packard Development Company, L.P. System and method for automatically configuring graphics pipelines by tracking a region of interest in a computer graphical display system
US7012610B2 (en) 2002-01-04 2006-03-14 Ati Technologies, Inc. Portable device for providing dual display and method thereof
US6774895B1 (en) 2002-02-01 2004-08-10 Nvidia Corporation System and method for depth clamping in a hardware graphics pipeline
US6829689B1 (en) 2002-02-12 2004-12-07 Nvidia Corporation Method and system for memory access arbitration for minimizing read/write turnaround penalties
US6947865B1 (en) 2002-02-15 2005-09-20 Nvidia Corporation Method and system for dynamic power supply voltage adjustment for a semiconductor integrated circuit device
JP4079410B2 (en) 2002-02-15 2008-04-23 株式会社バンダイナムコゲームス Image generation system, program, and information storage medium
US6933943B2 (en) 2002-02-27 2005-08-23 Hewlett-Packard Development Company, L.P. Distributed resource architecture and system
US6700580B2 (en) 2002-03-01 2004-03-02 Hewlett-Packard Development Company, L.P. System and method utilizing multiple pipelines to render graphical data
US6853380B2 (en) 2002-03-04 2005-02-08 Hewlett-Packard Development Company, L.P. Graphical display system and method
US20030171907A1 (en) 2002-03-06 2003-09-11 Shay Gal-On Methods and Apparatus for Optimizing Applications on Configurable Processors
US6919896B2 (en) * 2002-03-11 2005-07-19 Sony Computer Entertainment Inc. System and method of optimizing graphics processing
US7009605B2 (en) 2002-03-20 2006-03-07 Nvidia Corporation System, method and computer program product for generating a shader program
JP4193990B2 (en) * 2002-03-22 2008-12-10 ディーリング，マイケル，エフ． Scalable high-performance 3D graphics
US20030212735A1 (en) 2002-05-13 2003-11-13 Nvidia Corporation Method and apparatus for providing an integrated network of processors
US20040153778A1 (en) 2002-06-12 2004-08-05 Ati Technologies, Inc. Method, system and software for configuring a graphics processing communication mode
US6980209B1 (en) 2002-06-14 2005-12-27 Nvidia Corporation Method and system for scalable, dataflow-based, programmable processing of graphics data
US6812927B1 (en) 2002-06-18 2004-11-02 Nvidia Corporation System and method for avoiding depth clears using a stencil buffer
US6876362B1 (en) 2002-07-10 2005-04-05 Nvidia Corporation Omnidirectional shadow texture mapping
US6797998B2 (en) 2002-07-16 2004-09-28 Nvidia Corporation Multi-configuration GPU interface device
US6825843B2 (en) 2002-07-18 2004-11-30 Nvidia Corporation Method and apparatus for loop and branch instructions in a programmable graphics pipeline
US6954204B2 (en) 2002-07-18 2005-10-11 Nvidia Corporation Programmable graphics system and method using flexible, high-precision data formats
US6864893B2 (en) 2002-07-19 2005-03-08 Nvidia Corporation Method and apparatus for modifying depth values using pixel programs
US6952206B1 (en) 2002-08-12 2005-10-04 Nvidia Corporation Graphics application program interface system and method for accelerating graphics processing
US7112884B2 (en) 2002-08-23 2006-09-26 Ati Technologies, Inc. Integrated circuit having memory disposed thereon and method of making thereof
US6779069B1 (en) 2002-09-04 2004-08-17 Nvidia Corporation Computer system with source-synchronous digital link
JP4467267B2 (en) 2002-09-06 2010-05-26 株式会社ソニー・コンピュータエンタテインメント Image processing method, image processing apparatus, and image processing system
US7061495B1 (en) * 2002-11-18 2006-06-13 Ati Technologies, Inc. Method and apparatus for rasterizer interpolation
US7633506B1 (en) * 2002-11-27 2009-12-15 Ati Technologies Ulc Parallel pipeline graphics system
US7324547B1 (en) 2002-12-13 2008-01-29 Nvidia Corporation Internet protocol (IP) router residing in a processor chipset
US6885376B2 (en) 2002-12-30 2005-04-26 Silicon Graphics, Inc. System, method, and computer program product for near-real time load balancing across multiple rendering pipelines
EP1590769A4 (en) 2003-01-28 2007-04-04 Lucid Information Technology Ltd Method and system for compositing three-dimensional graphics images using associative decision mechanism
US7145565B2 (en) 2003-02-27 2006-12-05 Nvidia Corporation Depth bounds testing
US6911983B2 (en) 2003-03-12 2005-06-28 Nvidia Corporation Double-buffering of pixel data using copy-on-write semantics
US7129909B1 (en) 2003-04-09 2006-10-31 Nvidia Corporation Method and system using compressed display mode list
US6900810B1 (en) 2003-04-10 2005-05-31 Nvidia Corporation User programmable geometry engine
US6940515B1 (en) 2003-04-10 2005-09-06 Nvidia Corporation User programmable primitive engine
US7120816B2 (en) 2003-04-17 2006-10-10 Nvidia Corporation Method for testing synchronization and connection status of a graphics processing unit module
US7483031B2 (en) 2003-04-17 2009-01-27 Nvidia Corporation Method for synchronizing graphics processing units
US7068278B1 (en) 2003-04-17 2006-06-27 Nvidia Corporation Synchronized graphics processing units
US7038678B2 (en) 2003-05-21 2006-05-02 Nvidia Corporation Dependent texture shadow antialiasing
US7415708B2 (en) 2003-06-26 2008-08-19 Intel Corporation Virtual machine management using processor state information
US7038685B1 (en) 2003-06-30 2006-05-02 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
US7119808B2 (en) 2003-07-15 2006-10-10 Alienware Labs Corp. Multiple parallel processor computer graphics system
US6995767B1 (en) 2003-07-31 2006-02-07 Nvidia Corporation Trilinear optimization for texture filtering
WO2005015504A1 (en) * 2003-08-07 2005-02-17 Renesas Technology Corp. Image processing semiconductor processor
US7525547B1 (en) 2003-08-12 2009-04-28 Nvidia Corporation Programming multiple chips from a command buffer to process multiple images
US7015915B1 (en) 2003-08-12 2006-03-21 Nvidia Corporation Programming multiple chips from a command buffer
US6956579B1 (en) 2003-08-18 2005-10-18 Nvidia Corporation Private addressing in a multi-processor graphics processing system
US7075541B2 (en) 2003-08-18 2006-07-11 Nvidia Corporation Adaptive load balancing in a multi-processor graphics processing system
US7388581B1 (en) 2003-08-28 2008-06-17 Nvidia Corporation Asynchronous conditional graphics rendering
US8250412B2 (en) 2003-09-26 2012-08-21 Ati Technologies Ulc Method and apparatus for monitoring and resetting a co-processor
US20050086040A1 (en) * 2003-10-02 2005-04-21 Curtis Davis System incorporating physics processing unit
US7782325B2 (en) * 2003-10-22 2010-08-24 Alienware Labs Corporation Motherboard for supporting multiple graphics cards
US8035646B2 (en) 2003-11-14 2011-10-11 Microsoft Corporation Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
US7221896B2 (en) * 2003-12-09 2007-05-22 Sharp Kabushiki Kaisha Fixing device for fixing an unfixed developing agent on a recording medium and image forming apparatus including the same
US7015914B1 (en) 2003-12-10 2006-03-21 Nvidia Corporation Multiple data buffers for processing graphics data
US7053901B2 (en) 2003-12-11 2006-05-30 Nvidia Corporation System and method for accelerating a special purpose processor
US7248261B1 (en) 2003-12-15 2007-07-24 Nvidia Corporation Method and apparatus to accelerate rendering of shadow effects for computer-generated images
JP3879002B2 (en) 2003-12-26 2007-02-07 国立大学法人宇都宮大学 Self-optimizing arithmetic unit
US6975325B2 (en) 2004-01-23 2005-12-13 Ati Technologies Inc. Method and apparatus for graphics processing using state and shader management
US7259606B2 (en) 2004-01-27 2007-08-21 Nvidia Corporation Data sampling clock edge placement training for high speed GPU-memory interface
US7483034B2 (en) 2004-02-25 2009-01-27 Siemens Medical Solutions Usa, Inc. System and method for GPU-based 3D nonrigid registration
US7289125B2 (en) 2004-02-27 2007-10-30 Nvidia Corporation Graphics device clustering with PCI-express
US7027062B2 (en) 2004-02-27 2006-04-11 Nvidia Corporation Register based queuing for texture requests
US7978194B2 (en) 2004-03-02 2011-07-12 Ati Technologies Ulc Method and apparatus for hierarchical Z buffering and stenciling
US20050195186A1 (en) 2004-03-02 2005-09-08 Ati Technologies Inc. Method and apparatus for object based visibility culling
US20050275760A1 (en) 2004-03-02 2005-12-15 Nvidia Corporation Modifying a rasterized surface, such as by trimming
US7315912B2 (en) 2004-04-01 2008-01-01 Nvidia Corporation Deadlock avoidance in a bus fabric
US7336284B2 (en) 2004-04-08 2008-02-26 Ati Technologies Inc. Two level cache memory architecture
US7265759B2 (en) 2004-04-09 2007-09-04 Nvidia Corporation Field changeable rendering system for a computing device
US6985152B2 (en) 2004-04-23 2006-01-10 Nvidia Corporation Point-to-point bus bridging without a bridge controller
US20050237329A1 (en) 2004-04-27 2005-10-27 Nvidia Corporation GPU rendering to system memory
US7738045B2 (en) 2004-05-03 2010-06-15 Broadcom Corporation Film-mode (3:2/2:2 Pulldown) detector, method and video device
US7079156B1 (en) 2004-05-14 2006-07-18 Nvidia Corporation Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline
US7426724B2 (en) 2004-07-02 2008-09-16 Nvidia Corporation Optimized chaining of vertex and fragment programs
US7218291B2 (en) 2004-09-13 2007-05-15 Nvidia Corporation Increased scalability in the fragment shading pipeline
CN101091175B (en) 2004-09-16 2012-03-14 辉达公司 Load balancing
US7571296B2 (en) 2004-11-11 2009-08-04 Nvidia Corporation Memory controller-adaptive 1T/2T timing control
US7477256B1 (en) 2004-11-17 2009-01-13 Nvidia Corporation Connecting graphics adapters for scalable performance
US8066515B2 (en) 2004-11-17 2011-11-29 Nvidia Corporation Multiple graphics adapter connection systems
US7598958B1 (en) 2004-11-17 2009-10-06 Nvidia Corporation Multi-chip graphics processing unit apparatus, system, and method
US7633505B1 (en) * 2004-11-17 2009-12-15 Nvidia Corporation Apparatus, system, and method for joint processing in graphics processing units
US7275123B2 (en) 2004-12-06 2007-09-25 Nvidia Corporation Method and apparatus for providing peer-to-peer data transfer within a computing environment
US7451259B2 (en) 2004-12-06 2008-11-11 Nvidia Corporation Method and apparatus for providing peer-to-peer data transfer within a computing environment
US7372465B1 (en) 2004-12-17 2008-05-13 Nvidia Corporation Scalable graphics processing for remote display
US20060156399A1 (en) 2004-12-30 2006-07-13 Parmar Pankaj N System and method for implementing network security using a sequestered partition
US7924281B2 (en) 2005-03-09 2011-04-12 Ati Technologies Ulc System and method for determining illumination of a pixel by shadow planes
US7796095B2 (en) 2005-03-18 2010-09-14 Ati Technologies Ulc Display specific image processing in an integrated circuit
US7568056B2 (en) 2005-03-28 2009-07-28 Nvidia Corporation Host bus adapter that interfaces with host computer bus to multiple types of storage devices
US7681187B2 (en) 2005-03-31 2010-03-16 Nvidia Corporation Method and apparatus for register allocation in presence of hardware constraints
US7817155B2 (en) 2005-05-24 2010-10-19 Ati Technologies Inc. Master/slave graphics adapter arrangement
US20080143731A1 (en) 2005-05-24 2008-06-19 Jeffrey Cheng Video rendering across a high speed peripheral interconnect bus
US7539801B2 (en) 2005-05-27 2009-05-26 Ati Technologies Ulc Computing device with flexibly configurable expansion slots, and method of operation
US20060282604A1 (en) 2005-05-27 2006-12-14 Ati Technologies, Inc. Methods and apparatus for processing graphics data using multiple processing circuits
US7516301B1 (en) * 2005-12-16 2009-04-07 Nvidia Corporation Multiprocessor computing systems with heterogeneous processors
US7325086B2 (en) 2005-12-15 2008-01-29 Via Technologies, Inc. Method and system for multiple GPU support
US7728841B1 (en) 2005-12-19 2010-06-01 Nvidia Corporation Coherent shader output for multiple targets
US7768517B2 (en) 2006-02-21 2010-08-03 Nvidia Corporation Asymmetric multi-GPU processing
US8284204B2 (en) 2006-06-30 2012-10-09 Nokia Corporation Apparatus, method and a computer program product for providing a unified graphics pipeline for stereoscopic rendering
US7941791B2 (en) 2007-04-13 2011-05-10 Perry Wang Programming environment for heterogeneous processor resource integration

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US11341602B2 (en) 2022-05-24
US7834880B2 (en) 2010-11-16
US7812845B2 (en) 2010-10-12
US20200184594A1 (en) 2020-06-11
US10147157B2 (en) 2018-12-04
US7843457B2 (en) 2010-11-30
US20080129744A1 (en) 2008-06-05
US20140292775A1 (en) 2014-10-02
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US7812844B2 (en) 2010-10-12
US8754897B2 (en) 2014-06-17

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