WO2006118632A1 - Aluminum free group iii-nitride based high electron mobility transistors and methods of fabricating same - Google Patents

Aluminum free group iii-nitride based high electron mobility transistors and methods of fabricating same Download PDF

Info

Publication number
WO2006118632A1
WO2006118632A1 PCT/US2006/006146 US2006006146W WO2006118632A1 WO 2006118632 A1 WO2006118632 A1 WO 2006118632A1 US 2006006146 W US2006006146 W US 2006006146W WO 2006118632 A1 WO2006118632 A1 WO 2006118632A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
doped
hemt
gan
nitride
Prior art date
Application number
PCT/US2006/006146
Other languages
French (fr)
Inventor
Adam William Saxler
Original Assignee
Cree, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree, Inc. filed Critical Cree, Inc.
Priority to EP06735699A priority Critical patent/EP1875514A1/en
Priority to JP2008508832A priority patent/JP2008539586A/en
Publication of WO2006118632A1 publication Critical patent/WO2006118632A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • the present invention relates to semiconductor devices and, more particularly, to transistors that incorporate nitride-based active layers.
  • Si silicon
  • GaAs gallium arsenide
  • HEMT High Electron Mobility Transistor
  • MODFET modulation doped field effect transistor
  • a two-dimensional electron gas (2DEG) is formed at the heterojunction of two semiconductor materials with different bandgap energies, and where the smaller bandgap material has a higher electron affinity.
  • the 2DEG is an accumulation layer in the undoped ("unintentionally doped"), smaller bandgap material and can contain a very high sheet electron concentration in excess of, for example, 10 13 carriers/cm 2 . Additionally, electrons that originate in the wider-bandgap semiconductor transfer to the 2DEG, allowing a high electron mobility due to reduced ionized impurity scattering.
  • This combination of high carrier concentration and high carrier mobility can give the HEMT a very large transconductance and may provide a strong performance advantage over metal-semiconductor field effect transistors (MESFETs) for high- frequency applications.
  • MESFETs metal-semiconductor field effect transistors
  • High electron mobility transistors fabricated in the gallium nitride/aluminum gallium nitride (GaN/ AlGaN) material system have the potential to generate large amounts of RF power because of the combination of material characteristics that includes the aforementioned high breakdown fields, their wide bandgaps, large conduction band offset, and/or high saturated electron drift velocity.
  • a major portion of the electrons in the 2DEG is attributed to polarization in the AlGaN.
  • HEMTs in the GaN/AlGaN system have already been demonstrated.
  • U.S. Patents 5,192,987 and 5,296,395 describe AlGaN/GaN HEMT structures and methods of manufacture.
  • Conventional HEMTs typically have an AlGaN layer on a GaN channel layer.
  • the presence of aluminum in the active region of the device may reduce the reliability of the device as a result of oxidation effects, dislocation related pits and/or the presence of DX centers.
  • Some embodiments of the present invention provide high electron mobility transistors (HEMTs) and methods of fabricating HEMTs that include an aluminum free Group Ill-nitride barrier layer, an aluminum free Group Ill-nitride channel layer on the barrier layer and an aluminum free Group Ill-nitride cap layer on the channel layer.
  • the barrier layer comprises a doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
  • An undoped Group Ill-nitride layer may also be provided disposed between the doped Group Ill-nitride region and the channel layer.
  • the cap layer comprises a first doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
  • An undoped Group Ill-nitride layer may be disposed between the first doped Group Ill-nitride region and the channel layer.
  • the barrier layer comprises a GaN layer
  • the channel layer comprises an InGaN layer
  • the cap layer comprises a GaN layer.
  • the barrier layer may have a thickness of from about 0.1 ⁇ m to about 1000 ⁇ m
  • the channel layer may have a thickness of from about 1 nm to about 20 nm
  • the cap layer may have a thickness of from about 5 nm to about 100 nm.
  • the InGaN layer may have a percentage of indium of from about 1 to about 100 percent.
  • a first doped GaN layer is disposed between the GaN barrier layer and the InGaN channel layer.
  • the first doped GaN layer may comprise a Si, Sn, O and/or Ge doped GaN layer.
  • the first doped GaN layer may have a thickness of from about 0.2 nm to about 10 nm.
  • the first doped GaN layer may have a dopant concentration of from about 1 x 10 cm " to about 1 x 10 21 cm "3 .
  • a first undoped GaN layer may be disposed between the first doped GaN layer and the InGaN channel layer.
  • the first undoped GaN layer may have a thickness of from about 0.3 nm to about 5 nm.
  • a first doped GaN layer is disposed between the GaN cap layer and the InGaN channel layer.
  • the first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer may comprise a Si, Sn, O and/or Ge doped GaN layer.
  • the first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer may have a thickness of from about 0.2 nm to about 10 nm.
  • the first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer may have a dopant concentration of from about 1 x 10 16 cm "3 to about 1 x 10 21 cm "3 .
  • a first undoped GaN layer may be disposed between the first doped GaN layer and the InGaN channel layer.
  • the first undoped GaN layer disposed between the first doped GaN layer and the InGaN layer may have a thickness of from about 0.3 nm to about 5 nm.
  • a second doped GaN layer may be disposed between the GaN barrier layer and the InGaN channel layer.
  • the second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer may comprise a Si, Sn, O and/or Ge doped GaN layer.
  • the second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer may have a thickness of from about 0.2 nm to about 10 irai.
  • the second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer may have a dopant concentration of from about 1 x 10 16 cm “3 to about 1 x 10 21 cm "3 .
  • a second undoped GaN layer may be disposed between the second doped GaN layer and the InGaN channel layer.
  • the second undoped GaN layer may have a thickness of from about 0.3 nm to about 5 nm.
  • an InGaN layer is provided on the GaN cap layer opposite the InGaN channel layer.
  • the InGaN layer on the GaN cap layer opposite the InGaN channel layer may have a thickness of from about 0.3 nm to about 100 nm.
  • a metal semiconductor field effect transistor (MESFET) is provided.
  • Figure 1 is a cross-section of an aluminum free Group Ill-nitride based HEMT according to some embodiments of the present invention.
  • Figure 2 is a cross-section of an aluminum free GaN based HEMT according to some embodiments of the present invention.
  • Figures 3 A through 3D are cross-sections of aluminum free GaN based HEMTs according to further embodiments of the present invention.
  • Figures 4A through 4N are graphs of carrier concentration and band diagrams from simulation models of transistors according to some embodiments of the present invention.
  • first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
  • relative terms such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure.
  • Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have tapered, rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
  • references to a structure or feature that is disposed "adjacent" another feature may have portions that overlap or underlie the adjacent feature.
  • Embodiments of the present invention provide aluminum free nitride-based HEMTs such as Group Ill-nitride based devices.
  • Group III nitride refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, gallium (Ga), and/or indium (In).
  • the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., InGaN), and quaternary compounds. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as In x Ga 1-x N where 0 ⁇ x ⁇ 1 are often used to describe them.
  • aluminum free refers to the absence of Al intentionally incorporated into active layers of the Group Ill-nitride based device.
  • a region or layer with less than about 1% Al may be considered aluminum free.
  • an active layer of a device may be Al free even if some Al is present in the active layer, for example, through unintentional incorporation by contamination during fabrication.
  • Active layers of a device are the layers of the device where the 2DEG is formed and layers disposed between the layers where the 2DEG is formed and the source, drain and/or gate contacts and/or contact layers (i.e. layers on which a contact is directly formed) of the device. Aluminum is not, however, intentionally incorporated in the layers that form the 2DEG.
  • Al may be present in layers between the layers that form the 2DEG and a substrate, in contacts and/or in the substrate.
  • Al may be in the substrate, nucleation and/or buffer layers and/or the ohmic contacts.
  • Figure 1 illustrates a HEMT structure according to some embodiments of the present invention.
  • a substrate 10 is provided on which Group Ill-nitride based devices may be formed.
  • the substrate 10 may be a silicon carbide (SiC) substrate that may be, for example, 4H polytype of silicon carbide.
  • Other silicon carbide candidate polytypes include the 3C, 6H, and 15R polytypes.
  • the substrate 10 may be semi-insulating.
  • the term "semi-insulating" is used descriptively rather than in an absolute sense.
  • the silicon carbide bulk crystal has a resistivity equal to or higher than about 1x10 5 ⁇ -cm at room temperature.
  • the substrate 10 may be conductive.
  • Optional buffer, nucleation and/or transition layers may be provided on the substrate 10.
  • an AlN buffer layer may be provided to provide an appropriate crystal structure transition between the silicon carbide substrate and the remainder of the device.
  • strain balancing transition layer(s) may also be provided as described, for example, in commonly assigned U.S. Patent Publication No. 2003/0102482A1, filed July 19, 2002 and published June 5, 2003, and entitled "STRAIN BALANCED NITRIDE HETROJUNCTION TRANSISTORS AND METHODS OF FABRICATING STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTORS," and/or United States Patent No.
  • SiC substrates are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention, and methods for producing are described, for example, in U. S. Patent Nos. Re. 34,861 ; 4,946,547; 5,200,022; and 6,218,680, the contents of which are incorporated herein by reference in their entirety.
  • techniques for epitaxial growth of Group III nitrides have been described in, for example, U. S. Patent Nos. 5,210,051; 5,393,993; 5,523,589; and 5,592,501, the contents of which are also incorporated herein by reference in their entirety.
  • silicon carbide may be used as a substrate material
  • embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like.
  • an appropriate buffer layer also may be formed.
  • some embodiments of the present invention may utilize thick semi-insulating or insulating Group Ill-nitride layers and/or conducting substrates or layers as described in United States Patent Application Serial No.
  • an aluminum free Group III nitride barrier layer 12 is provided on the substrate 10.
  • An aluminum free Group Ill-nitride channel layer 14 is provided on the barrier layer 12 and an aluminum free Group Ill-nitride cap layer 16 is provided on the channel layer 14.
  • the barrier layer 12 may be deposited on the substrate 10 using buffer layers, transition layers, and/or nucleation layers as described above.
  • the barrier layer 12 may be semi-insulating or insulating and/or may be unintentionally doped.
  • the barrier layer 12 and/or the cap layer 16 may include doped regions adjacent the channel layer 14. Furthermore, the barrier layer 12, channel layer 14, cap layer 16 and/or buffer nucleation and/or transition layers may be deposited by MOCVD or by other techniques known to those of skill in the art, such as MBE or HVPE .
  • the barrier layer 12 may be undoped or unintentionally doped.
  • the barrier layer 12 may include a thick semi-insulating or insulating layer with an undoped or unintentionally doped region adjacent the channel layer 14.
  • the barrier layer 12 should be thick enough to prevent migration of Al in layers disposed opposite the channel layer 14 to the channel layer 14. Thus, portions of the barrier layer 12 may unintentionally include Al while still being an aluminum free Group Ill-nitride layer.
  • the barrier layer 12 may be from about 1 nm to about 1 x 10 6 nm thick and may have less than about 1% aluminum, hi some embodiments of the present invention, the barrier layer 12 is about 1000 A thick.
  • barrier layer 12 may be doped with Fe or other elements to make it more insulating or provide a larger barrier as described in the above referenced patent applications.
  • the barrier layer 12 may be provided as part or all of the substrate 10 or as a separate layer on the substrate 10.
  • the channel layer 14 is a Group Ill-nitride, such as In x Ga 1-x N, where 0 ⁇ x ⁇ l provided that the energy of the conduction band edge of the channel layer 14 is less than the energy of the conduction band edge of the cap layer 16 at the interface between the channel and cap layers.
  • the channel layer 14 may have a bandgap that is less than the bandgap of the cap layer 16 and the channel layer 14 may also have a larger electron affinity than the cap layer 16.
  • the channel layer 14 may be undoped or unintentionally doped and may be grown to a thickness of greater than about 10 A.
  • the channel layer 14 may have a thickness of from about 10 A to about 200 A.
  • the channel layer 14 may also be a multi-layer structure, such as a superlattice or combinations of GaN, InGaN or the like.
  • the channel layer 14 has less than about 1% aluminum.
  • the cap layer 16 is thick enough and/or has a high enough doping to induce a significant carrier concentration at the interface between the channel layer 14 and the cap layer 16 through polarization effects.
  • the cap layer 16 may be a Group Ill-nitride and has a bandgap larger than that of the channel layer 14 and a smaller electron affinity than the channel layer 14.
  • the cap layer 16 may be GaN or InGaN. If the cap layer 16 is InGaN the cap layer 16 should have a lower indium percentage than is present in the channel layer 14.
  • the cap layer 16 may, for example, be from about 5 nm to about 100 nm thick, but is not so thick as to cause cracking or substantial defect formation therein.
  • the cap layer 16 may be thicker if the gate contact 24 is recessed into the cap layer 16.
  • the cap layer 16 is undoped and/or doped with an n-type dopant to a concentration of 1 x 10 16 cm "3 about 1 x 10 cm " .
  • the cap layer 16 has less than about 1% aluminum.
  • Source and drain ohmic contacts 20 and 22 are provided on the cap layer 16 and a gate contact 24 is disposed between the source and drain contacts 20 and 22.
  • Suitable ohmic contact materials may include, for example, Ti, Al, Ni and/orAu.
  • Suitable gate materials may depend on the composition of the cap layer, however, in certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSi x , Cu, Pd, Cr, W and/or WSiN.
  • FIG. 2 is a schematic diagram of HEMTs according to further embodiments of the present invention.
  • a GaN barrier layer 112 is provided on a substrate 110.
  • the substrate 110 may be a substrate as described above with reference to the substrate 10.
  • optional buffer, nucleation and/or transition layers (not shown) may be provided on the substrate 110 as described above. These optional buffer, nucleation and/or transition layers may include aluminum.
  • the substrate 110 is a GaN substrate.
  • an InGaN channel layer 114 is provided on the GaN barrier layer 112.
  • a GaN cap layer 116 is provided on the InGaN channel layer 114.
  • the GaN barrier layer 112 is a thick GaN layer and may be undoped, unintentionally doped and/or semi- insulating or insulating.
  • the GaN barrier layer 112 may be semi- insulating or insulating in a region proximate the substrate 110 and may be undoped or unintentionally doped in a region proximate the InGaN channel layer 114.
  • the GaN barrier layer 112 should be sufficiently thick to prevent migration of Al in layers disposed opposite the channel layer 114 to the channel layer 114. Thus, portions of the barrier layer 112 may unintentionally include Al while still being an aluminum free layer.
  • the barrier layer 112 may be from about 10 nm to about 1 x 10 6 nm thick. In particular embodiments of the present invention, the barrier layer 112 is at least about 1000 A thick. In some embodiments of the present invention, the barrier layer 112 has less than about 1% aluminum.
  • the InGaN channel layer 114 may be In x G 1-x aN, where 0 ⁇ x ⁇ 1 provided that the energy of the conduction band edge of the channel layer 114 is less than the energy of the conduction band edge of the cap layer 116 at the interface between the channel and cap layers.
  • the channel layer 114 may have a bandgap that is less than the bandgap of the cap layer 116 and the channel layer 114 may also have a larger electron affinity than the cap layer 116.
  • the channel layer 114 may be undoped or unintentionally doped and may be grown to a thickness of greater than about 10 A.
  • the channel layer 114 may have a thickness of from about 10 A to about 200 A.
  • the maximum thickness of the channel layer 114 may depend on the percentage of indium in the channel layer 114. The lower the percentage of indium in the channel layer 114, the thicker the channel layer 114 may be before an undesirable two dimensional hole gas is formed for Ga polar devices. A low or high indium percentage may be desirable to reduce or minimize impurity scattering. In particular embodiments of the present invention, the indium percentage is the channel layer 114 is about 30% or less. In some embodiments, the indium percentage is the channel layer 114 is about 20%. In some embodiments of the present invention, the channel layer 114 has less than about 1% aluminum.
  • the GaN cap layer 116 is thick enough and/or has a high enough doping to induce a significant carrier concentration at the interface between the channel layer 114 and the cap layer 116.
  • the GaN cap layer 116 is from about 1 nm to about 100 nm thick, but is not so thick as to cause cracking or substantial defect formation therein.
  • the cap layer 116 has less than about 1% aluminum. As discussed above, with reference to the cap layer 16, the cap layer 116 may be thicker if the gate contact 24 is recessed into the cap layer 116.
  • an InGaN layer (not shown) may be provided on the GaN cap layer 116.
  • the InGaN layer may increase the barrier to the surface from the channel. If an InGaN layer is provided on the GaN cap layer 116, the InGaN layer may have an indium composition of from about 1% to 100% and may have a thickness of from about 1 ran to about 100 nm.
  • FIGS 3 A through 3D are schematic illustrations of further embodiments of HEMTs according the present invention having doped and/or spacer layers adjacent an InGaN channel layer 214.
  • a GaN barrier layer 212 is provided on a substrate 210.
  • An InGaN channel layer 214 is provided on the GaN barrier layer 212 and a GaN cap layer 216 is provided on the InGaN channel layer 214.
  • the substrate 210, GaN barrier layer 212, InGaN channel layer 214 and GaN cap layer 216 may be provided as described above with reference to the substrate 110, GaN barrier layer 112, InGaN channel layer 114 and GaN cap layer 116 of Figure 2.
  • the optional buffer, nucleation and/or transition layers described above may also be provided.
  • An optional InGaN layer (not shown) may also be provided on the cap layer 216 as described above.
  • Figure 3 A illustrates embodiments of the present invention where a doped GaN layer 230 is disposed between the GaN barrier layer 212 and the InGaN channel layer 214.
  • the doped GaN layer 230 may be doped with Si, Ge, Sn and/or O and may have a dopant concentration of from about 1 x 10 16 cm “3 to about 1 x 10 21 cm "3 , hi particular embodiments, the dopant concentration may be about 1 x 10 20 cm "3 .
  • the doped GaN layer 230 may be from about 0.2 nm to about 10 nm thick.
  • the doping concentration should be high enough and the layer thick enough to supply sufficient electrons to the 2DEG channel, but not so high or thick as to have additional, unintentional n-type regions outside of the channel region.
  • the dopant may be Sn and/or Ge. hi other embodiments, the dopant may be Si.
  • the doped GaN layer 230 may be provided as a delta doped region. In particular embodiments of the present invention, the doped layer 230 provides a sheet density of from about 1 x 10 12 cm "2 to about 1 x 10 14 cm "2 at the interface with the channel layer 214.
  • the doped layer 230 may be provided by an InGaN layer.
  • the doped layer 230 may be provided by a doped region of the InGaN channel layer 214.
  • the InGaN channel layer 214 should be thick enough and the doped portion thin enough and doped lightly enough so that electrons from the doping are supplied to the 2DEG and do not form an n-type region in the doped region.
  • Figure 3B illustrates embodiments of the present invention where a doped GaN layer 230 is disposed between the GaN barrier layer 212 and the InGaN channel layer 214 and an undoped GaN layer 240 is disposed between the doped GaN layer 230 and the InGaN channel layer 214.
  • the undoped GaN layer 240 may be from about 0.5 run to about 5 nm thick.
  • the undoped GaN layer 240 may space the doped layer 230 from the channel layer 214 to reduce and/or minimize impurity scattering.
  • Figure 3 C illustrates embodiments of the present invention where a doped GaN layer 250 is disposed between the GaN cap layer 216 and the InGaN channel layer 214.
  • the doped GaN layer 250 may be doped with Si, Sn, Ge and/or O and may have a dopant concentration of from about 1 x 10 16 cm “3 to about 1 x 10 21 cm "3 .
  • the doped GaN layer 250 may be from about 0.2 nm to about 100 nm thick.
  • the structure of Figure 3C could be used as a MESFET with the InGaN channel layer 214 acting more as a back barrier than a channel if the GaN layer 250 is doped heavily enough. Mobility may be better in the doped GaN layer 250 than in the InGaN channel layer 214 depending on the doping density and the indium percentage.
  • Figure 3D illustrates embodiments of the present invention where a doped GaN layer 250 is disposed between the GaN cap layer 216 and the InGaN channel layer 214 and an undoped GaN layer 260 is disposed between the doped GaN layer 250 and the InGaN channel layer 214.
  • the undoped GaN layer 260 may be from about 0.3 nm to about 10 nm thick.
  • the undoped GaN layer 260 may space the doped layer 250 from the channel layer 214 to reduce and/or minimize impurity scattering.
  • FIG. 3 A through 3D While embodiments of the present invention are illustrated in Figures 3 A through 3D as including doped and/or undoped layers on one side or the other of the InGaN channel layer 214, combinations and subcombinations of the structures illustrated in Figures 3A through 3D may also be provided.
  • a structure with a doped layer between the cap layer 216 and the channel layer 214 may also have a doped layer between the barrier layer 212 and the channel layer 214.
  • a passivation layer may also be provided on the structures of Figures 1 through 3D.
  • the passivation layer may be silicon nitride, aluminum nitride, silicon dioxide, an ONO structure and/or an oxynitride.
  • the passivation layer may be a single or multiple layers of uniform and/or non-uniform composition.
  • Figures 4 A through 4N are graphs of carrier concentration and band diagrams from simulation models of transistors according to some embodiments of the present invention, hi the simulations depicted in Figures 4 A through 4N 5 the aluminum free layers are modeled as having 0% aluminum. These simulations are not meant to be exact but are provided to illustrate possible trends and to estimate properties of different designs. Accordingly, these graphs are provided as a rough estimate of possible characteristics of the simulated device structures but are only as accurate as the underlying assumptions and models. Accordingly, the properties of actual devices may differ from those illustrated in Figures 4A through 4N.
  • Figure 4A illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick InGaN channel layer with 30% indium and a 10 nm thick undoped GaN cap layer.
  • Figure 4B illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick InGaN channel layer with 30% indium and a 20 nm thick undoped GaN cap layer.
  • Figure 4C illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 1 nm thick doped GaN layer with a dopant concentration of 18 X 10 19 cm “3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 6 nm thick InGaN channel layer with 30% indium and a 60 nm thick undoped GaN cap layer.
  • the configuration of Figure 4C is predicted to have a higher peak electron concentration than either of the configurations of Figures 4A and 4B.
  • Figure 4D illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 1 nm thick doped GaN layer with a dopant concentration of 20 X 10 19 cm “3 between the barrier layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer.
  • the configuration of Figure 4D is predicted to have a higher peak electron concentration than either of the configurations of Figures 4 A and 4B but may have a lower peak electron concentration than provided by the configuration of Figure 4C.
  • Figure 4E illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 1 nm thick doped GaN layer with a dopant concentration of 10 X 10 19 cm '3 between the barrier layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer.
  • the configuration of Figure 4E is predicted to have a higher peak electron concentration than either of the configurations of Figures 4 A and 4B but may have a lower peak electron concentration than provided by the configuration of Figures 4C or 4D.
  • the configuration of Figure 4E is predicted to have a higher conduction band edge in the barrier layer than in Figure 4D due to the lower doping.
  • Figure 4F illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer that is delta doped at 1 x 10 cm " at the interface with the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer.
  • the configuration of Figure 4F is about the same as the configuration in Figure 4E due to the same sheet doping density in both structures with slightly lower conduction band bending in the barrier due to the reduced thickness of the doped region.
  • Figure 4G illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 10 19 cm "3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 30% indium and a 20 nm thick undoped GaN cap layer.
  • the configuration of Figure 4G is predicted to have a higher peak electron concentration than either of the configurations of Figures 4A and 4B.
  • Figure 4H illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 10 19 cm '3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 30% indium and a 30 nm thick undoped GaN cap layer.
  • the configuration of Figure 4H is predicted to have a slightly higher peak electron concentration than the configuration of Figure 4G as a result of the thicker GaN cap.
  • Figure 41 illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 10 19 cm “3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 20% indium and a 30 nm thick undoped GaN cap layer.
  • the configuration of Figure 41 is predicted to have a lower peak electron concentration than the configurations of Figure 4H due to the lower In percentage.
  • Figure 4 J illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 10 19 cm “3 between the cap layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 20% indium and a 26 nm thick undoped GaN cap layer.
  • the configuration of Figure 4 J is predicted to have two peaks in the electron concentration and has a lower peak electron concentration than configurations with a doped layer on the opposite side of the channel layer as seen in Figure 41.
  • a structure similar to that of Figure 4 J could be used as a MESFET, as mentioned above.
  • Figure 4K illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 10 19 cm "3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 30 nm thick undoped GaN cap layer.
  • the structure of Figure 4K has a higher back barrier due to the thicker InGaN layer. See United States Patent Application Serial No.
  • Figure 4L illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 run thick doped GaN layer with a dopant concentration of 3 X 10 19 cm "3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer. As seen in Figures 4K and 4L, a thicker GaN cap may increase the charge in the channel.
  • Figures 4M and 4N illustrate modeling of configurations that vary the thickness of the GaN doped layer.
  • the structure of Figure 4M has a higher In concentration than the structure of Figure 4L 5 resulting in a higher carrier concentration and higher conduction band in the barrier, but a lower mobility due to increased alloy scattering is likely.
  • Figure 4N has a thicker doped layer than Figure 4M and, therefore, a higher electron concentration in the channel and a lower conduction band energy in the barrier layer.
  • An aluminum free HEMT structure has been fabricated using a 60 nm GaN cap layer, a 6 nm InGaN channel layer with 20 % In and a 1.7 x 10 13 cm "2 Si delta doped region at the interface with a thick GaN barrier layer.
  • Such device structure exhibited a sheet resistivity of approximately 1200 ⁇ / ⁇ .
  • insulating layers such as SiN, an ONO structure or relatively high quality AlN may be deposited for making a MISHEMT and/or passivating the surface.
  • the additional layers may also include a compositionally graded transition layer or layers.
  • some embodiments of the present invention provide aluminum free embodiments of structures such as those described in, for example, U.S. Patent 6,316,793 and U.S. Patent Publication No. 2002/0066908A1 filed July 12, 2001 and published June 6, 2002, for "ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME," U. S. Patent No. 6,849,882 to Smorchkova et al.
  • HETEROJUNCTION TRANSISTORS HAVING CHARGE-TRANSFER INDUCED ENERGY BARRIERS AND METHODS OF FABRICATING THE SAME
  • U.S. Patent Application Serial No. 10/849,617 filed May 20, 2004 entitled “METHODS OF FABRICATINGNITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS AND NITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS”
  • Patent Application Serial No. 10/849,589 filed May 20, 2004 and entitled "SEMICONDUCTOR DEVICES HAVING A HYBRID CHANNEL LAYER, CURRENT APERTURE TRANSISTORS AND METHODS OF FABRICATING SAME," U.S. Patent Publication No. 2003/0020092 filed July 23, 2002 and published January 30, 2003 for "INSULATING GATE ALGAN/GAN HEMT", U.S. Patent Application Serial No.10/996,249, filed November 23, 2004 and entitled “CAP LAYERS AND/OR PASSFVATION LAYERS FOR NITRIDE- BASED TRANSISTORS, TRANSISTOR STRUCTURES AND METHODS OF

Abstract

Aluminum free high electron mobility transistors (HEMTs) and methods of fabricating aluminum free HEMTs are provided. In some embodiments, the aluminum free HEMTs include an aluminum free Group III-nitride barrier layer, an aluminum free Group III-nitride channel layer on the barrier layer and an aluminum free Group III-nitride cap layer on the channel layer.

Description

ALUMINUM FREE GROUP III-NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF FABRICATING SAME
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to transistors that incorporate nitride-based active layers.
BACKGROUND
Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for lower power and (in the case of Si) lower frequency applications. These, more familiar, semiconductor materials may not be well suited for higher power and/or high frequency applications, however, because of their relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs at room temperature) and/or relatively small breakdown voltages.
In light of the difficulties presented by Si and GaAs, interest in high power, high temperature and/or high frequency applications and devices has turned to wide bandgap semiconductor materials such as silicon carbide (2.996 eV for alpha SiC at room temperature) and the Group III nitrides (e.g., 3.36 eV for GaN at room temperature). These materials, typically, have higher electric field breakdown strengths and higher electron saturation velocities as compared to gallium arsenide and silicon. A device of particular interest for high power and/or high frequency applications is the High Electron Mobility Transistor (HEMT), which, in certain cases, is also known as a modulation doped field effect transistor (MODFET). These devices may offer operational advantages under a number of circumstances because a two-dimensional electron gas (2DEG) is formed at the heterojunction of two semiconductor materials with different bandgap energies, and where the smaller bandgap material has a higher electron affinity. The 2DEG is an accumulation layer in the undoped ("unintentionally doped"), smaller bandgap material and can contain a very high sheet electron concentration in excess of, for example, 1013 carriers/cm2. Additionally, electrons that originate in the wider-bandgap semiconductor transfer to the 2DEG, allowing a high electron mobility due to reduced ionized impurity scattering.
This combination of high carrier concentration and high carrier mobility can give the HEMT a very large transconductance and may provide a strong performance advantage over metal-semiconductor field effect transistors (MESFETs) for high- frequency applications.
High electron mobility transistors fabricated in the gallium nitride/aluminum gallium nitride (GaN/ AlGaN) material system have the potential to generate large amounts of RF power because of the combination of material characteristics that includes the aforementioned high breakdown fields, their wide bandgaps, large conduction band offset, and/or high saturated electron drift velocity. A major portion of the electrons in the 2DEG is attributed to polarization in the AlGaN. HEMTs in the GaN/AlGaN system have already been demonstrated. U.S. Patents 5,192,987 and 5,296,395 describe AlGaN/GaN HEMT structures and methods of manufacture. U.S. Patent No. 6,316,793, to Sheppard et al., which is commonly assigned and is incorporated herein by reference, describes a HEMT device having a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an aluminum gallium nitride barrier layer on the gallium nitride layer, and a passivation layer on the aluminum gallium nitride active structure.
Conventional HEMTs typically have an AlGaN layer on a GaN channel layer. However, the presence of aluminum in the active region of the device may reduce the reliability of the device as a result of oxidation effects, dislocation related pits and/or the presence of DX centers.
SUMMARY OF THE INVENTION
Some embodiments of the present invention provide high electron mobility transistors (HEMTs) and methods of fabricating HEMTs that include an aluminum free Group Ill-nitride barrier layer, an aluminum free Group Ill-nitride channel layer on the barrier layer and an aluminum free Group Ill-nitride cap layer on the channel layer. In some embodiments of the present invention, the barrier layer comprises a doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer. An undoped Group Ill-nitride layer may also be provided disposed between the doped Group Ill-nitride region and the channel layer. 06146
In additional embodiments of the present invention, the cap layer comprises a first doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer. An undoped Group Ill-nitride layer may be disposed between the first doped Group Ill-nitride region and the channel layer.
In some embodiments of the present invention, the barrier layer comprises a GaN layer, the channel layer comprises an InGaN layer and the cap layer comprises a GaN layer. The barrier layer may have a thickness of from about 0.1 μm to about 1000 μm, the channel layer may have a thickness of from about 1 nm to about 20 nm and the cap layer may have a thickness of from about 5 nm to about 100 nm. The InGaN layer may have a percentage of indium of from about 1 to about 100 percent.
In additional embodiments of the present invention, a first doped GaN layer is disposed between the GaN barrier layer and the InGaN channel layer. The first doped GaN layer may comprise a Si, Sn, O and/or Ge doped GaN layer. The first doped GaN layer may have a thickness of from about 0.2 nm to about 10 nm. The first doped GaN layer may have a dopant concentration of from about 1 x 10 cm" to about 1 x 1021 cm"3. A first undoped GaN layer may be disposed between the first doped GaN layer and the InGaN channel layer. The first undoped GaN layer may have a thickness of from about 0.3 nm to about 5 nm. In further embodiments of the present invention, a first doped GaN layer is disposed between the GaN cap layer and the InGaN channel layer. The first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer may comprise a Si, Sn, O and/or Ge doped GaN layer. The first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer may have a thickness of from about 0.2 nm to about 10 nm. The first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer may have a dopant concentration of from about 1 x 1016 cm"3 to about 1 x 1021 cm"3. A first undoped GaN layer may be disposed between the first doped GaN layer and the InGaN channel layer. The first undoped GaN layer disposed between the first doped GaN layer and the InGaN layer may have a thickness of from about 0.3 nm to about 5 nm. A second doped GaN layer may be disposed between the GaN barrier layer and the InGaN channel layer. The second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer may comprise a Si, Sn, O and/or Ge doped GaN layer. The second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer may have a thickness of from about 0.2 nm to about 10 irai. The second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer may have a dopant concentration of from about 1 x 1016 cm"3 to about 1 x 1021 cm"3. A second undoped GaN layer may be disposed between the second doped GaN layer and the InGaN channel layer. The second undoped GaN layer may have a thickness of from about 0.3 nm to about 5 nm.
In additional embodiments of the present invention, an InGaN layer is provided on the GaN cap layer opposite the InGaN channel layer. The InGaN layer on the GaN cap layer opposite the InGaN channel layer may have a thickness of from about 0.3 nm to about 100 nm.
In some embodiments of the present invention, a metal semiconductor field effect transistor (MESFET) is provided.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a cross-section of an aluminum free Group Ill-nitride based HEMT according to some embodiments of the present invention.
Figure 2 is a cross-section of an aluminum free GaN based HEMT according to some embodiments of the present invention.
Figures 3 A through 3D are cross-sections of aluminum free GaN based HEMTs according to further embodiments of the present invention. Figures 4A through 4N are graphs of carrier concentration and band diagrams from simulation models of transistors according to some embodiments of the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. As used herein the term "and/or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like numbers refer to like elements throughout the specification. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The exemplary term "lower", therefore, encompasses both an orientation of "lower" and "upper," depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary terms "below" or "beneath" can, therefore, encompass both an orientation of above and below.
Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have tapered, rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed "adjacent" another feature may have portions that overlap or underlie the adjacent feature.
Embodiments of the present invention provide aluminum free nitride-based HEMTs such as Group Ill-nitride based devices. As used herein, the term "Group III nitride" refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, gallium (Ga), and/or indium (In). As is well understood by those in this art, the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., InGaN), and quaternary compounds. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as InxGa1-xN where 0 < x < 1 are often used to describe them.
Furthermore, as used herein, aluminum free refers to the absence of Al intentionally incorporated into active layers of the Group Ill-nitride based device. For example, in some embodiments a region or layer with less than about 1% Al may be considered aluminum free. Thus, an active layer of a device may be Al free even if some Al is present in the active layer, for example, through unintentional incorporation by contamination during fabrication. Active layers of a device are the layers of the device where the 2DEG is formed and layers disposed between the layers where the 2DEG is formed and the source, drain and/or gate contacts and/or contact layers (i.e. layers on which a contact is directly formed) of the device. Aluminum is not, however, intentionally incorporated in the layers that form the 2DEG. Accordingly, in some embodiments of the present invention, Al may be present in layers between the layers that form the 2DEG and a substrate, in contacts and/or in the substrate. For example, Al may be in the substrate, nucleation and/or buffer layers and/or the ohmic contacts.
Figure 1 illustrates a HEMT structure according to some embodiments of the present invention. As seen in Figure 1, a substrate 10 is provided on which Group Ill-nitride based devices may be formed. In particular embodiments of the present invention, the substrate 10 may be a silicon carbide (SiC) substrate that may be, for example, 4H polytype of silicon carbide. Other silicon carbide candidate polytypes include the 3C, 6H, and 15R polytypes. In particular embodiments of the present invention, the substrate 10 may be semi-insulating. The term "semi-insulating" is used descriptively rather than in an absolute sense. In particular embodiments of the present invention, the silicon carbide bulk crystal has a resistivity equal to or higher than about 1x105 Ω-cm at room temperature. In other embodiments of the present invention, the substrate 10 may be conductive.
Optional buffer, nucleation and/or transition layers (not shown) may be provided on the substrate 10. For example, an AlN buffer layer may be provided to provide an appropriate crystal structure transition between the silicon carbide substrate and the remainder of the device. Additionally, strain balancing transition layer(s) may also be provided as described, for example, in commonly assigned U.S. Patent Publication No. 2003/0102482A1, filed July 19, 2002 and published June 5, 2003, and entitled "STRAIN BALANCED NITRIDE HETROJUNCTION TRANSISTORS AND METHODS OF FABRICATING STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTORS," and/or United States Patent No. 6,841,001, entitled "STRAIN COMPENSATED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING STRAIN COMPENSATED SEMICONDUCTOR STRUCTURES," the disclosures of which are incorporated herein by reference as if set forth fully herein.
Appropriate SiC substrates are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention, and methods for producing are described, for example, in U. S. Patent Nos. Re. 34,861 ; 4,946,547; 5,200,022; and 6,218,680, the contents of which are incorporated herein by reference in their entirety. Similarly, techniques for epitaxial growth of Group III nitrides have been described in, for example, U. S. Patent Nos. 5,210,051; 5,393,993; 5,523,589; and 5,592,501, the contents of which are also incorporated herein by reference in their entirety. Although silicon carbide may be used as a substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In some embodiments, an appropriate buffer layer also may be formed. For example, some embodiments of the present invention may utilize thick semi-insulating or insulating Group Ill-nitride layers and/or conducting substrates or layers as described in United States Patent Application Serial No.
(Attorney Docket No. 5308-551), filed April 11, 2005 and entitled "COMPOSITE SUBSTRATES OF CONDUCTIVE AND INSULTATING OR SEMI-INSULATING GROUP III-NITRIDES FOR GROUP III-NITRIDE DEVICES," and/or United States Patent Application Serial No. (Attorney Docket No. 5308-553), filed
April 11, 2005 and entitled "THICK SEMI-INSULATING OR INSULATING EPITAXIAL GALLIUMNITRIDE LAYERS AND DEVICES INCORPORATING SAME," the disclosures of which are incorporated herein by reference as if set forth in their entirety. Returning to Figure 1, an aluminum free Group III nitride barrier layer 12 is provided on the substrate 10. An aluminum free Group Ill-nitride channel layer 14 is provided on the barrier layer 12 and an aluminum free Group Ill-nitride cap layer 16 is provided on the channel layer 14. The barrier layer 12 may be deposited on the substrate 10 using buffer layers, transition layers, and/or nucleation layers as described above. The barrier layer 12 may be semi-insulating or insulating and/or may be unintentionally doped. In some embodiments, the barrier layer 12 and/or the cap layer 16 may include doped regions adjacent the channel layer 14. Furthermore, the barrier layer 12, channel layer 14, cap layer 16 and/or buffer nucleation and/or transition layers may be deposited by MOCVD or by other techniques known to those of skill in the art, such as MBE or HVPE .
The barrier layer 12 may be undoped or unintentionally doped. In some embodiments, the barrier layer 12 may include a thick semi-insulating or insulating layer with an undoped or unintentionally doped region adjacent the channel layer 14. The barrier layer 12 should be thick enough to prevent migration of Al in layers disposed opposite the channel layer 14 to the channel layer 14. Thus, portions of the barrier layer 12 may unintentionally include Al while still being an aluminum free Group Ill-nitride layer. For example, in some embodiments of the present invention, the barrier layer 12 may be from about 1 nm to about 1 x 106 nm thick and may have less than about 1% aluminum, hi some embodiments of the present invention, the barrier layer 12 is about 1000 A thick. Furthermore, a portion of the barrier layer 12 distal from the channel layer 14 may be doped with Fe or other elements to make it more insulating or provide a larger barrier as described in the above referenced patent applications. The barrier layer 12 may be provided as part or all of the substrate 10 or as a separate layer on the substrate 10.
In some embodiments of the present invention, the channel layer 14 is a Group Ill-nitride, such as InxGa1-xN, where 0<x<l provided that the energy of the conduction band edge of the channel layer 14 is less than the energy of the conduction band edge of the cap layer 16 at the interface between the channel and cap layers. In particular, the channel layer 14 may have a bandgap that is less than the bandgap of the cap layer 16 and the channel layer 14 may also have a larger electron affinity than the cap layer 16. Embodiments of the present invention where the channel layer 14 is InN (i.e. x=l) may exhibit lower alloy scatter because InN is a binary material. The channel layer 14 may be undoped or unintentionally doped and may be grown to a thickness of greater than about 10 A. For example, in some embodiments, the channel layer 14 may have a thickness of from about 10 A to about 200 A. The channel layer 14 may also be a multi-layer structure, such as a superlattice or combinations of GaN, InGaN or the like. In some embodiments of the present invention, the channel layer 14 has less than about 1% aluminum. In particular embodiments of the present invention, the cap layer 16 is thick enough and/or has a high enough doping to induce a significant carrier concentration at the interface between the channel layer 14 and the cap layer 16 through polarization effects. As discussed above, the cap layer 16 may be a Group Ill-nitride and has a bandgap larger than that of the channel layer 14 and a smaller electron affinity than the channel layer 14. For example, the cap layer 16 may be GaN or InGaN. If the cap layer 16 is InGaN the cap layer 16 should have a lower indium percentage than is present in the channel layer 14. The cap layer 16 may, for example, be from about 5 nm to about 100 nm thick, but is not so thick as to cause cracking or substantial defect formation therein. The cap layer 16 may be thicker if the gate contact 24 is recessed into the cap layer 16. In certain embodiments of the present invention, the cap layer 16 is undoped and/or doped with an n-type dopant to a concentration of 1 x 1016 cm"3 about 1 x 10 cm" . hi some embodiments of the present invention, the cap layer 16 has less than about 1% aluminum. Source and drain ohmic contacts 20 and 22 are provided on the cap layer 16 and a gate contact 24 is disposed between the source and drain contacts 20 and 22. Suitable ohmic contact materials may include, for example, Ti, Al, Ni and/orAu. Suitable gate materials may depend on the composition of the cap layer, however, in certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, W and/or WSiN.
Figure 2 is a schematic diagram of HEMTs according to further embodiments of the present invention. As seen in Figure 2, a GaN barrier layer 112 is provided on a substrate 110. The substrate 110 may be a substrate as described above with reference to the substrate 10. Furthermore, optional buffer, nucleation and/or transition layers (not shown) may be provided on the substrate 110 as described above. These optional buffer, nucleation and/or transition layers may include aluminum. In particular embodiments of the present invention, the substrate 110 is a GaN substrate. As is further illustrated in Figure 2, an InGaN channel layer 114 is provided on the GaN barrier layer 112. A GaN cap layer 116 is provided on the InGaN channel layer 114.
In particular embodiments of the present invention, the GaN barrier layer 112 is a thick GaN layer and may be undoped, unintentionally doped and/or semi- insulating or insulating. For example, the GaN barrier layer 112 may be semi- insulating or insulating in a region proximate the substrate 110 and may be undoped or unintentionally doped in a region proximate the InGaN channel layer 114. The GaN barrier layer 112 should be sufficiently thick to prevent migration of Al in layers disposed opposite the channel layer 114 to the channel layer 114. Thus, portions of the barrier layer 112 may unintentionally include Al while still being an aluminum free layer. In some embodiments of the present invention, the barrier layer 112 may be from about 10 nm to about 1 x 106 nm thick. In particular embodiments of the present invention, the barrier layer 112 is at least about 1000 A thick. In some embodiments of the present invention, the barrier layer 112 has less than about 1% aluminum.
The InGaN channel layer 114 may be InxG1-xaN, where 0<x< 1 provided that the energy of the conduction band edge of the channel layer 114 is less than the energy of the conduction band edge of the cap layer 116 at the interface between the channel and cap layers. In particular, the channel layer 114 may have a bandgap that is less than the bandgap of the cap layer 116 and the channel layer 114 may also have a larger electron affinity than the cap layer 116. The channel layer 114 may be undoped or unintentionally doped and may be grown to a thickness of greater than about 10 A. For example, in some embodiments, the channel layer 114 may have a thickness of from about 10 A to about 200 A. The maximum thickness of the channel layer 114 may depend on the percentage of indium in the channel layer 114. The lower the percentage of indium in the channel layer 114, the thicker the channel layer 114 may be before an undesirable two dimensional hole gas is formed for Ga polar devices. A low or high indium percentage may be desirable to reduce or minimize impurity scattering. In particular embodiments of the present invention, the indium percentage is the channel layer 114 is about 30% or less. In some embodiments, the indium percentage is the channel layer 114 is about 20%. In some embodiments of the present invention, the channel layer 114 has less than about 1% aluminum.
The GaN cap layer 116 is thick enough and/or has a high enough doping to induce a significant carrier concentration at the interface between the channel layer 114 and the cap layer 116. In some embodiments of the present invention, the GaN cap layer 116 is from about 1 nm to about 100 nm thick, but is not so thick as to cause cracking or substantial defect formation therein. In some embodiments of the present invention, the cap layer 116 has less than about 1% aluminum. As discussed above, with reference to the cap layer 16, the cap layer 116 may be thicker if the gate contact 24 is recessed into the cap layer 116.
Optionally, an InGaN layer (not shown) may be provided on the GaN cap layer 116. The InGaN layer may increase the barrier to the surface from the channel. If an InGaN layer is provided on the GaN cap layer 116, the InGaN layer may have an indium composition of from about 1% to 100% and may have a thickness of from about 1 ran to about 100 nm.
Figures 3 A through 3D are schematic illustrations of further embodiments of HEMTs according the present invention having doped and/or spacer layers adjacent an InGaN channel layer 214. As seen in Figures 3 A through 3D a GaN barrier layer 212 is provided on a substrate 210. An InGaN channel layer 214 is provided on the GaN barrier layer 212 and a GaN cap layer 216 is provided on the InGaN channel layer 214. The substrate 210, GaN barrier layer 212, InGaN channel layer 214 and GaN cap layer 216 may be provided as described above with reference to the substrate 110, GaN barrier layer 112, InGaN channel layer 114 and GaN cap layer 116 of Figure 2. The optional buffer, nucleation and/or transition layers described above may also be provided. An optional InGaN layer (not shown) may also be provided on the cap layer 216 as described above.
Figure 3 A illustrates embodiments of the present invention where a doped GaN layer 230 is disposed between the GaN barrier layer 212 and the InGaN channel layer 214. hi some embodiments of the present invention, the doped GaN layer 230 may be doped with Si, Ge, Sn and/or O and may have a dopant concentration of from about 1 x 1016 cm"3 to about 1 x 1021 cm"3, hi particular embodiments, the dopant concentration may be about 1 x 1020 cm"3. Furthermore, the doped GaN layer 230 may be from about 0.2 nm to about 10 nm thick. The doping concentration should be high enough and the layer thick enough to supply sufficient electrons to the 2DEG channel, but not so high or thick as to have additional, unintentional n-type regions outside of the channel region. In particular embodiments, the dopant may be Sn and/or Ge. hi other embodiments, the dopant may be Si. The doped GaN layer 230 may be provided as a delta doped region. In particular embodiments of the present invention, the doped layer 230 provides a sheet density of from about 1 x 1012 cm"2 to about 1 x 1014 cm"2 at the interface with the channel layer 214.
While the doped layer 230 is described above with reference to a GaN layer, in some embodiments of the present invention, the doped layer 230 may be provided by an InGaN layer. Thus, for example, the doped layer 230 may be provided by a doped region of the InGaN channel layer 214. In such a case, the InGaN channel layer 214 should be thick enough and the doped portion thin enough and doped lightly enough so that electrons from the doping are supplied to the 2DEG and do not form an n-type region in the doped region.
Figure 3B illustrates embodiments of the present invention where a doped GaN layer 230 is disposed between the GaN barrier layer 212 and the InGaN channel layer 214 and an undoped GaN layer 240 is disposed between the doped GaN layer 230 and the InGaN channel layer 214. In some embodiments of the present invention, the undoped GaN layer 240 may be from about 0.5 run to about 5 nm thick. The undoped GaN layer 240 may space the doped layer 230 from the channel layer 214 to reduce and/or minimize impurity scattering.
Figure 3 C illustrates embodiments of the present invention where a doped GaN layer 250 is disposed between the GaN cap layer 216 and the InGaN channel layer 214. In some embodiments of the present invention, the doped GaN layer 250 may be doped with Si, Sn, Ge and/or O and may have a dopant concentration of from about 1 x 1016 cm"3 to about 1 x 1021 cm"3. Furthermore, the doped GaN layer 250 may be from about 0.2 nm to about 100 nm thick. The structure of Figure 3C could be used as a MESFET with the InGaN channel layer 214 acting more as a back barrier than a channel if the GaN layer 250 is doped heavily enough. Mobility may be better in the doped GaN layer 250 than in the InGaN channel layer 214 depending on the doping density and the indium percentage.
Figure 3D illustrates embodiments of the present invention where a doped GaN layer 250 is disposed between the GaN cap layer 216 and the InGaN channel layer 214 and an undoped GaN layer 260 is disposed between the doped GaN layer 250 and the InGaN channel layer 214. In some embodiments of the present invention, the undoped GaN layer 260 may be from about 0.3 nm to about 10 nm thick. The undoped GaN layer 260 may space the doped layer 250 from the channel layer 214 to reduce and/or minimize impurity scattering. While embodiments of the present invention are illustrated in Figures 3 A through 3D as including doped and/or undoped layers on one side or the other of the InGaN channel layer 214, combinations and subcombinations of the structures illustrated in Figures 3A through 3D may also be provided. For example, a structure with a doped layer between the cap layer 216 and the channel layer 214 may also have a doped layer between the barrier layer 212 and the channel layer 214.
A passivation layer (not shown) may also be provided on the structures of Figures 1 through 3D. In certain embodiments of the present invention, the passivation layer may be silicon nitride, aluminum nitride, silicon dioxide, an ONO structure and/or an oxynitride. Furthermore, the passivation layer may be a single or multiple layers of uniform and/or non-uniform composition.
Figures 4 A through 4N are graphs of carrier concentration and band diagrams from simulation models of transistors according to some embodiments of the present invention, hi the simulations depicted in Figures 4 A through 4N5 the aluminum free layers are modeled as having 0% aluminum. These simulations are not meant to be exact but are provided to illustrate possible trends and to estimate properties of different designs. Accordingly, these graphs are provided as a rough estimate of possible characteristics of the simulated device structures but are only as accurate as the underlying assumptions and models. Accordingly, the properties of actual devices may differ from those illustrated in Figures 4A through 4N.
Figure 4A illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick InGaN channel layer with 30% indium and a 10 nm thick undoped GaN cap layer. Figure 4B illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick InGaN channel layer with 30% indium and a 20 nm thick undoped GaN cap layer. By comparing Figures 4A and 4B, an increase in peak electron concentration is predicted as a result of increasing the thickness of the GaN cap layer. Figure 4C illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 1 nm thick doped GaN layer with a dopant concentration of 18 X 1019 cm"3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 6 nm thick InGaN channel layer with 30% indium and a 60 nm thick undoped GaN cap layer. As seen in Figure 4C, the configuration of Figure 4C is predicted to have a higher peak electron concentration than either of the configurations of Figures 4A and 4B.
Figure 4D illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 1 nm thick doped GaN layer with a dopant concentration of 20 X 1019 cm"3 between the barrier layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer. As seen in Figure 4D, the configuration of Figure 4D is predicted to have a higher peak electron concentration than either of the configurations of Figures 4 A and 4B but may have a lower peak electron concentration than provided by the configuration of Figure 4C.
Figure 4E illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 1 nm thick doped GaN layer with a dopant concentration of 10 X 1019 cm'3 between the barrier layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer. As seen in Figure 4E, by increasing the dopant concentration in the doped GaN layer and increasing the thickness of the GaN cap layer, the configuration of Figure 4E is predicted to have a higher peak electron concentration than either of the configurations of Figures 4 A and 4B but may have a lower peak electron concentration than provided by the configuration of Figures 4C or 4D. The configuration of Figure 4E is predicted to have a higher conduction band edge in the barrier layer than in Figure 4D due to the lower doping.
Figure 4F illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer that is delta doped at 1 x 10 cm" at the interface with the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer. As seen in Figure 4F, the configuration of Figure 4F is about the same as the configuration in Figure 4E due to the same sheet doping density in both structures with slightly lower conduction band bending in the barrier due to the reduced thickness of the doped region.
Figure 4G illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 1019 cm"3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 30% indium and a 20 nm thick undoped GaN cap layer. As seen in Figure 4G, the configuration of Figure 4G is predicted to have a higher peak electron concentration than either of the configurations of Figures 4A and 4B. Figure 4H illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 1019 cm'3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 30% indium and a 30 nm thick undoped GaN cap layer. As seen in Figure 4H, the configuration of Figure 4H is predicted to have a slightly higher peak electron concentration than the configuration of Figure 4G as a result of the thicker GaN cap.
Figure 41 illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 1019 cm"3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 20% indium and a 30 nm thick undoped GaN cap layer. As seen in Figure 41, the configuration of Figure 41 is predicted to have a lower peak electron concentration than the configurations of Figure 4H due to the lower In percentage.
Figure 4 J illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 1019 cm"3 between the cap layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 3 nm thick InGaN channel layer with 20% indium and a 26 nm thick undoped GaN cap layer. As seen in Figure 4 J, the configuration of Figure 4 J is predicted to have two peaks in the electron concentration and has a lower peak electron concentration than configurations with a doped layer on the opposite side of the channel layer as seen in Figure 41. A structure similar to that of Figure 4 J could be used as a MESFET, as mentioned above.
Figure 4K illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 nm thick doped GaN layer with a dopant concentration of 3 X 1019 cm"3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 30 nm thick undoped GaN cap layer. In comparison to the structure of Figure 41, the structure of Figure 4K has a higher back barrier due to the thicker InGaN layer. See United States Patent Application Serial No. 10/772,882, filed February 5, entitled "NITRIDE HETEROJUNCTION TRANSISTORS HAVING CHARGE-TRANSFER INDUCED ENERGY BARRIERS AND METHODS OF FABRICATING THE SAME," the disclosure of which is incorporated herein as if set forth fully herein.
Figure 4L illustrates a modeled band diagram and electron concentration for an aluminum free HEMT with a thick undoped GaN barrier layer, a 3 run thick doped GaN layer with a dopant concentration of 3 X 1019 cm"3 between the barrier layer and the channel layer, a 1 nm thick undoped GaN layer between the doped GaN layer and the channel layer, a 6 nm thick InGaN channel layer with 20% indium and a 60 nm thick undoped GaN cap layer. As seen in Figures 4K and 4L, a thicker GaN cap may increase the charge in the channel.
Figures 4M and 4N illustrate modeling of configurations that vary the thickness of the GaN doped layer. The structure of Figure 4M has a higher In concentration than the structure of Figure 4L5 resulting in a higher carrier concentration and higher conduction band in the barrier, but a lower mobility due to increased alloy scattering is likely. As seen in Figures 4M and 4N, Figure 4N has a thicker doped layer than Figure 4M and, therefore, a higher electron concentration in the channel and a lower conduction band energy in the barrier layer.
An aluminum free HEMT structure according to some embodiments of the present invention has been fabricated using a 60 nm GaN cap layer, a 6 nm InGaN channel layer with 20 % In and a 1.7 x 1013 cm"2 Si delta doped region at the interface with a thick GaN barrier layer. Such device structure exhibited a sheet resistivity of approximately 1200 Ω/α.
While embodiments of the present invention have been described herein with reference to particular HEMT structures, the present invention should not be construed as limited to such structures. For example, additional layers may be included in the HEMT device while still benefiting from the teachings of the present invention. In some embodiments, insulating layers such as SiN, an ONO structure or relatively high quality AlN may be deposited for making a MISHEMT and/or passivating the surface. The additional layers may also include a compositionally graded transition layer or layers.
Also, other structures, such as recessed or "T" gate structures, regrown contact regions or the like may also be provided. Accordingly, some embodiments of the present invention provide aluminum free embodiments of structures such as those described in, for example, U.S. Patent 6,316,793 and U.S. Patent Publication No. 2002/0066908A1 filed July 12, 2001 and published June 6, 2002, for "ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME," U. S. Patent No. 6,849,882 to Smorchkova et al. , entitled "GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER", U.S. Patent Application Serial No. 10/617,843 filed July 11, 2003 for "NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATION THEREOF USING NON-ETCHED CONTACT RECESSES," U.S. Patent Application Serial No. 10/772,882 filed February 5, 2004 for "NITRIDE
HETEROJUNCTION TRANSISTORS HAVING CHARGE-TRANSFER INDUCED ENERGY BARRIERS AND METHODS OF FABRICATING THE SAME," U.S. Patent Application Serial No. 10/897,726, filed July 23, 2004 entitled "METHODS OF FABRICATINGNITRIDE-BASED TRANSISTORS WITH A CAP LAYER AND A RECESSED GATE," U.S. Patent Application Serial No. 10/849,617, filed May 20, 2004 entitled "METHODS OF FABRICATINGNITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS AND NITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS," U.S. Patent Application Serial No. 10/849,589, filed May 20, 2004 and entitled "SEMICONDUCTOR DEVICES HAVING A HYBRID CHANNEL LAYER, CURRENT APERTURE TRANSISTORS AND METHODS OF FABRICATING SAME," U.S. Patent Publication No. 2003/0020092 filed July 23, 2002 and published January 30, 2003 for "INSULATING GATE ALGAN/GAN HEMT", U.S. Patent Application Serial No.10/996,249, filed November 23, 2004 and entitled "CAP LAYERS AND/OR PASSFVATION LAYERS FOR NITRIDE- BASED TRANSISTORS, TRANSISTOR STRUCTURES AND METHODS OF
FABRICATING SAME," United States Patent Application Serial No.
(Attorney Docket No. 5308-516), filed March 15, 2005 and entitled "GROUP III NITRIDE FIELD EFFECT TRANSISTORS (FETs) CAPABLE OF WITHSTANDING HIGH TEMPERATURE REVERSE BIAS TEST
CONDITIONS," United States Patent Application Serial No. 11/005,107, filed December 6, 2004 and entitled " HIGH POWER DENSITY AND/OR LINEARITY TRANSISTORS," and United States Patent Application Serial No. 11/005,423, filed December 6, 2004 and entitled "FIELD EFFECT TRANSISTORS (FETs) HAVING MULTI-WATT OUTPUT POWER AT MILLIMETER-WAVE FREQUENCIES," the disclosures of which are incorporated herein as if described in their entirety. Embodiments of the present invention may also be utilized with HEMT structures such as described in, for example, Yu et al., "Schottky barrier engineering in III-V nitrides via the piezoelectric effect," Applied Physics Letters, Vol. 73, No. 13, 1998, or in U.S. Patent No. 6,584,333 filed July 12, 2001, for "ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME," the disclosures of which are incorporated herein by reference as if set forth fully herein.
In the drawings and specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

THAT WHICH IS CLAIMED IS:
1. A high electron mobility transistor (HEMT), comprising: an aluminum free Group Ill-nitride barrier layer; an aluminum free Group Ill-nitride channel layer on the barrier layer; and an aluminum free Group Ill-nitride cap layer on the channel layer.
2. The HEMT of Claim 1, wherein the barrier layer comprises a doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
3. The HEMT of Claim 2, further comprising an undoped Group III- nitride layer disposed between the doped Group Ill-nitride region and the channel layer.
4. The HEMT of Claim 2, wherein the cap layer comprises a first doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
5. The HEMT of Claim 4, further comprising an undoped Group III- nitride layer disposed between the first doped Group Ill-nitride region and the channel layer.
6. The HEMT of Claim 1, wherein the cap layer comprises a first doped
Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
7. The HEMT of Claim 6, further comprising an undoped Group III- nitride layer disposed between the first doped Group Ill-nitride region and the channel layer.
8. The HEMT of Claim 1 , wherein the barrier layer comprises a GaN layer, the channel layer comprises an InGaN layer and the cap layer comprises a GaN layer.
9. The HEMT of Claim 8, wherein the barrier layer has a thickness of from about 1 nm to about 1 mm, the channel layer has a thickness of from about 0.3 ran to about 50 nm and the cap layer has a thickness of from about 1 nm to about 100 ran.
10. The HEMT of Claim 8, wherein the InGaN layer has a percentage of indium of from about 1 % to about 100 %.
11. The HEMT of Claim 8, further comprising a first doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer.
12. The HEMT of Claim 11 , wherein the first doped GaN layer comprises a Si, Sn, O and/or Ge doped GaN layer.
13. The HEMT of Claim 11 , wherein the first doped GaN layer has a thickness of from about 0.2 nm to about 10 nm.
14. The HEMT of Claim 11 , wherein the first doped GaN layer has a dopant concentration of from about 1 x 1017 cm"3 to about 1 x 1021 cm"3.
15. The HEMT of Claim 11 , further comprising a first undoped GaN layer disposed between the first doped GaN layer and the InGaN channel layer.
16. The HEMT of Claim 15 , wherein the first undoped GaN layer has a thickness of from about 0.3 nm to about 10 nm.
17. The HEMT of Claim 8, further comprising a first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer.
18. The HEMT of Claim 17, wherein the first doped GaN layer comprises a Si, Sn, O and/or Ge doped GaN layer.
19. The HEMT of Claim 17, wherein the first doped GaN layer has a thickness of from about 0.2 nm to about 10 nm.
20. The HEMT of Claim 17, wherein the first doped GaN layer has a dopant concentration of from about 1 x 1017 cm"3 to about 1 x 1021 cm"3.
21. The HEMT of Claim 17, further comprising a first undoped GaN layer disposed between the first doped GaN layer and the InGaN channel layer.
22. The HEMT of Claim 2I5 wherein the first undoped GaN layer has a thickness of from about 0.3 nm to about 10 ran.
23. The HEMT of Claim 17, further comprising a second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer.
24. The HEMT of Claim 23, wherein the second doped GaN layer comprises a Si, Sn, O and/or Ge doped GaN layer.
25. The HEMT of Claim 23, wherein the second doped GaN layer has a thickness of from about 0.2 nm to about 10 nm.
26. The HEMT of Claim 23, wherein the second doped GaN layer has a dopant concentration of from about 1 x 1017 cm"3 to about 1 x 10 l cm" .
27. The HEMT of Claim 23, further comprising a second undoped GaN layer disposed between the second doped GaN layer and the InGaN channel layer.
28. The HEMT of Claim 27, wherein the second undoped GaN layer has a thickness of from about 0.3 nm to about 10 nm.
29. The HEMT of Claim 8, further comprising an InGaN layer on the GaN cap layer opposite the InGaN channel layer.
30. The HEMT of Claim 29, wherein the InGaN layer on the GaN cap layer opposite the InGaN channel layer has a thickness of from about 0.3 nm to about 50 nm.
31. A method of fabricating a high electron mobility transistor (HEMT), comprising: forming an aluminum free Group Ill-nitride barrier layer; forming an aluminum free Group Ill-nitride channel layer on the barrier layer; and forming an aluminum free Group Ill-nitride cap layer on the channel layer.
32. The method of Claim 31 , wherein the barrier layer comprises a doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
33. The method of Claim 32, further comprising forming an undoped Group Ill-nitride layer disposed between the doped Group Ill-nitride region and the channel layer.
34. The method of Claim 32, wherein the cap layer comprises a first doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
35. The method of Claim 34, further comprising forming an undoped Group Ill-nitride layer disposed between the first doped Group Ill-nitride region and the channel layer.
36. The method of Claim 31 , wherein the cap layer comprises a first doped
Group Ill-nitride region adjacent the aluminum free Group Ill-nitride channel layer.
37. The method of Claim 36, further comprising forming an undoped Group Ill-nitride layer disposed between the first doped Group Ill-nitride region and the channel layer.
38. The method of Claim 31 , wherein the barrier layer comprises a GaN layer, the channel layer comprises an InGaN layer and the cap layer comprises a GaN layer.
39. The method of Claim 38, wherein the barrier layer has a thickness of from about 1 nm to about 1 mm, the channel layer has a thickness of from about 0.3 nm to about 50 nm and the cap layer has a thickness of from about 1 nm to about 100 nm.
40. The method of Claim 38, wherein the InGaN layer has a percentage of indium of from about 1 % to about 100 %.
41. The method of Claim 38, further comprising a first doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer.
42. The method of Claim 41 , wherein the first doped GaN layer comprises a Si5 Sn, O and/or Ge doped GaN layer.
43. The method of Claim 41 , wherein the first doped GaN layer has a thickness of from about 0.2 nm to about 10 nm.
44. The method of Claim 41, wherein the first doped GaN layer has a dopant concentration of from about 1 x 1017 cm"3 to about 1 x 1021 cm'3.
45. The method of Claim 41 , further comprising forming a first undoped GaN layer disposed between the first doped GaN layer and the InGaN channel layer.
46. The method of Claim 45, wherein the first undoped GaN layer has a thickness of from about 0.3 nm to about 10 nm.
47. The method of Claim 38, further comprising forming a first doped GaN layer disposed between the GaN cap layer and the InGaN channel layer.
48. The method of Claim 47, wherein the first doped GaN layer comprises a Si, Sn, O and/or Ge doped GaN layer.
49. The method of Claim 47, wherein the first doped GaN layer has a thickness of from about 0.2 nm to about 10 nm.
50. The method of Claim 47, wherein the first doped GaN layer has a dopant concentration of from about 1 x 1017 cm'3 to about 1 x 1021 cm"3.
51. The method of Claim 47, further comprising a first undoped GaN layer disposed between the first doped GaN layer and the InGaN channel layer.
52. The method of Claim 51 , wherein the first undoped GaN layer has a thickness of from about 0.3 nm to about 10 nm.
53. The method of Claim 47, further comprising forming a second doped GaN layer disposed between the GaN barrier layer and the InGaN channel layer.
54. The method of Claim 53, wherein the second doped GaN layer comprises a Si, Sn, O and/or Ge doped GaN layer.
55. The method of Claim 53, wherein the second doped GaN layer has a thickness of from about 0.2 nm to about 10 nm.
56. The method of Claim 53, wherein the second doped GaN layer has a dopant concentration of from about 1 x 1017 cm"3 to about 1 x 1021 cm'3.
57. The method of Claim 53, further comprising forming a second undoped GaN layer disposed between the second doped GaN layer and the LiGaN channel layer.
58. The method of Claim 57, wherein the second undoped GaN layer has a thickness of from about 0.3 nm to about 10 nm.
59. The method of Claim 38, further comprising forming an InGaN layer on the GaN cap layer opposite the InGaN channel layer.
60. The method of Claim 59, wherein the InGaN layer on the GaN cap layer opposite the InGaN channel layer has a thickness of from about 0.3 nm to about 50 nm.
61. The method of Claim 36, wherein the transistor comprises a metal semiconductor field effect transistor (MESFET).
62. The HEMT of Claim 6, wherein the transistor comprises a metal semiconductor field effect transistor (MESFET).
63. The HEMT of Claim 1 , wherein the channel layer comprises a doped Group Ill-nitride region adjacent the aluminum free Group Ill-nitride barrier layer.
64. The HEMT of Claim 63, wherein the channel layer comprises an InGaN channel layer and the barrier layer comprises a GaN barrier layer, the InGaN channel layer comprising a doped region adjacent the GaN barrier layer.
65. The HEMT of Claim 1, wherein the aluminum free Group Ill-nitride barrier layer comprises a substantially relaxed InxGa1-xN layer where x >0, the aluminum free Group Ill-nitride channel layer on the barrier layer comprises an LIyGa1 -yN layer where y > x and the aluminum free Group Ill-nitride cap layer on the channel layer comprises an In2Ga1-2N layer where z<x.
66. The HEMT of Claim 65, wherein the barrier layer, channel layer and cap layer are strain balanced.
67. The HEMT of Claim 65, wherein y=l .
68. The HEMT of Claim 65, wherein z =0.
69. The HEMT of Claim 68, wherein y=l .
PCT/US2006/006146 2005-04-29 2006-02-23 Aluminum free group iii-nitride based high electron mobility transistors and methods of fabricating same WO2006118632A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06735699A EP1875514A1 (en) 2005-04-29 2006-02-23 Aluminum free group iii-nitride based high electron mobility transistors and methods of fabricating same
JP2008508832A JP2008539586A (en) 2005-04-29 2006-02-23 Aluminum-free group III-nitride based high electron mobility transistor and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/118,575 US7615774B2 (en) 2005-04-29 2005-04-29 Aluminum free group III-nitride based high electron mobility transistors
US11/118,575 2005-04-29

Publications (1)

Publication Number Publication Date
WO2006118632A1 true WO2006118632A1 (en) 2006-11-09

Family

ID=36540139

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/006146 WO2006118632A1 (en) 2005-04-29 2006-02-23 Aluminum free group iii-nitride based high electron mobility transistors and methods of fabricating same

Country Status (5)

Country Link
US (1) US7615774B2 (en)
EP (1) EP1875514A1 (en)
JP (1) JP2008539586A (en)
TW (1) TW200644246A (en)
WO (1) WO2006118632A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11557668B2 (en) 2018-04-25 2023-01-17 Sumitomo Electric Device Innovations, Inc. High electron mobility transistor with reverse arrangement of channel layer and barrier layer

Families Citing this family (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612390B2 (en) 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
US7417266B1 (en) 2004-06-10 2008-08-26 Qspeed Semiconductor Inc. MOSFET having a JFET embedded as a body diode
US7436039B2 (en) * 2005-01-06 2008-10-14 Velox Semiconductor Corporation Gallium nitride semiconductor device
JP4792814B2 (en) * 2005-05-26 2011-10-12 住友電気工業株式会社 High electron mobility transistor, field effect transistor, epitaxial substrate, method for producing epitaxial substrate, and method for producing group III nitride transistor
US9331192B2 (en) 2005-06-29 2016-05-03 Cree, Inc. Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same
US20070018198A1 (en) * 2005-07-20 2007-01-25 Brandes George R High electron mobility electronic device structures comprising native substrates and methods for making the same
US8026568B2 (en) 2005-11-15 2011-09-27 Velox Semiconductor Corporation Second Schottky contact metal layer to improve GaN Schottky diode performance
JPWO2007069601A1 (en) * 2005-12-14 2009-05-21 日本電気株式会社 Field effect transistor
KR101294518B1 (en) * 2006-02-14 2013-08-07 엘지이노텍 주식회사 Nitride semiconductor light-emitting device and manufacturing method thereof
US7728402B2 (en) 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
KR101529331B1 (en) 2006-08-17 2015-06-16 크리 인코포레이티드 High power insulated gate bipolar transistors
US8823057B2 (en) 2006-11-06 2014-09-02 Cree, Inc. Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
US7939853B2 (en) * 2007-03-20 2011-05-10 Power Integrations, Inc. Termination and contact structures for a high voltage GaN-based heterojunction transistor
JP5292716B2 (en) * 2007-03-30 2013-09-18 富士通株式会社 Compound semiconductor device
US8519438B2 (en) 2008-04-23 2013-08-27 Transphorm Inc. Enhancement mode III-N HEMTs
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8289065B2 (en) 2008-09-23 2012-10-16 Transphorm Inc. Inductive load power switching circuits
US7898004B2 (en) 2008-12-10 2011-03-01 Transphorm Inc. Semiconductor heterostructure diodes
JP5737948B2 (en) * 2008-12-26 2015-06-17 ルネサスエレクトロニクス株式会社 Heterojunction field effect transistor, method of manufacturing heterojunction field transistor, and electronic device
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8742459B2 (en) 2009-05-14 2014-06-03 Transphorm Inc. High voltage III-nitride semiconductor devices
US8629509B2 (en) 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8541787B2 (en) 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US8390000B2 (en) 2009-08-28 2013-03-05 Transphorm Inc. Semiconductor devices with field plates
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9312343B2 (en) 2009-10-13 2016-04-12 Cree, Inc. Transistors with semiconductor interconnection layers and semiconductor channel layers of different semiconductor materials
JP5625338B2 (en) * 2009-11-30 2014-11-19 日亜化学工業株式会社 Field effect transistor
US8389977B2 (en) 2009-12-10 2013-03-05 Transphorm Inc. Reverse side engineered III-nitride devices
US8563372B2 (en) * 2010-02-11 2013-10-22 Cree, Inc. Methods of forming contact structures including alternating metal and silicon layers and related devices
US9214352B2 (en) 2010-02-11 2015-12-15 Cree, Inc. Ohmic contact to semiconductor device
US9548206B2 (en) 2010-02-11 2017-01-17 Cree, Inc. Ohmic contact structure for group III nitride semiconductor device having improved surface morphology and well-defined edge features
KR101774933B1 (en) * 2010-03-02 2017-09-06 삼성전자 주식회사 High Electron Mobility Transistor representing dual depletion and method of manufacturing the same
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
JP2011228442A (en) * 2010-04-19 2011-11-10 Hitachi Cable Ltd Nitride semiconductor wafer and nitride semiconductor device
US8816395B2 (en) * 2010-05-02 2014-08-26 Visic Technologies Ltd. Field effect power transistors
US8742460B2 (en) 2010-12-15 2014-06-03 Transphorm Inc. Transistors with isolation regions
US8643062B2 (en) 2011-02-02 2014-02-04 Transphorm Inc. III-N device structures and methods
US8772842B2 (en) 2011-03-04 2014-07-08 Transphorm, Inc. Semiconductor diodes with low reverse bias currents
US8716141B2 (en) 2011-03-04 2014-05-06 Transphorm Inc. Electrode configurations for semiconductor devices
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9673283B2 (en) 2011-05-06 2017-06-06 Cree, Inc. Power module for supporting high current densities
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US8901604B2 (en) 2011-09-06 2014-12-02 Transphorm Inc. Semiconductor devices with guard rings
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US9257547B2 (en) 2011-09-13 2016-02-09 Transphorm Inc. III-N device structures having a non-insulating substrate
JP6017125B2 (en) * 2011-09-16 2016-10-26 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
US8598937B2 (en) 2011-10-07 2013-12-03 Transphorm Inc. High power semiconductor electronic components with increased reliability
US8633094B2 (en) 2011-12-01 2014-01-21 Power Integrations, Inc. GaN high voltage HFET with passivation plus gate dielectric multilayer structure
US8940620B2 (en) 2011-12-15 2015-01-27 Power Integrations, Inc. Composite wafer for fabrication of semiconductor devices
JP2013131650A (en) * 2011-12-21 2013-07-04 Fujitsu Ltd Semiconductor device and method of manufacturing the same
US9165766B2 (en) 2012-02-03 2015-10-20 Transphorm Inc. Buffer layer structures suited for III-nitride devices with foreign substrates
US9093366B2 (en) 2012-04-09 2015-07-28 Transphorm Inc. N-polar III-nitride transistors
US9184275B2 (en) 2012-06-27 2015-11-10 Transphorm Inc. Semiconductor devices with integrated hole collectors
US9147632B2 (en) 2012-08-24 2015-09-29 Rf Micro Devices, Inc. Semiconductor device having improved heat dissipation
US9917080B2 (en) * 2012-08-24 2018-03-13 Qorvo US. Inc. Semiconductor device with electrical overstress (EOS) protection
CN105164811B (en) 2013-02-15 2018-08-31 创世舫电子有限公司 Electrode of semiconductor devices and forming method thereof
US8928037B2 (en) 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer
US9087718B2 (en) 2013-03-13 2015-07-21 Transphorm Inc. Enhancement-mode III-nitride devices
US9245992B2 (en) 2013-03-15 2016-01-26 Transphorm Inc. Carbon doping semiconductor devices
WO2015009514A1 (en) 2013-07-19 2015-01-22 Transphorm Inc. Iii-nitride transistor including a p-type depleting layer
JP6241915B2 (en) * 2013-07-31 2017-12-06 住友電工デバイス・イノベーション株式会社 Manufacturing method of semiconductor device
US9318593B2 (en) 2014-07-21 2016-04-19 Transphorm Inc. Forming enhancement mode III-nitride devices
US9231064B1 (en) * 2014-08-12 2016-01-05 Raytheon Company Double heterojunction group III-nitride structures
US9536967B2 (en) 2014-12-16 2017-01-03 Transphorm Inc. Recessed ohmic contacts in a III-N device
US9536966B2 (en) 2014-12-16 2017-01-03 Transphorm Inc. Gate structures for III-N devices
JP6601938B2 (en) * 2015-01-22 2019-11-06 国立大学法人名古屋大学 Method for manufacturing group III nitride semiconductor device
US10062684B2 (en) 2015-02-04 2018-08-28 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US10615158B2 (en) 2015-02-04 2020-04-07 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US11322599B2 (en) 2016-01-15 2022-05-03 Transphorm Technology, Inc. Enhancement mode III-nitride devices having an Al1-xSixO gate insulator
US10224401B2 (en) 2016-05-31 2019-03-05 Transphorm Inc. III-nitride devices including a graded depleting layer
US10651306B2 (en) * 2017-08-25 2020-05-12 Hrl Laboratories, Llc Digital alloy based back barrier for P-channel nitride transistors
EP3673513A4 (en) * 2017-08-25 2021-04-07 HRL Laboratories, LLC Digital alloy based back barrier for p-channel nitride transistors
JP7074282B2 (en) * 2018-04-25 2022-05-24 住友電工デバイス・イノベーション株式会社 High electron mobility transistor
CN109346407A (en) * 2018-09-21 2019-02-15 张海涛 The manufacturing method of gallium nitride HEMT
CN111048586B (en) * 2018-10-11 2022-07-29 苏州能讯高能半导体有限公司 Semiconductor device and method for manufacturing the same
US10923585B2 (en) 2019-06-13 2021-02-16 Cree, Inc. High electron mobility transistors having improved contact spacing and/or improved contact vias
US10971612B2 (en) 2019-06-13 2021-04-06 Cree, Inc. High electron mobility transistors and power amplifiers including said transistors having improved performance and reliability
US11749758B1 (en) 2019-11-05 2023-09-05 Semiq Incorporated Silicon carbide junction barrier schottky diode with wave-shaped regions
US11469333B1 (en) 2020-02-19 2022-10-11 Semiq Incorporated Counter-doped silicon carbide Schottky barrier diode
US11837457B2 (en) 2020-09-11 2023-12-05 Wolfspeed, Inc. Packaging for RF transistor amplifiers
US11670605B2 (en) 2020-04-03 2023-06-06 Wolfspeed, Inc. RF amplifier devices including interconnect structures and methods of manufacturing
US20210313293A1 (en) 2020-04-03 2021-10-07 Cree, Inc. Rf amplifier devices and methods of manufacturing
US11356070B2 (en) 2020-06-01 2022-06-07 Wolfspeed, Inc. RF amplifiers having shielded transmission line structures
US11769768B2 (en) 2020-06-01 2023-09-26 Wolfspeed, Inc. Methods for pillar connection on frontside and passive device integration on backside of die
US11228287B2 (en) 2020-06-17 2022-01-18 Cree, Inc. Multi-stage decoupling networks integrated with on-package impedance matching networks for RF power amplifiers
US11533025B2 (en) 2020-06-18 2022-12-20 Wolfspeed, Inc. Integrated doherty amplifier with added isolation between the carrier and the peaking transistors
US11581859B2 (en) 2020-06-26 2023-02-14 Wolfspeed, Inc. Radio frequency (RF) transistor amplifier packages with improved isolation and lead configurations
US11887945B2 (en) 2020-09-30 2024-01-30 Wolfspeed, Inc. Semiconductor device with isolation and/or protection structures
US20220139852A1 (en) 2020-10-30 2022-05-05 Cree, Inc. Transistor packages with improved die attach
US20220157671A1 (en) 2020-11-13 2022-05-19 Cree, Inc. Packaged rf power device with pcb routing
US20220376085A1 (en) 2021-05-20 2022-11-24 Cree, Inc. Methods of manufacturing high electron mobility transistors having improved performance
US11842937B2 (en) 2021-07-30 2023-12-12 Wolfspeed, Inc. Encapsulation stack for improved humidity performance and related fabrication methods
US20230075505A1 (en) 2021-09-03 2023-03-09 Wolfspeed, Inc. Metal pillar connection topologies for heterogeneous packaging
US20230078017A1 (en) 2021-09-16 2023-03-16 Wolfspeed, Inc. Semiconductor device incorporating a substrate recess

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192987A (en) 1991-05-17 1993-03-09 Apa Optics, Inc. High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions
US6177685B1 (en) 1998-01-20 2001-01-23 Sharp Kabushiki Kaisha Nitride-type III-V HEMT having an InN 2DEG channel layer
US6316793B1 (en) 1998-06-12 2001-11-13 Cree, Inc. Nitride based transistors on semi-insulating silicon carbide substrates
WO2001092428A1 (en) 2000-06-02 2001-12-06 Erhard Kohn Heterostructure with rear-face donor doping
US20030218183A1 (en) * 2001-12-06 2003-11-27 Miroslav Micovic High power-low noise microwave GaN heterojunction field effet transistor

Family Cites Families (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2465317A2 (en) 1979-03-28 1981-03-20 Thomson Csf FIELD EFFECT TRANSISTOR WITH HIGH BREAKAGE FREQUENCY
DE3072175D1 (en) 1979-12-28 1990-04-26 Fujitsu Ltd SEMICONDUCTOR DEVICES WITH HETEROUITION.
JPH088350B2 (en) 1985-04-08 1996-01-29 日本電気株式会社 Semiconductor device
US4755867A (en) 1986-08-15 1988-07-05 American Telephone And Telegraph Company, At&T Bell Laboratories Vertical Enhancement-mode Group III-V compound MISFETs
US4788156A (en) 1986-09-24 1988-11-29 Microwave Technology, Inc. Subchannel doping to reduce short-gate effects in field effect transistors
US4866005A (en) 1987-10-26 1989-09-12 North Carolina State University Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide
US5411914A (en) 1988-02-19 1995-05-02 Massachusetts Institute Of Technology III-V based integrated circuits having low temperature growth buffer or passivation layers
EP0334006A1 (en) 1988-02-22 1989-09-27 Siemens Aktiengesellschaft Stacked channel heterojunction fet
US4946547A (en) 1989-10-13 1990-08-07 Cree Research, Inc. Method of preparing silicon carbide surfaces for crystal growth
US5053348A (en) 1989-12-01 1991-10-01 Hughes Aircraft Company Fabrication of self-aligned, t-gate hemt
US5210051A (en) 1990-03-27 1993-05-11 Cree Research, Inc. High efficiency light emitting diodes from bipolar gallium nitride
US5172197A (en) 1990-04-11 1992-12-15 Hughes Aircraft Company Hemt structure with passivated donor layer
US5200022A (en) 1990-10-03 1993-04-06 Cree Research, Inc. Method of improving mechanically prepared substrate surfaces of alpha silicon carbide for deposition of beta silicon carbide thereon and resulting product
JP3352712B2 (en) 1991-12-18 2002-12-03 浩 天野 Gallium nitride based semiconductor device and method of manufacturing the same
DE69202554T2 (en) 1991-12-25 1995-10-19 Nec Corp Tunnel transistor and its manufacturing process.
JPH05275463A (en) 1992-03-30 1993-10-22 Matsushita Electric Ind Co Ltd Semiconductor device
JPH05326561A (en) 1992-05-22 1993-12-10 Nec Corp Manufacture of field effect transistor
JPH06267991A (en) 1993-03-12 1994-09-22 Hitachi Ltd Semiconductor device and its manufacture
US5393993A (en) 1993-12-13 1995-02-28 Cree Research, Inc. Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices
US5686737A (en) 1994-09-16 1997-11-11 Cree Research, Inc. Self-aligned field-effect transistor for high frequency applications
US5523589A (en) 1994-09-20 1996-06-04 Cree Research, Inc. Vertical geometry light emitting diode with group III nitride active layer and extended lifetime
US5592501A (en) 1994-09-20 1997-01-07 Cree Research, Inc. Low-strain laser structures with group III nitride active layers
JP3157690B2 (en) 1995-01-19 2001-04-16 沖電気工業株式会社 Method for manufacturing pn junction element
US5534462A (en) 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
US5670798A (en) 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
SE9501311D0 (en) 1995-04-10 1995-04-10 Abb Research Ltd Method of producing a semiconductor device having a semiconductor layer of SiC
US6002148A (en) 1995-06-30 1999-12-14 Motorola, Inc. Silicon carbide transistor and method
EP0852416B1 (en) * 1995-09-18 2002-07-10 Hitachi, Ltd. Semiconductor material, method of producing the semiconductor material, and semiconductor device
KR100195269B1 (en) 1995-12-22 1999-06-15 윤종용 Manufacture method of liquid crystal display device
US5915164A (en) 1995-12-28 1999-06-22 U.S. Philips Corporation Methods of making high voltage GaN-A1N based semiconductor devices
DE19600116C2 (en) 1996-01-03 2001-03-15 Siemens Ag Double heterostructure HEMT
JPH1050982A (en) 1996-07-31 1998-02-20 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
US6936839B2 (en) 1996-10-16 2005-08-30 The University Of Connecticut Monolithic integrated circuit including a waveguide and quantum well inversion channel devices and a method of fabricating same
US6677619B1 (en) 1997-01-09 2004-01-13 Nichia Chemical Industries, Ltd. Nitride semiconductor device
US6448648B1 (en) 1997-03-27 2002-09-10 The United States Of America As Represented By The Secretary Of The Navy Metalization of electronic semiconductor devices
US6582392B1 (en) * 1998-05-01 2003-06-24 Ekos Corporation Ultrasound assembly for use with a catheter
JPH10335637A (en) 1997-05-30 1998-12-18 Sony Corp Hetero-junction field effect transistor
US6201262B1 (en) 1997-10-07 2001-03-13 Cree, Inc. Group III nitride photonic devices on silicon carbide substrates with conductive buffer interlay structure
US6608327B1 (en) 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
US6051849A (en) 1998-02-27 2000-04-18 North Carolina State University Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer
US6150680A (en) 1998-03-05 2000-11-21 Welch Allyn, Inc. Field effect semiconductor device having dipole barrier
JPH11261053A (en) 1998-03-09 1999-09-24 Furukawa Electric Co Ltd:The High electron mobility transistor
US6086673A (en) 1998-04-02 2000-07-11 Massachusetts Institute Of Technology Process for producing high-quality III-V nitride substrates
US6255198B1 (en) 1998-11-24 2001-07-03 North Carolina State University Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby
US6177688B1 (en) 1998-11-24 2001-01-23 North Carolina State University Pendeoepitaxial gallium nitride semiconductor layers on silcon carbide substrates
JP3209270B2 (en) 1999-01-29 2001-09-17 日本電気株式会社 Heterojunction field effect transistor
US6582906B1 (en) 1999-04-05 2003-06-24 Affymetrix, Inc. Proportional amplification of nucleic acids
US6518637B1 (en) 1999-04-08 2003-02-11 Wayne State University Cubic (zinc-blende) aluminum nitride
US6218680B1 (en) 1999-05-18 2001-04-17 Cree, Inc. Semi-insulating silicon carbide without vanadium domination
DE29912965U1 (en) * 1999-07-24 1999-09-16 Hoelzle Dieter Tech Projekte Injection device
US6812053B1 (en) 1999-10-14 2004-11-02 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
US6521514B1 (en) 1999-11-17 2003-02-18 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates
JP4592938B2 (en) 1999-12-08 2010-12-08 パナソニック株式会社 Semiconductor device
US6639255B2 (en) 1999-12-08 2003-10-28 Matsushita Electric Industrial Co., Ltd. GaN-based HFET having a surface-leakage reducing cap layer
US6380108B1 (en) 1999-12-21 2002-04-30 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby
JP3393602B2 (en) 2000-01-13 2003-04-07 松下電器産業株式会社 Semiconductor device
US6586781B2 (en) 2000-02-04 2003-07-01 Cree Lighting Company Group III nitride based FETs and HEMTs with reduced trapping and method for producing the same
US6403451B1 (en) 2000-02-09 2002-06-11 Noerh Carolina State University Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts
JP4667556B2 (en) 2000-02-18 2011-04-13 古河電気工業株式会社 Vertical GaN-based field effect transistor, bipolar transistor and vertical GaN-based field effect transistor manufacturing method
US6261929B1 (en) 2000-02-24 2001-07-17 North Carolina State University Methods of forming a plurality of semiconductor layers using spaced trench arrays
US6475889B1 (en) 2000-04-11 2002-11-05 Cree, Inc. Method of forming vias in silicon carbide and resulting devices and circuits
JP4022708B2 (en) 2000-06-29 2007-12-19 日本電気株式会社 Semiconductor device
US6515316B1 (en) 2000-07-14 2003-02-04 Trw Inc. Partially relaxed channel HEMT device
US6992319B2 (en) * 2000-07-18 2006-01-31 Epitaxial Technologies Ultra-linear multi-channel field effect transistor
JP2002164352A (en) * 2000-09-13 2002-06-07 Toshiba Corp Bipolar transistor, semiconductor light-emitting device, and semiconductor device
US6548333B2 (en) 2000-12-01 2003-04-15 Cree, Inc. Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
JP3428962B2 (en) 2000-12-19 2003-07-22 古河電気工業株式会社 GaN based high mobility transistor
US6593193B2 (en) 2001-02-27 2003-07-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US6849882B2 (en) 2001-05-11 2005-02-01 Cree Inc. Group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer
US6706114B2 (en) 2001-05-21 2004-03-16 Cree, Inc. Methods of fabricating silicon carbide crystals
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US7230284B2 (en) 2001-07-24 2007-06-12 Cree, Inc. Insulating gate AlGaN/GaN HEMT
JP2003133332A (en) * 2001-10-24 2003-05-09 Shin Etsu Handotai Co Ltd Compound semiconductor element
US7030428B2 (en) 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
JP3986887B2 (en) 2002-05-17 2007-10-03 松下電器産業株式会社 Semiconductor device
US6982204B2 (en) 2002-07-16 2006-01-03 Cree, Inc. Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
US6841001B2 (en) 2002-07-19 2005-01-11 Cree, Inc. Strain compensated semiconductor structures and methods of fabricating strain compensated semiconductor structures
US6884704B2 (en) 2002-08-05 2005-04-26 Hrl Laboratories, Llc Ohmic metal contact and channel protection in GaN devices using an encapsulation layer
US20040021152A1 (en) 2002-08-05 2004-02-05 Chanh Nguyen Ga/A1GaN Heterostructure Field Effect Transistor with dielectric recessed gate
JP4748498B2 (en) * 2002-12-05 2011-08-17 古河電気工業株式会社 GaN-based semiconductor device with current breaker
US6825559B2 (en) * 2003-01-02 2004-11-30 Cree, Inc. Group III nitride based flip-chip intergrated circuit and method for fabricating
JP4645034B2 (en) * 2003-02-06 2011-03-09 株式会社豊田中央研究所 Semiconductor device having group III nitride semiconductor
JP4746825B2 (en) 2003-05-15 2011-08-10 富士通株式会社 Compound semiconductor device
US7501669B2 (en) * 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192987A (en) 1991-05-17 1993-03-09 Apa Optics, Inc. High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions
US5296395A (en) 1991-05-17 1994-03-22 Apa Optics, Inc. Method of making a high electron mobility transistor
US6177685B1 (en) 1998-01-20 2001-01-23 Sharp Kabushiki Kaisha Nitride-type III-V HEMT having an InN 2DEG channel layer
US6316793B1 (en) 1998-06-12 2001-11-13 Cree, Inc. Nitride based transistors on semi-insulating silicon carbide substrates
WO2001092428A1 (en) 2000-06-02 2001-12-06 Erhard Kohn Heterostructure with rear-face donor doping
US20030218183A1 (en) * 2001-12-06 2003-11-27 Miroslav Micovic High power-low noise microwave GaN heterojunction field effet transistor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KONG Y C ET AL: "A novel InxGa1-xN/InN heterostructure field-effect transistor with extremely high two-dimensional electron-gas sheet density", SOLID STATE ELECTRONICS, ELSEVIER SCIENCE PUBLISHERS, BARKING, GB, vol. 49, no. 2, February 2005 (2005-02-01), pages 199 - 203, XP004645013, ISSN: 0038-1101 *
See also references of EP1875514A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11557668B2 (en) 2018-04-25 2023-01-17 Sumitomo Electric Device Innovations, Inc. High electron mobility transistor with reverse arrangement of channel layer and barrier layer

Also Published As

Publication number Publication date
TW200644246A (en) 2006-12-16
JP2008539586A (en) 2008-11-13
US7615774B2 (en) 2009-11-10
US20060244010A1 (en) 2006-11-02
EP1875514A1 (en) 2008-01-09

Similar Documents

Publication Publication Date Title
US7615774B2 (en) Aluminum free group III-nitride based high electron mobility transistors
EP1817798B2 (en) Cap layers and/or passivation layers for nitride-based transistors, transistor structures and methods of fabricating same
US7544963B2 (en) Binary group III-nitride based high electron mobility transistors
US8803198B2 (en) Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions
US20180233590A1 (en) Field effect transistor and multilayered epitaxial film for use in preparation of field effect transistor
US7105868B2 (en) High-electron mobility transistor with zinc oxide
EP1779437B1 (en) Nitride-based transistors having laterally grown active region and methods of fabricating same
JP5350585B2 (en) Nitride-based transistors for millimeter wave operation
US7960756B2 (en) Transistors including supported gate electrodes
KR101108344B1 (en) Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
EP1522091B1 (en) Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
US7388236B2 (en) High efficiency and/or high power density wide bandgap transistors
KR20070032701A (en) A method of manufacturing a nitride transistor having a regrown ohmic contact region and a nitride transistor having a regrown ohmic contact region
US7355215B2 (en) Field effect transistors (FETs) having multi-watt output power at millimeter-wave frequencies

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
REEP Request for entry into the european phase

Ref document number: 2006735699

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2006735699

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2008508832

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU