WO2006127485A3 - Method and system for incorporation of patterns and design rule checking - Google Patents

Method and system for incorporation of patterns and design rule checking Download PDF

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Publication number
WO2006127485A3
WO2006127485A3 PCT/US2006/019509 US2006019509W WO2006127485A3 WO 2006127485 A3 WO2006127485 A3 WO 2006127485A3 US 2006019509 W US2006019509 W US 2006019509W WO 2006127485 A3 WO2006127485 A3 WO 2006127485A3
Authority
WO
WIPO (PCT)
Prior art keywords
pattern library
patterns
design rules
incorporation
implementations
Prior art date
Application number
PCT/US2006/019509
Other languages
French (fr)
Other versions
WO2006127485A2 (en
Inventor
Louis K Scheffer
David C Noice
Original Assignee
Cadence Design Systems Inc
Louis K Scheffer
David C Noice
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc, Louis K Scheffer, David C Noice filed Critical Cadence Design Systems Inc
Publication of WO2006127485A2 publication Critical patent/WO2006127485A2/en
Publication of WO2006127485A3 publication Critical patent/WO2006127485A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes 'known good' patterns, which chip fabricators know from experience are successful, and 'known bad' patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.
PCT/US2006/019509 2005-05-20 2006-05-19 Method and system for incorporation of patterns and design rule checking WO2006127485A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68336705P 2005-05-20 2005-05-20
US60/683,367 2005-05-20

Publications (2)

Publication Number Publication Date
WO2006127485A2 WO2006127485A2 (en) 2006-11-30
WO2006127485A3 true WO2006127485A3 (en) 2007-06-21

Family

ID=36992686

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/019509 WO2006127485A2 (en) 2005-05-20 2006-05-19 Method and system for incorporation of patterns and design rule checking

Country Status (2)

Country Link
US (1) US8136056B2 (en)
WO (1) WO2006127485A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8578313B2 (en) * 2008-04-24 2013-11-05 Synopsys, Inc. Pattern-clip-based hotspot database system for layout verification
US20110047519A1 (en) * 2009-05-11 2011-02-24 Juan Andres Torres Robles Layout Content Analysis for Source Mask Optimization Acceleration
US20110067059A1 (en) * 2009-09-15 2011-03-17 At&T Intellectual Property I, L.P. Media control
US8516406B1 (en) * 2010-06-12 2013-08-20 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
WO2012034044A2 (en) * 2010-09-11 2012-03-15 Social Communications Company Relationship based presence indicating in virtual area contexts
US8849472B2 (en) * 2011-02-02 2014-09-30 Inscope Energy, Llc Effectuating energization and deactivation of particular circuits through rules-based smart nodes
US8832621B1 (en) 2011-11-28 2014-09-09 Cadence Design Systems, Inc. Topology design using squish patterns
US8799836B1 (en) 2013-07-08 2014-08-05 International Business Machines Corporation Yield optimization for design library elements at library element level or at product level
US9870441B1 (en) 2013-10-04 2018-01-16 Pdf Solutions, Inc. Snap-to valid pattern system and method
US10783311B2 (en) * 2016-10-31 2020-09-22 Synopsys, Inc. DRC processing tool for early stage IC layout designs
US10565344B1 (en) 2017-12-01 2020-02-18 Pdf Solutions, Inc. Standard cell design conformance using boolean assertions
US20190266310A1 (en) * 2018-02-26 2019-08-29 Globalfoundries Inc. Rule check structures

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030115569A1 (en) * 2001-11-26 2003-06-19 Atsuhiko Ikeuchi Method and system for optical proximity correction

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2806831B2 (en) * 1995-07-28 1998-09-30 日本電気アイシーマイコンシステム株式会社 Method of checking design rules for semiconductor integrated circuits
US6782524B2 (en) * 1999-09-22 2004-08-24 Dupont Photomasks, Inc. Photomask and integrated circuit manufactured by automatically correcting design rule violations in a mask layout file
US6584455B1 (en) * 1999-12-14 2003-06-24 International Business Machines Corporation System and method for predicting design errors in integrated circuits
US6507930B1 (en) * 2000-06-30 2003-01-14 International Business Machines Corporation Method and system for improving yield of semiconductor integrated circuits
US7152215B2 (en) 2002-06-07 2006-12-19 Praesagus, Inc. Dummy fill for integrated circuits
US7124386B2 (en) 2002-06-07 2006-10-17 Praesagus, Inc. Dummy fill for integrated circuits
US7774726B2 (en) 2002-06-07 2010-08-10 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7853904B2 (en) 2002-06-07 2010-12-14 Cadence Design Systems, Inc. Method and system for handling process related variations for integrated circuits based upon reflections
EP1532670A4 (en) 2002-06-07 2007-09-12 Praesagus Inc Characterization adn reduction of variation for integrated circuits
US20030229875A1 (en) 2002-06-07 2003-12-11 Smith Taber H. Use of models in integrated circuit fabrication
US7393755B2 (en) 2002-06-07 2008-07-01 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7363099B2 (en) 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US7234128B2 (en) * 2003-10-03 2007-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving the critical dimension uniformity of patterned features on wafers
US7653890B2 (en) * 2004-04-02 2010-01-26 Cadence Design Systems, Inc. Modeling resolution enhancement processes in integrated circuit fabrication
US7284214B2 (en) * 2004-10-22 2007-10-16 Mentor Graphics Corporation In-line XOR checking of master cells during integrated circuit design rule checking
US7814447B2 (en) 2006-12-29 2010-10-12 Cadence Design Systems, Inc. Supplant design rules in electronic designs
US7962866B2 (en) 2006-12-29 2011-06-14 Cadence Design Systems, Inc. Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs
US20080162103A1 (en) 2006-12-29 2008-07-03 Cadence Design Systems, Inc. Method, system, and computer program product for concurrent model aided electronic design automation
US7937674B2 (en) 2006-12-29 2011-05-03 Cadence Design Systems, Inc. Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designs
US7827519B2 (en) 2006-12-29 2010-11-02 Cadence Design Systems, Inc. Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
US7721237B2 (en) 2006-12-29 2010-05-18 Cadence Design Systems, Inc. Method, system, and computer program product for timing closure in electronic designs
US7861203B2 (en) 2006-12-29 2010-12-28 Cadence Design Systems, Inc. Method and system for model-based routing of an integrated circuit
CN101785011A (en) 2007-06-27 2010-07-21 凯迪斯设计系统公司 Utilize the robust designs of manufacturability models

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030115569A1 (en) * 2001-11-26 2003-06-19 Atsuhiko Ikeuchi Method and system for optical proximity correction

Also Published As

Publication number Publication date
US8136056B2 (en) 2012-03-13
WO2006127485A2 (en) 2006-11-30
US20070006114A1 (en) 2007-01-04

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