WO2006136845A3 - Integrated circuit routing and compaction - Google Patents

Integrated circuit routing and compaction Download PDF

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Publication number
WO2006136845A3
WO2006136845A3 PCT/GB2006/002311 GB2006002311W WO2006136845A3 WO 2006136845 A3 WO2006136845 A3 WO 2006136845A3 GB 2006002311 W GB2006002311 W GB 2006002311W WO 2006136845 A3 WO2006136845 A3 WO 2006136845A3
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WO
WIPO (PCT)
Prior art keywords
nets
integrated circuit
rows
compaction
channel
Prior art date
Application number
PCT/GB2006/002311
Other languages
French (fr)
Other versions
WO2006136845A2 (en
Inventor
Mark Waller
Original Assignee
Pulsic Ltd
Mark Waller
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pulsic Ltd, Mark Waller filed Critical Pulsic Ltd
Publication of WO2006136845A2 publication Critical patent/WO2006136845A2/en
Publication of WO2006136845A3 publication Critical patent/WO2006136845A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An iterative technique (401) is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel (405) , which are gaps between the rows, the technique determines which nets should be routed in which areas (408) . Spine routing is used for nets than span more than one row or channel (411) . The space is altered between rows, larger or smaller, which will allow routing of the nets .
PCT/GB2006/002311 2005-06-24 2006-06-23 Integrated circuit routing and compaction WO2006136845A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US59535105P 2005-06-24 2005-06-24
US60/595,351 2005-06-24
US11/425,828 US7603644B2 (en) 2005-06-24 2006-06-22 Integrated circuit routing and compaction
US11/425,828 2006-06-22

Publications (2)

Publication Number Publication Date
WO2006136845A2 WO2006136845A2 (en) 2006-12-28
WO2006136845A3 true WO2006136845A3 (en) 2007-04-19

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PCT/GB2006/002311 WO2006136845A2 (en) 2005-06-24 2006-06-23 Integrated circuit routing and compaction

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US (4) US7603644B2 (en)
WO (1) WO2006136845A2 (en)

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Also Published As

Publication number Publication date
US20130104095A1 (en) 2013-04-25
US8707239B2 (en) 2014-04-22
WO2006136845A2 (en) 2006-12-28
US20110276937A1 (en) 2011-11-10
US7603644B2 (en) 2009-10-13
US20060294488A1 (en) 2006-12-28
US7984411B2 (en) 2011-07-19
US8332799B2 (en) 2012-12-11
US20090327990A1 (en) 2009-12-31

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