WO2006138086A3 - Non-volatile two-transistor programmable logic cell and array layout - Google Patents

Non-volatile two-transistor programmable logic cell and array layout Download PDF

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Publication number
WO2006138086A3
WO2006138086A3 PCT/US2006/021569 US2006021569W WO2006138086A3 WO 2006138086 A3 WO2006138086 A3 WO 2006138086A3 US 2006021569 W US2006021569 W US 2006021569W WO 2006138086 A3 WO2006138086 A3 WO 2006138086A3
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
memory
switch
volatile
drain regions
Prior art date
Application number
PCT/US2006/021569
Other languages
French (fr)
Other versions
WO2006138086A2 (en
Inventor
Fethi Dhaoui
John Mccollum
Vidyadhara Bellippady
Zhigang Wang
Original Assignee
Actel Corp
Fethi Dhaoui
John Mccollum
Vidyadhara Bellippady
Zhigang Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Actel Corp, Fethi Dhaoui, John Mccollum, Vidyadhara Bellippady, Zhigang Wang filed Critical Actel Corp
Priority to EP06772035A priority Critical patent/EP1889299A4/en
Priority to JP2008516919A priority patent/JP2008547198A/en
Publication of WO2006138086A2 publication Critical patent/WO2006138086A2/en
Publication of WO2006138086A3 publication Critical patent/WO2006138086A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Abstract

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch- transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
PCT/US2006/021569 2005-06-15 2006-06-01 Non-volatile two-transistor programmable logic cell and array layout WO2006138086A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06772035A EP1889299A4 (en) 2005-06-15 2006-06-01 Non-volatile two-transistor programmable logic cell and array layout
JP2008516919A JP2008547198A (en) 2005-06-15 2006-06-01 Non-volatile, two-transistor programmable logic cell and array layout

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/155,005 US7285818B2 (en) 2005-06-15 2005-06-15 Non-volatile two-transistor programmable logic cell and array layout
US11/155,005 2005-06-15

Publications (2)

Publication Number Publication Date
WO2006138086A2 WO2006138086A2 (en) 2006-12-28
WO2006138086A3 true WO2006138086A3 (en) 2009-04-30

Family

ID=37570957

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/021569 WO2006138086A2 (en) 2005-06-15 2006-06-01 Non-volatile two-transistor programmable logic cell and array layout

Country Status (4)

Country Link
US (6) US7285818B2 (en)
EP (1) EP1889299A4 (en)
JP (1) JP2008547198A (en)
WO (1) WO2006138086A2 (en)

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US7368789B1 (en) * 2005-06-13 2008-05-06 Actel Corporation Non-volatile programmable memory cell and array for programmable logic array
US7538379B1 (en) 2005-06-15 2009-05-26 Actel Corporation Non-volatile two-transistor programmable logic cell and array layout
US7285818B2 (en) * 2005-06-15 2007-10-23 Actel Corporation Non-volatile two-transistor programmable logic cell and array layout
US7495279B2 (en) * 2005-09-09 2009-02-24 Infineon Technologies Ag Embedded flash memory devices on SOI substrates and methods of manufacture thereof
US7808055B2 (en) * 2007-06-21 2010-10-05 Gigadevice Semiconductor Inc. Methods and apparatus for semiconductor memory devices manufacturable using bulk CMOS process manufacturing
US9530495B1 (en) * 2015-08-05 2016-12-27 Adesto Technologies Corporation Resistive switching memory having a resistor, diode, and switch memory cell
US9922973B1 (en) * 2017-06-01 2018-03-20 Globalfoundries Inc. Switches with deep trench depletion and isolation structures

Citations (1)

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US20040233736A1 (en) * 2003-04-10 2004-11-25 Stmicroelectronics S.R.L. Nonvolatile switch, in particular for high-density nonvolatile programmable-logic devices

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US5587603A (en) * 1995-01-06 1996-12-24 Actel Corporation Two-transistor zero-power electrically-alterable non-volatile latch
US5625211A (en) * 1995-01-12 1997-04-29 Actel Corporation Two-transistor electrically-alterable switch employing hot electron injection and fowler nordheim tunneling
US5740106A (en) * 1995-06-29 1998-04-14 Cypress Semiconductor Corp. Apparatus and method for nonvolatile configuration circuit
US5640344A (en) * 1995-07-25 1997-06-17 Btr, Inc. Programmable non-volatile bidirectional switch for programmable logic
US5633518A (en) * 1995-07-28 1997-05-27 Zycad Corporation Nonvolatile reprogrammable interconnect cell with FN tunneling and programming method thereof
US6252273B1 (en) * 1996-08-09 2001-06-26 Actel Corporation Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase
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US5847993A (en) * 1997-06-23 1998-12-08 Xilinx, Inc. Non-volatile programmable CMOS logic cell and method of operating same
JP3951443B2 (en) * 1997-09-02 2007-08-01 ソニー株式会社 Nonvolatile semiconductor memory device and writing method thereof
US6114724A (en) * 1998-03-31 2000-09-05 Cypress Semiconductor Corporation Nonvolatile semiconductor memory cell with select gate
JP3123646B2 (en) * 1998-06-18 2001-01-15 日本電気株式会社 Nonvolatile semiconductor memory device and method for extracting electrons therefrom
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Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US20040233736A1 (en) * 2003-04-10 2004-11-25 Stmicroelectronics S.R.L. Nonvolatile switch, in particular for high-density nonvolatile programmable-logic devices

Also Published As

Publication number Publication date
US7342278B2 (en) 2008-03-11
EP1889299A4 (en) 2010-06-09
EP1889299A2 (en) 2008-02-20
US7898018B2 (en) 2011-03-01
US20080093654A1 (en) 2008-04-24
US20110147821A1 (en) 2011-06-23
JP2008547198A (en) 2008-12-25
US7285818B2 (en) 2007-10-23
US20060284238A1 (en) 2006-12-21
US20070215935A1 (en) 2007-09-20
WO2006138086A2 (en) 2006-12-28
US20090159954A1 (en) 2009-06-25
US7473960B1 (en) 2009-01-06
US7501681B2 (en) 2009-03-10
US8258567B2 (en) 2012-09-04

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