WO2007002938A1 - Policy table rule based processor side bus signaling - Google Patents
Policy table rule based processor side bus signaling Download PDFInfo
- Publication number
- WO2007002938A1 WO2007002938A1 PCT/US2006/025945 US2006025945W WO2007002938A1 WO 2007002938 A1 WO2007002938 A1 WO 2007002938A1 US 2006025945 W US2006025945 W US 2006025945W WO 2007002938 A1 WO2007002938 A1 WO 2007002938A1
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- WIPO (PCT)
- Prior art keywords
- computer hardware
- signal
- action
- course
- instructions
- Prior art date
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
- G06F1/206—Cooling means comprising thermal management
Definitions
- Embodiments of the invention pertain to cooling systems for computer systems. More particularly, embodiments of the invention pertain to throttling a component of a computer system based on a criterion.
- Such damage may include the warping of the electrical components and possible fire hazards.
- thermal sensors are attached to a die to read the actual temperature of the die hot spots.
- that die reduces its temperature independently of the other die using some form of reduction in work per unit time, also called throttling.
- This throttling prevents a die from reaching its maximum working temperature and damaging the system. Throttling may be performed by clock gating and clock frequency reduction.
- the throttling may be triggered if the thermal sensors read a throttling threshold temperature up to some maximum tolerable temperature. To ensure safety, this maximum temperature may be set well below a temperature that causes actual catastrophic damage.
- Throttling and performance scaling will reduce the amount of work performed by the die to a level below its peak potential. This action is necessary to keep the die operating at a temperature within its specified limits when adversely influenced by an elevated temperature of the environment in which it is operating.
- FIG. 1 illustrates one embodiment of a cooling system according to the present invention.
- Figure 2 illustrates one embodiment of a computing system according to the present invention.
- Figure 3 illustrates in a flowchart one embodiment of a method for using a co-thermal control system 213 to determine a proportional response to a thermal condition according to the present invention.
- Figure 4 illustrates a co-thermal controller with a table based rule generator according to one embodiment of the present invention.
- Figure 5 illustrates in a flowchart a method to determine a proportional response by the system according to one embodiment of the present invention.
- Figure 6 illustrates one embodiment of a table to be used by the table- based rule generator in determining a response to a Processor Hot (PROCHOT) signal according to one embodiment of the present invention.
- Figure 7 illustrates in a flowchart one embodiment of a method to determine a proportional response to a PROCHOT signal according to one embodiment of the present invention.
- a system and method for selecting a computer hardware component (CHC) of a computing system to throttle based on a selection policy is disclosed.
- a co-thermal control (CTC) system may receive a first signal indicating a first thermal condition for a plurality of CHCs has occurred.
- the CTC system may choose a course of action at least partially based upon the first signal using a table-based rule generator.
- the CTC system may output instructions for the course of action.
- the first signal may be a sensor signal and the course of action may be to send a second signal from a first CHC to a second CHC to throttle the second CHC a proportional amount.
- the first signal may be a Processor Hot (PROCHOT) signal to the first CHC and the course of action may be to throttle the first CHC a proportional amount (e.g. , reducing the internal clocking signal by 50%).
- the first signal may be weighted before being input into the table-based rule generator.
- the instructions from the table-based rule generator may be weighted.
- the instructions for the course of action may be further based upon at least one of a state of one of the plurality of CHCs, a power condition, a utilization condition, or a temperature condition.
- FIG. 1 illustrates one embodiment of a co-thermal control (CTC) system
- the CTC system may throttle 130 the power consumption of the CHCs such as CPU 140 and the graphics memory and controller hub (GMCH) 150.
- the throttling 130 of one of the CHCs may take the throttling 130 of the other
- Power, utilization, or temperature information from a first thermal sensor 160 connected to the output of a first CHC and a second thermal sensor 170 connected to the output of a second CHC may be subtracted from the power, utilization, or temperature budget 120 to determine the error 110.
- FIG. 2 illustrates one embodiment of a computing system 200 according to the present invention.
- a first computer hardware component such as a CPU 210
- a second computer hardware component such as a GMCH 220
- FFB front side bus
- this description will refer specifically to a CPU and a GMCH, it is to be understood that other components may also be used.
- the CHC may also be a CPU memory controller hub.
- the system is not limited to just two computer hardware components, as multiple computer hardware components may be interacting within the system.
- the CPU 210 and the GMCH 220 share a cooling system 240.
- This cooling system 240 may take one of any number of forms known in the art, such as air circulation units, heat exchangers, or other systems. While the cooling system 240 should be able to handle the sum of the thermal design power (TDP) of both the CPU 210 and the GMCH 220 in most computing systems, in some computing systems this is not the case for various reasons.
- the TDP for a component is defined as the steady state power for which a thermal solution for that component should be designed so that the component will not exceed any reliability temperature threshold, and is generally quoted at a specific ambient temperature.
- the maximum power for the CPU 210 and GMCH 220 may be more than the TDP of each device. Since the maximum power is more than
- the minimum residual GMCH thermal power budget is the power available to the GMCH 220 when the CPU 210 is at its maximum operating power in steady state.
- the minimum residual CPU thermal power budget is the power available to the CPU 210 when the GMCH 220 is at its maximum operating power in steady state.
- the CPU 210 has a microprocessor 211 to process software instructions.
- the CPU 210 may have a thermal sensor 212 to detect when the CPU 210 is getting too hot.
- the thermal sensor 212 may alert a CPU CTC system 213, which may contain throttling control logic to control CPU throttling hardware 214.
- the CPU CTC system 213 may also control communications between the CPU 210 and the GMCH 220 that pertain to the thermal condition of the system.
- the throttling hardware 214 may then reduce the amount of processing being performed by the microprocessor.
- a graphics driver 215 may be used to interact with the GMCH 220 via the FSB 230. Messages may be transmitted via the FSB 230 using the message protocol 216.
- the GMCH 220 may have a graphics engine 221 to execute graphics processing.
- the GMCH 220 may have a thermal sensor 222 to detect when the GMCH 220 is getting too hot.
- the thermal sensor 222 may alert a GMCH CTC system 223, which may contain throttling control logic to control GMCH throttling hardware 224.
- the GMCH CTC system 223 may also control communications between the CPU 210 and the GMCH 220 that pertain to the thermal
- the CTC system may be integrated with either the CPU 210, the GMCH 220, both, or as a separate component.
- the throttling hardware 224 may then reduce the amount of graphics execution being performed by the microprocessor. Messages may be transmitted via the FSB 230 using the message protocol 225.
- the CPU 210 may have a pin 250, such as a PROCHOT pin, which receives a signal from the GMCH 220.
- the CPU CTC system 213 may cause the CPU throttling hardware 214 to throttle the microprocessor 211.
- the GMCH 220 may also have a PROCHOT pin 260, which receives a signal from the CPU 210.
- FIG. 3 illustrates in a flowchart one embodiment of a method 300 for using a CTC system 223 to determine a proportional response to a thermal condition according to the present invention.
- the CTC system 223 may receive a first signal indicating the thermal condition for a plurality of CHCs (Block 310).
- the thermal condition may be that either the temperature or the power has exceeded its budget or other conditions.
- the CTC system 223 may then choose a course of action using a table-based rule generator (Block 320).
- the CTC system 223 may then output instructions for that course of action (Block 330).
- Figure 4 illustrates one embodiment of a CTC system 400 with a table based rule generator.
- a rule or decision table 410 may be used to determine what course of action should be taken in response to the state of two or more CHCs.
- the CHCs may be a CPU, a GMCH, a
- the two or more CHCs may input the temperature 420, the power 430 or a different thermal characteristic.
- the temperature may be further divided into the average temperature 422, the temperature differential over time 424, or the temperature integral over time 426.
- the power may be further divided into the average power 432, the power differential over time 434, and the power integral over time 436.
- the table 410 may output 440 instructions designating a course of action, either to the first CHC 450 or the second CHC 460. While a first CHC 450 and a second CHC 460 are described in this example, the table 410 may proscribe a course of action in any number of CHCs.
- the state and the utilization of the plurality of CHCs may be another factor in the table. For example, if the CPU is in a more active state than the GMCH because a more processing intense activity is being executed, then the table may factor that into determining which CHC is throttled.
- the temperature input 420 and the power input may be weighted by an input weighting unit 470 before being sent to the table 410.
- the input weighting unit 470 allows an analog input to be more accurately placed in the table. For example, if an input may range from a value of 0 to 3, any input between 0 and 1 is weighted as low, any input between 1 and 2 is weighted as medium, and any input between 2 and 3 is weighted as high.
- the output 440 may be weighted by an output weighting unit 480 before being sent to the first CHC 450 or the second CHC 460.
- the output weighting may be calibrated to more accurately induce a selected CHC to perform the action dictated by the table 410.
- the first CHC 450 may throttle its performance a medium amount in reaction to an output value of 2 while the second CHC 460 may throttle its performance a medium amount in reaction to an output value of 4.
- an output 440 from the table 410 in the medium range would be converted by the weighting for the first CHC 450 into a output value of 2 and by the weighting for the second CHC into an output value of 4.
- FIG. 5 illustrates in a flowchart one embodiment of a method 500 to determine a proportional response by the system.
- the CTC system 223 receives input from the thermal sensor 222 (Block 510).
- the thermal sensor input is weighted (Block 520).
- the CTC system 223 chooses a course of action using the table-based rule generator 410 (Block 530).
- the table-based rule generator 410 outputs a throttling instruction (Block 540).
- the throttling instruction is weighted (Block 550).
- the throttling instruction is then transmitted to the designated CHC (Block 560).
- the CTC system may also be used to prevent a CHC from being taken over by another component.
- Figure 6 illustrates one embodiment of a table 600 to be used by the table-based rule generator in determining a response to a Processor Hot (PROCHOT) signal.
- the table-based rule generator resides on a CTC system in a CHC, in this instance the CPU.
- the CHCs may be a CPU, a GMCH, or a CPU memory controller hub.
- the PROCHOT signal 610 may be asserted or not asserted.
- a power sensor may input the average power 620, the power differential over time 630, and the power integral over time 640. Additionally or alternatively, other thermal information, such as the temperature, or the state of the two or more CHCs may be other factors in the table.
- the table may process these factors and determine which level of throttling 650 is performed on the CPU, or other CHC.
- FIG. 7 illustrates in a flowchart one embodiment of a method 700 to determine a proportional response to a PROCHOT signal. While a first CHC and a second CHC are described in this example, the CTC system 213 may proscribe a course of action in any number of CHCs.
- the CTC system 213 in the first CHC (CHCl) may receive a PROCHOT signal (Block 710).
- the CTC system 213 may then receive state data for the CHCl and the second CHC (CHC2) (Block 720).
- the CTC system 213 may then receive thermal data, such as power and temperature, for CHCl and CHC2 (Block 730).
- the CTC system 213 may then pick a throttling rule (Block 740).
- the CTC system 213 may then output a throttling rule to the CHCl (Block 750), which then throttles its execution unit at a level proportionate to the throttling rule.
- Embodiments of the present invention also relate to apparatus for performing the operations herein.
- This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
- a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, compact disk-read only memories (CD-ROMs), and magnetic- optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read only memories (EPROMs), electronically erasable programmable read only memories (EEPROMs), magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus. Instructions are executable using one or more devices (e.g., central processing units, etc.). In other embodiments, operations of the present invention
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112006001637.7T DE112006001637B4 (en) | 2005-06-29 | 2006-06-29 | Tabular-based processor side-bus signaling |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/172,113 US7415625B2 (en) | 2005-06-29 | 2005-06-29 | Policy table rule based processor side bus signaling |
US11/172,113 | 2005-06-29 |
Publications (1)
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WO2007002938A1 true WO2007002938A1 (en) | 2007-01-04 |
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Family Applications (1)
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PCT/US2006/025945 WO2007002938A1 (en) | 2005-06-29 | 2006-06-29 | Policy table rule based processor side bus signaling |
Country Status (4)
Country | Link |
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US (1) | US7415625B2 (en) |
DE (1) | DE112006001637B4 (en) |
TW (1) | TWI331279B (en) |
WO (1) | WO2007002938A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8930724B2 (en) * | 2011-08-17 | 2015-01-06 | Broadcom Corporation | Semiconductor device predictive dynamic thermal management |
KR102211126B1 (en) | 2014-04-17 | 2021-02-02 | 삼성전자주식회사 | Memory System controlling an operation performance and Operating Method thereof |
US9846541B2 (en) * | 2014-12-11 | 2017-12-19 | Toshiba Memory Corporation | Memory system for controlling perforamce by adjusting amount of parallel operations |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US6470289B1 (en) * | 1999-08-05 | 2002-10-22 | Compaq Information Technologies Group, L.P. | Independently controlling passive and active cooling in a computer system |
US20030050714A1 (en) * | 2001-09-10 | 2003-03-13 | Tymchenko Viktor Andrew | Apparatus, method and computer system for reducing power consumption of a processor or processors upon occurrence of a failure condition affecting the processor or processors |
WO2003079170A2 (en) * | 2002-03-15 | 2003-09-25 | Intel Corporation (A Delaware Corporation) | Processor temperature control interface |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5752011A (en) * | 1994-06-20 | 1998-05-12 | Thomas; C. Douglas | Method and system for controlling a processor's clock frequency in accordance with the processor's temperature |
US6311287B1 (en) * | 1994-10-11 | 2001-10-30 | Compaq Computer Corporation | Variable frequency clock control for microprocessor-based computer systems |
US6029119A (en) * | 1996-01-16 | 2000-02-22 | Compaq Computer Corporation | Thermal management of computers |
US6535798B1 (en) * | 1998-12-03 | 2003-03-18 | Intel Corporation | Thermal management in a system |
US7058824B2 (en) * | 2001-06-15 | 2006-06-06 | Microsoft Corporation | Method and system for using idle threads to adaptively throttle a computer |
CN1949117A (en) * | 2005-10-11 | 2007-04-18 | 鸿富锦精密工业(深圳)有限公司 | Fan speed controlling system and method |
-
2005
- 2005-06-29 US US11/172,113 patent/US7415625B2/en active Active
-
2006
- 2006-06-29 TW TW095123630A patent/TWI331279B/en not_active IP Right Cessation
- 2006-06-29 DE DE112006001637.7T patent/DE112006001637B4/en not_active Expired - Fee Related
- 2006-06-29 WO PCT/US2006/025945 patent/WO2007002938A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6470289B1 (en) * | 1999-08-05 | 2002-10-22 | Compaq Information Technologies Group, L.P. | Independently controlling passive and active cooling in a computer system |
US20030050714A1 (en) * | 2001-09-10 | 2003-03-13 | Tymchenko Viktor Andrew | Apparatus, method and computer system for reducing power consumption of a processor or processors upon occurrence of a failure condition affecting the processor or processors |
WO2003079170A2 (en) * | 2002-03-15 | 2003-09-25 | Intel Corporation (A Delaware Corporation) | Processor temperature control interface |
Also Published As
Publication number | Publication date |
---|---|
DE112006001637T5 (en) | 2008-05-08 |
TWI331279B (en) | 2010-10-01 |
US7415625B2 (en) | 2008-08-19 |
DE112006001637B4 (en) | 2016-06-09 |
US20070006005A1 (en) | 2007-01-04 |
TW200720916A (en) | 2007-06-01 |
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