WO2007005706A3 - Encrypted jtag interface - Google Patents

Encrypted jtag interface Download PDF

Info

Publication number
WO2007005706A3
WO2007005706A3 PCT/US2006/025762 US2006025762W WO2007005706A3 WO 2007005706 A3 WO2007005706 A3 WO 2007005706A3 US 2006025762 W US2006025762 W US 2006025762W WO 2007005706 A3 WO2007005706 A3 WO 2007005706A3
Authority
WO
WIPO (PCT)
Prior art keywords
line
test
jtag
debug
debug interface
Prior art date
Application number
PCT/US2006/025762
Other languages
French (fr)
Other versions
WO2007005706A2 (en
Inventor
Edwin D Cruzado
Brian R Bernier
William J Dalzell
Original Assignee
Honeywell Int Inc
Edwin D Cruzado
Brian R Bernier
William J Dalzell
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Int Inc, Edwin D Cruzado, Brian R Bernier, William J Dalzell filed Critical Honeywell Int Inc
Priority to EP06774400A priority Critical patent/EP1896948A2/en
Publication of WO2007005706A2 publication Critical patent/WO2007005706A2/en
Publication of WO2007005706A3 publication Critical patent/WO2007005706A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0894—Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
    • H04L9/0897—Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage involving additional devices, e.g. trusted platform module [TPM], smartcard or USB
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2151—Time stamp

Abstract

In one embodiment, a system comprises JTAG functionality that implements at least a portion of a JTAG protocol. The JTAG functionality supports a test data in (TDI) line, a test data out (TDO) line, a test rest (TR) line, a test mode state (TMS) line, and a test clock (TCLK) line. The system further comprises a debug interface to communicatively couple the system to a debug device external to the system. The debug interface comprises a transmit (TX) line, receive (RX) line, and a clock (CLK) line. The system transmits data output by the JTAG functionality on the TDI input on the RX line of the debug interface and receives data from the debug device on the TX line of the debug interface and provides the received data to the JTAG functionality on the TDO line, TR line and the TMS line.
PCT/US2006/025762 2005-06-30 2006-06-29 Encrypted jtag interface WO2007005706A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06774400A EP1896948A2 (en) 2005-06-30 2006-06-29 Encrypted jtag interface

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US69561305P 2005-06-30 2005-06-30
US60/695,613 2005-06-30
US11/266,792 US7961885B2 (en) 2005-04-20 2005-11-04 Encrypted JTAG interface
US11/266,792 2005-11-04

Publications (2)

Publication Number Publication Date
WO2007005706A2 WO2007005706A2 (en) 2007-01-11
WO2007005706A3 true WO2007005706A3 (en) 2007-05-03

Family

ID=37605077

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/025762 WO2007005706A2 (en) 2005-06-30 2006-06-29 Encrypted jtag interface

Country Status (3)

Country Link
US (1) US7961885B2 (en)
EP (1) EP1896948A2 (en)
WO (1) WO2007005706A2 (en)

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EP1276033B1 (en) * 2001-07-10 2012-03-14 Trident Microsystems (Far East) Ltd. Memory device with data protection in a processor
GB0526448D0 (en) * 2005-12-23 2006-02-08 Advanced Risc Mach Ltd Diagnostic mode switching
US7925896B2 (en) * 2006-03-30 2011-04-12 Texas Instruments Incorporated Hardware key encryption for data scrambling
US8099629B2 (en) * 2006-07-14 2012-01-17 Marvell World Trade Ltd. System-on-a-chip (SoC) test interface security
GB0615392D0 (en) * 2006-08-03 2006-09-13 Wivenhoe Technology Ltd Pseudo random number circuitry
US8627079B2 (en) 2007-11-01 2014-01-07 Infineon Technologies Ag Method and system for controlling a device
US8908870B2 (en) * 2007-11-01 2014-12-09 Infineon Technologies Ag Method and system for transferring information to a device
US9141776B2 (en) 2008-04-30 2015-09-22 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for secure hardware analysis
US8484451B2 (en) * 2010-03-11 2013-07-09 St-Ericsson Sa Method and apparatus for software boot revocation
DE102012219112A1 (en) 2012-10-19 2014-04-24 Siemens Aktiengesellschaft Use of a PUF for checking an authentication, in particular for protection against unauthorized access to a function of an IC or control unit
FR2998209B1 (en) 2012-11-19 2015-05-22 Hexcel Reinforcements METHOD FOR DEPOSITING AN INTERMEDIATE MATERIAL FOR ENSURING COHESION THEREOF AND METHOD FOR ESTABLISHING A STACK FOR THE MANUFACTURE OF COMPOSITE PARTS
US9172380B2 (en) * 2013-07-04 2015-10-27 Samsung Electronics Co., Ltd. Method and apparatus for supporting self-destruction function in baseband modem
US20150178184A1 (en) * 2013-12-19 2015-06-25 International Business Machines Corporation Test management using distributed computing
GB2531770A (en) * 2014-10-30 2016-05-04 Ibm Confidential Extracting System Internal Data
CN111886585B (en) * 2018-03-27 2022-12-13 华为技术有限公司 Terminal device, debugging card and debugging method
CN113722732B (en) * 2021-08-26 2024-02-23 安徽敏矽微电子有限公司 2-line on-chip debugging encryption and decryption safety protection system

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EP0806737A2 (en) * 1996-05-08 1997-11-12 Lattice Semiconductor Corporation In-system programming with two wire interface
WO2002071231A1 (en) * 2001-02-15 2002-09-12 Nokia Corporation Method and arrangement for protecting information
WO2004056031A2 (en) * 2002-12-18 2004-07-01 Koninklijke Philips Electronics N.V. Dedicated encrypted virtual channel in a multi-channel serial communications interface
FR2862150A1 (en) * 2003-11-12 2005-05-13 Innova Card Integrated circuit for performing confidential transaction, has central processing unit, random access memory and read only memory that are connected by data bus that routes encrypted data produced from plain data

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US5117457A (en) 1986-11-05 1992-05-26 International Business Machines Corp. Tamper resistant packaging for information protection in electronic circuitry
US6215397B1 (en) 1996-08-13 2001-04-10 Lindskog Innovation Ab Electrical manually portable security case for the storage of theft attractive articles with an electrical mat having at least one elongated electrically conductive wire in a substantially continuous mesh, loop or eye structure
US5568124A (en) 1993-05-20 1996-10-22 Hughes Aircraft Company Method to detect penetration of a surface and apparatus implementing same
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EP0806737A2 (en) * 1996-05-08 1997-11-12 Lattice Semiconductor Corporation In-system programming with two wire interface
WO2002071231A1 (en) * 2001-02-15 2002-09-12 Nokia Corporation Method and arrangement for protecting information
WO2004056031A2 (en) * 2002-12-18 2004-07-01 Koninklijke Philips Electronics N.V. Dedicated encrypted virtual channel in a multi-channel serial communications interface
FR2862150A1 (en) * 2003-11-12 2005-05-13 Innova Card Integrated circuit for performing confidential transaction, has central processing unit, random access memory and read only memory that are connected by data bus that routes encrypted data produced from plain data

Also Published As

Publication number Publication date
US7961885B2 (en) 2011-06-14
EP1896948A2 (en) 2008-03-12
WO2007005706A2 (en) 2007-01-11
US20060242465A1 (en) 2006-10-26

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