WO2007027409A8 - Combined engine for video and graphics processing - Google Patents

Combined engine for video and graphics processing

Info

Publication number
WO2007027409A8
WO2007027409A8 PCT/US2006/031451 US2006031451W WO2007027409A8 WO 2007027409 A8 WO2007027409 A8 WO 2007027409A8 US 2006031451 W US2006031451 W US 2006031451W WO 2007027409 A8 WO2007027409 A8 WO 2007027409A8
Authority
WO
WIPO (PCT)
Prior art keywords
combined engine
video
arbiter
graphics
channel
Prior art date
Application number
PCT/US2006/031451
Other languages
French (fr)
Other versions
WO2007027409A2 (en
WO2007027409A3 (en
Inventor
Enoch Y Lee
Li Sha
Shuhua Xiang
Original Assignee
Micronas Usa Inc
Enoch Y Lee
Li Sha
Shuhua Xiang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micronas Usa Inc, Enoch Y Lee, Li Sha, Shuhua Xiang filed Critical Micronas Usa Inc
Priority to EP06789714A priority Critical patent/EP1987488A4/en
Publication of WO2007027409A2 publication Critical patent/WO2007027409A2/en
Publication of WO2007027409A3 publication Critical patent/WO2007027409A3/en
Publication of WO2007027409A8 publication Critical patent/WO2007027409A8/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
    • G09G2340/125—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels wherein one of the images is motion video
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/10—Display system comprising arrangements, such as a coprocessor, specific for motion video images
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Abstract

The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.
PCT/US2006/031451 2005-08-31 2006-08-11 Combined engine for video and graphics processing WO2007027409A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06789714A EP1987488A4 (en) 2005-08-31 2006-08-11 Combined engine for video and graphics processing

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US71350605P 2005-08-31 2005-08-31
US60/713,506 2005-08-31
US11/259,558 US7380036B2 (en) 2004-12-10 2005-10-25 Combined engine for video and graphics processing
US11/259,558 2005-10-25

Publications (3)

Publication Number Publication Date
WO2007027409A2 WO2007027409A2 (en) 2007-03-08
WO2007027409A3 WO2007027409A3 (en) 2007-11-01
WO2007027409A8 true WO2007027409A8 (en) 2007-12-27

Family

ID=37809352

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/031451 WO2007027409A2 (en) 2005-08-31 2006-08-11 Combined engine for video and graphics processing

Country Status (3)

Country Link
US (2) US7380036B2 (en)
EP (1) EP1987488A4 (en)
WO (1) WO2007027409A2 (en)

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US20070283131A1 (en) * 2006-01-30 2007-12-06 Ati Technologies Inc. Processing of high priority data elements in systems comprising a host processor and a co-processor
US7924296B2 (en) * 2007-02-20 2011-04-12 Mtekvision Co., Ltd. System and method for DMA controlled image processing
US9665969B1 (en) * 2009-09-29 2017-05-30 Nvidia Corporation Data path and instruction set for packed pixel operations for video processing
US20130021438A1 (en) * 2010-03-31 2013-01-24 Design & Test Technology, Inc. 3d video processing unit
US8925009B2 (en) * 2010-12-10 2014-12-30 Verizon Patent And Licensing Inc. Graphics handling for electronic program guide graphics in an RVU system
US9535722B2 (en) * 2012-09-12 2017-01-03 The Directv Group, Inc. Method and system for communicating between a host device and a user device through an intermediate device using a composite graphics signal
US10521250B2 (en) 2012-09-12 2019-12-31 The Directv Group, Inc. Method and system for communicating between a host device and user device through an intermediate device using a composite video signal
US9747658B2 (en) * 2013-09-06 2017-08-29 Apple Inc. Arbitration method for multi-request display pipeline
CN103489424B (en) * 2013-10-08 2016-01-13 东南大学 A kind of implementation method of image-text video mixed display driver

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Also Published As

Publication number Publication date
WO2007027409A2 (en) 2007-03-08
US7380036B2 (en) 2008-05-27
EP1987488A2 (en) 2008-11-05
US20060125831A1 (en) 2006-06-15
EP1987488A4 (en) 2010-05-26
US20080222332A1 (en) 2008-09-11
US7516259B2 (en) 2009-04-07
WO2007027409A3 (en) 2007-11-01

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