WO2007027762A8 - Metal interconnect structure for integrated ciruits and a design rule therefor - Google Patents

Metal interconnect structure for integrated ciruits and a design rule therefor

Info

Publication number
WO2007027762A8
WO2007027762A8 PCT/US2006/033841 US2006033841W WO2007027762A8 WO 2007027762 A8 WO2007027762 A8 WO 2007027762A8 US 2006033841 W US2006033841 W US 2006033841W WO 2007027762 A8 WO2007027762 A8 WO 2007027762A8
Authority
WO
WIPO (PCT)
Prior art keywords
metallization
interconnect structure
level
lines
given level
Prior art date
Application number
PCT/US2006/033841
Other languages
French (fr)
Other versions
WO2007027762A3 (en
WO2007027762A2 (en
Inventor
Takeshi Nogami
Keishi Inoue
Original Assignee
Sony Corp
Sony Electronics Inc
Takeshi Nogami
Keishi Inoue
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Sony Electronics Inc, Takeshi Nogami, Keishi Inoue filed Critical Sony Corp
Publication of WO2007027762A2 publication Critical patent/WO2007027762A2/en
Publication of WO2007027762A8 publication Critical patent/WO2007027762A8/en
Publication of WO2007027762A3 publication Critical patent/WO2007027762A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two. The layout of lines in the second level of metallization is arranged so that they partially overlap in the vertical direction one of the lines in the first level of metallization.
PCT/US2006/033841 2005-08-30 2006-08-30 Metal interconnect structure for integrated ciruits and a design rule therefor WO2007027762A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/215,766 2005-08-30
US11/215,766 US7251799B2 (en) 2005-08-30 2005-08-30 Metal interconnect structure for integrated circuits and a design rule therefor

Publications (3)

Publication Number Publication Date
WO2007027762A2 WO2007027762A2 (en) 2007-03-08
WO2007027762A8 true WO2007027762A8 (en) 2007-12-06
WO2007027762A3 WO2007027762A3 (en) 2008-01-24

Family

ID=37802939

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/033841 WO2007027762A2 (en) 2005-08-30 2006-08-30 Metal interconnect structure for integrated ciruits and a design rule therefor

Country Status (2)

Country Link
US (1) US7251799B2 (en)
WO (1) WO2007027762A2 (en)

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US7340709B1 (en) * 2004-07-08 2008-03-04 Luxtera, Inc. Method of generating a geometrical rule for germanium integration within CMOS
KR100679822B1 (en) * 2005-12-14 2007-02-06 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method thereof
US7566652B2 (en) * 2006-07-24 2009-07-28 Texas Instruments Incorporated Electrically inactive via for electromigration reliability improvement
KR100778869B1 (en) * 2006-09-06 2007-11-22 동부일렉트로닉스 주식회사 Method for forming contact of semiconductor device
US7981771B2 (en) * 2008-06-04 2011-07-19 International Business Machines Corporation Structures and methods to enhance Cu interconnect electromigration (EM) performance
US9293410B2 (en) * 2013-11-29 2016-03-22 Samsung Electronics Co., Ltd. Semiconductor device

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US5920088A (en) * 1995-06-16 1999-07-06 Interuniversitair Micro-Electronica Centrum (Imec Vzw) Vertical MISFET devices
US8779597B2 (en) * 2004-06-21 2014-07-15 Sang-Yun Lee Semiconductor device with base support structure
US5729491A (en) * 1996-11-12 1998-03-17 Samsung Electronics Co., Ltd. Nonvolatile integrated circuit memory devices having ground interconnect lattices with reduced lateral dimensions
US20040113222A1 (en) 2002-09-16 2004-06-17 Ozguz Volkan H Stacked microelectronic module with vertical interconnect vias
US6122187A (en) 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6770975B2 (en) 1999-06-09 2004-08-03 Alliedsignal Inc. Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
US20030082845A1 (en) 2000-01-14 2003-05-01 Amkor Technology, Inc. Package for multiple integrated circuits and method of making
US7494927B2 (en) 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
US6596467B2 (en) 2000-09-13 2003-07-22 Shipley Company, L.L.C. Electronic device manufacture
US6527855B2 (en) 2000-10-10 2003-03-04 Rensselaer Polytechnic Institute Atomic layer deposition of cobalt from cobalt metallorganic compounds
US20020064592A1 (en) 2000-11-29 2002-05-30 Madhav Datta Electroless method of seed layer depostion, repair, and fabrication of Cu interconnects
US6992394B2 (en) 2000-12-28 2006-01-31 Infineon Technologies Ag Multi-level conductive lines with reduced pitch
US6936906B2 (en) 2001-09-26 2005-08-30 Applied Materials, Inc. Integration of barrier layer and seed layer
US20030218253A1 (en) 2001-12-13 2003-11-27 Avanzino Steven C. Process for formation of a wiring network using a porous interlevel dielectric and related structures
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US6924222B2 (en) * 2002-11-21 2005-08-02 Intel Corporation Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide
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US20050130407A1 (en) 2003-12-12 2005-06-16 Jui-Neng Tu Dual damascene process for forming a multi-layer low-k dielectric interconnect

Also Published As

Publication number Publication date
WO2007027762A3 (en) 2008-01-24
US20070045850A1 (en) 2007-03-01
US7251799B2 (en) 2007-07-31
WO2007027762A2 (en) 2007-03-08

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