WO2007039412A3 - System and method for dynamic power management in a processor design - Google Patents

System and method for dynamic power management in a processor design Download PDF

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Publication number
WO2007039412A3
WO2007039412A3 PCT/EP2006/066249 EP2006066249W WO2007039412A3 WO 2007039412 A3 WO2007039412 A3 WO 2007039412A3 EP 2006066249 W EP2006066249 W EP 2006066249W WO 2007039412 A3 WO2007039412 A3 WO 2007039412A3
Authority
WO
WIPO (PCT)
Prior art keywords
pipeline stage
detection logic
stall
power management
dynamic power
Prior art date
Application number
PCT/EP2006/066249
Other languages
French (fr)
Other versions
WO2007039412A2 (en
Inventor
Christopher Michael Abernathy
Jonathan James Dement
Ronald Hall
Robert Alan Philhower
David Shippy
Original Assignee
Ibm
Ibm Uk
Christopher Michael Abernathy
Jonathan James Dement
Ronald Hall
Robert Alan Philhower
David Shippy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Ibm Uk, Christopher Michael Abernathy, Jonathan James Dement, Ronald Hall, Robert Alan Philhower, David Shippy filed Critical Ibm
Priority to CN2006800341885A priority Critical patent/CN101268432B/en
Priority to EP06793427A priority patent/EP1941338A2/en
Publication of WO2007039412A2 publication Critical patent/WO2007039412A2/en
Publication of WO2007039412A3 publication Critical patent/WO2007039412A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3237Power saving characterised by the action undertaken by disabling clock generation or distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3243Power saving in microcontroller unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
PCT/EP2006/066249 2005-09-27 2006-09-11 System and method for dynamic power management in a processor design WO2007039412A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800341885A CN101268432B (en) 2005-09-27 2006-09-11 System and method for dynamic power management in a processor design
EP06793427A EP1941338A2 (en) 2005-09-27 2006-09-11 System and method for dynamic power management in a processor design

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/236,657 2005-09-27
US11/236,657 US7401242B2 (en) 2005-09-27 2005-09-27 Dynamic power management in a processor design

Publications (2)

Publication Number Publication Date
WO2007039412A2 WO2007039412A2 (en) 2007-04-12
WO2007039412A3 true WO2007039412A3 (en) 2007-10-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/066249 WO2007039412A2 (en) 2005-09-27 2006-09-11 System and method for dynamic power management in a processor design

Country Status (4)

Country Link
US (2) US7401242B2 (en)
EP (1) EP1941338A2 (en)
CN (1) CN101268432B (en)
WO (1) WO2007039412A2 (en)

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US8701091B1 (en) 2005-12-15 2014-04-15 Nvidia Corporation Method and system for providing a generic console interface for a graphics application
DE102006004346A1 (en) * 2006-01-30 2007-10-18 Deutsche Thomson-Brandt Gmbh Data bus interface with switch-off clock
US8452981B1 (en) 2006-03-01 2013-05-28 Nvidia Corporation Method for author verification and software authorization
US7891012B1 (en) 2006-03-01 2011-02-15 Nvidia Corporation Method and computer-usable medium for determining the authorization status of software
US8963932B1 (en) * 2006-08-01 2015-02-24 Nvidia Corporation Method and apparatus for visualizing component workloads in a unified shader GPU architecture
US8607151B2 (en) * 2006-08-01 2013-12-10 Nvidia Corporation Method and system for debugging a graphics pipeline subunit
US8436864B2 (en) * 2006-08-01 2013-05-07 Nvidia Corporation Method and user interface for enhanced graphical operation organization
US8436870B1 (en) 2006-08-01 2013-05-07 Nvidia Corporation User interface and method for graphical processing analysis
US8073669B2 (en) * 2007-08-21 2011-12-06 International Business Machines Corporation Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design
US8458497B2 (en) 2007-10-11 2013-06-04 Qualcomm Incorporated Demand based power control in a graphics processing unit
CN101493761B (en) * 2008-01-25 2013-05-29 国际商业机器公司 Method for pipelinedly processing instruction by processor and relevant processor
US8448002B2 (en) * 2008-04-10 2013-05-21 Nvidia Corporation Clock-gated series-coupled data processing modules
CN103890713B (en) * 2011-10-01 2018-08-24 英特尔公司 Device and method for managing the register information in processing system
CN102439535A (en) * 2011-10-25 2012-05-02 深圳市海思半导体有限公司 Method for reducing dynamic power dissipation and electronic device
US9323315B2 (en) * 2012-08-15 2016-04-26 Nvidia Corporation Method and system for automatic clock-gating of a clock grid at a clock source
US8850371B2 (en) 2012-09-14 2014-09-30 Nvidia Corporation Enhanced clock gating in retimed modules
US9471456B2 (en) 2013-05-15 2016-10-18 Nvidia Corporation Interleaved instruction debugger
US9645635B2 (en) * 2015-05-26 2017-05-09 Nvidia Corporation Selective power gating to extend the lifetime of sleep FETs
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CN107610039A (en) * 2016-07-12 2018-01-19 联发科技股份有限公司 Image processing method and image processing apparatus
US10298456B1 (en) 2016-11-28 2019-05-21 Barefoot Networks, Inc. Dynamically reconfiguring data plane of forwarding element to account for power consumption
US10630294B1 (en) * 2019-03-04 2020-04-21 Micron Technology, Inc. Apparatuses and methods for transmitting an operation mode with a clock

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Also Published As

Publication number Publication date
US7401242B2 (en) 2008-07-15
CN101268432B (en) 2010-06-16
EP1941338A2 (en) 2008-07-09
WO2007039412A2 (en) 2007-04-12
US20070074059A1 (en) 2007-03-29
CN101268432A (en) 2008-09-17
US7681056B2 (en) 2010-03-16
US20080229078A1 (en) 2008-09-18

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