WO2007040752A3 - Process and system for etching doped silicon using sf6-based chemistry - Google Patents

Process and system for etching doped silicon using sf6-based chemistry Download PDF

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Publication number
WO2007040752A3
WO2007040752A3 PCT/US2006/029278 US2006029278W WO2007040752A3 WO 2007040752 A3 WO2007040752 A3 WO 2007040752A3 US 2006029278 W US2006029278 W US 2006029278W WO 2007040752 A3 WO2007040752 A3 WO 2007040752A3
Authority
WO
WIPO (PCT)
Prior art keywords
doped silicon
based chemistry
etching doped
etching
fluorocarbon gas
Prior art date
Application number
PCT/US2006/029278
Other languages
French (fr)
Other versions
WO2007040752A2 (en
Inventor
Akiteru Ko
Original Assignee
Tokyo Electron Ltd
Akiteru Ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd, Akiteru Ko filed Critical Tokyo Electron Ltd
Priority to KR1020087008478A priority Critical patent/KR101220073B1/en
Priority to JP2008531093A priority patent/JP5159626B2/en
Publication of WO2007040752A2 publication Critical patent/WO2007040752A2/en
Publication of WO2007040752A3 publication Critical patent/WO2007040752A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process and system for anisoptropically dry etching through a doped silicon layer is described. The process chemistry comprises SF6 and a fluorocarbon gas. For example, the fluorocarbon gas can include CxFy, where x and y are integers greater than or equal to unity, for example, C4F8.
PCT/US2006/029278 2005-09-14 2006-07-27 Process and system for etching doped silicon using sf6-based chemistry WO2007040752A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020087008478A KR101220073B1 (en) 2005-09-14 2006-07-27 Method of etching a silicon layer on a substrate, plasma processing system for etching a silicon layer on a substrate and computer readable medium
JP2008531093A JP5159626B2 (en) 2005-09-14 2006-07-27 Process and system for etching doped silicon using SF6 based chemistry

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/225,891 2005-09-14
US11/225,891 US7531461B2 (en) 2005-09-14 2005-09-14 Process and system for etching doped silicon using SF6-based chemistry

Publications (2)

Publication Number Publication Date
WO2007040752A2 WO2007040752A2 (en) 2007-04-12
WO2007040752A3 true WO2007040752A3 (en) 2008-01-17

Family

ID=37853997

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/029278 WO2007040752A2 (en) 2005-09-14 2006-07-27 Process and system for etching doped silicon using sf6-based chemistry

Country Status (6)

Country Link
US (1) US7531461B2 (en)
JP (1) JP5159626B2 (en)
KR (1) KR101220073B1 (en)
CN (1) CN100557776C (en)
TW (1) TWI338330B (en)
WO (1) WO2007040752A2 (en)

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US7341951B2 (en) * 2005-12-27 2008-03-11 Micron Technology, Inc. Methods of forming semiconductor constructions
US8394724B2 (en) * 2006-08-31 2013-03-12 Globalfoundries Singapore Pte. Ltd. Processing with reduced line end shortening ratio
CN101925983A (en) * 2007-12-21 2010-12-22 苏威氟有限公司 Process for production of microelectromechanical systems
US7888267B2 (en) * 2008-02-01 2011-02-15 Tokyo Electron Limited Method for etching silicon-containing ARC layer with reduced CD bias
JP4999185B2 (en) * 2008-03-04 2012-08-15 富士フイルム株式会社 Dry etching method and dry etching apparatus
JP5102720B2 (en) * 2008-08-25 2012-12-19 東京エレクトロン株式会社 Substrate processing method
JP5530088B2 (en) * 2008-10-20 2014-06-25 東京エレクトロン株式会社 Plasma etching method and plasma etching apparatus
CN103086607B (en) * 2011-10-28 2015-08-26 清华大学 The preparation method of grating
CN102709350A (en) * 2012-07-05 2012-10-03 合肥海润光伏科技有限公司 Selective emitter structure of solar cell and preparation method thereof
US9882113B1 (en) * 2014-06-23 2018-01-30 National Technology & Engineering Solutions Of Sandia, Llc Gallium beam lithography for superconductive structure formation
GB2551017B (en) * 2014-10-10 2020-03-11 Kanto Denka Kogyo Kk Etching gas composition for silicon compound, and etching method
KR101623654B1 (en) * 2014-11-25 2016-05-23 아주대학교산학협력단 Etching method of silicon substrate using plasma gas
GB2533090A (en) * 2014-12-08 2016-06-15 Skf Ab Sensor device with mounting means
EP3153463B1 (en) 2015-10-08 2018-06-13 IMEC vzw Method for producing a pillar structure in a semiconductor layer
JP7443953B2 (en) 2020-06-19 2024-03-06 東京エレクトロン株式会社 Method and system for removing phosphorus-doped silicon film
JP2023002200A (en) * 2021-06-22 2023-01-10 東京エレクトロン株式会社 Method and device for forming film

Citations (5)

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US6479373B2 (en) * 1997-02-20 2002-11-12 Infineon Technologies Ag Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases
US20030190814A1 (en) * 1999-12-23 2003-10-09 Applied Materials, Inc. Method of reducing micromasking during plasma etching of a silicon-comprising substrate
US6660127B2 (en) * 1999-09-22 2003-12-09 Applied Materials, Inc. Apparatus for plasma etching at a constant etch rate
US6815366B2 (en) * 2002-09-20 2004-11-09 Fujitsu Limited Method for etching organic insulating film and method for fabricating semiconductor device
US6921723B1 (en) * 2002-04-23 2005-07-26 Applied Materials, Inc. Etching method having high silicon-to-photoresist selectivity

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JP3193265B2 (en) 1995-05-20 2001-07-30 東京エレクトロン株式会社 Plasma etching equipment
DE19706783A1 (en) * 1997-02-20 1998-08-27 Siemens Ag Methods for producing doped polysilicon layers and layer structures and methods for structuring layers and layer structures which comprise polysilicon layers
US6635185B2 (en) * 1997-12-31 2003-10-21 Alliedsignal Inc. Method of etching and cleaning using fluorinated carbonyl compounds
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity
US6890863B1 (en) 2000-04-27 2005-05-10 Micron Technology, Inc. Etchant and method of use
US6670278B2 (en) * 2001-03-30 2003-12-30 Lam Research Corporation Method of plasma etching of silicon carbide
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US6867084B1 (en) 2002-10-03 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure and method of forming the gate dielectric with mini-spacer
JP3905462B2 (en) 2002-11-20 2007-04-18 東京エレクトロン株式会社 Plasma processing method and plasma processing apparatus
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479373B2 (en) * 1997-02-20 2002-11-12 Infineon Technologies Ag Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases
US6660127B2 (en) * 1999-09-22 2003-12-09 Applied Materials, Inc. Apparatus for plasma etching at a constant etch rate
US20030190814A1 (en) * 1999-12-23 2003-10-09 Applied Materials, Inc. Method of reducing micromasking during plasma etching of a silicon-comprising substrate
US6921723B1 (en) * 2002-04-23 2005-07-26 Applied Materials, Inc. Etching method having high silicon-to-photoresist selectivity
US6815366B2 (en) * 2002-09-20 2004-11-09 Fujitsu Limited Method for etching organic insulating film and method for fabricating semiconductor device

Also Published As

Publication number Publication date
JP5159626B2 (en) 2013-03-06
JP2009508354A (en) 2009-02-26
US7531461B2 (en) 2009-05-12
TW200717647A (en) 2007-05-01
CN101263582A (en) 2008-09-10
TWI338330B (en) 2011-03-01
KR20080044340A (en) 2008-05-20
US20070056926A1 (en) 2007-03-15
KR101220073B1 (en) 2013-01-18
CN100557776C (en) 2009-11-04
WO2007040752A2 (en) 2007-04-12

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