WO2007046771A1 - Method of forming component package - Google Patents
Method of forming component package Download PDFInfo
- Publication number
- WO2007046771A1 WO2007046771A1 PCT/SG2005/000362 SG2005000362W WO2007046771A1 WO 2007046771 A1 WO2007046771 A1 WO 2007046771A1 SG 2005000362 W SG2005000362 W SG 2005000362W WO 2007046771 A1 WO2007046771 A1 WO 2007046771A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- die pad
- isolation layer
- heat sink
- forming
- mould
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
Abstract
There is provided a method of forming a component package. The method includes the steps of providing the die pad or heat sink, forming an isolation layer on the rear surface of the die pad or heat sink and encapsulating the die pad with encapsulating material in a mould cavity after forming the isolation layer on the rear of the die pad or heat sink.
Description
METHOD OF FORMING COMPONENT PACKAGE
Field of the invention
The present invention relates to a method of forming a component package, arid in particular to the formation of a component package in which .an isolation layer is provided on the heat sink or die pad.
Discussion of the prior art
Component packages typically comprise a die pad or heat sink which supports the component, for example in the form of a semiconductor chip. The die pad or heat sink and components are encapsulated in a resin material. This is generally achieved by locating the die pad and components within a mould cavity, and injecting or introducing resin material into the mould cavity. By surrounding the die pad or heat sink with resin material, an isolation layer is formed on the rear surface of the die pad.
The problem with this known method is that the die pad or heat sink may move within the mould cavity during injection of the encapsulating material, and accordingly it becomes difficult to reproduce a highly accurate isolation layer thickness on the rear of the heat sink. To try and overcome this problem, it has been proposed to maintain the position of the die pad or heat sink within the mould cavity for example using one or more pins which hold the die pad or heat sink in position. In one example, the pins are retractable, such that these are removed during the moulding process. However, such retractable pins are liable to wear, and therefore regularly need replacing. Further, the retraction of the pins must be carefully controlled to ensure that the encapsulating material fills the spaces from which the pins were retracted. The difficulty in accurately timing the retraction of the pins may result in a highly inconsistent outcome of the product. Where the pins are fixed, it is necessary to remove the pins after initial moulding, and to then fill the hole left by the pins. Typically, the material used to fill these holes is not the same as the mould compound, leading to a possible material mismatch.
Summary of the invention
According to the present invention, a method of forming a component package comprises providing the die pad or heat sink, and forming an isolation layer on the rear surface of the die pad or heat sink prior to encapsulating the die pad with encapsulating material in the mould cavity. By forming the isolation layer on the rear of the die pad or heat sink prior to encapsulation of the device, it is possible to accurately form an isolation layer of known and consistent thickness. Accordingly, it is then less important whether the die pad or heat sink moves during the final encapsulation process.
The isolation layer should be formed from insulating material, and is preferably formed from the same material as the mould compound used to encapsulate the device. This ensures that there is no mismatch between the materials which may affect the electrical properties, as well as the physical properties, of the device.
It is also preferred that the isolation layer is formed by a moulding process, preferably by a transfer moulding process.
It will be appreciated that the die pad or heat sink with the preformed isolation layer may be held within the mould cavity during the final encapsulate using either fixed or retractable pains as is known in the prior art.
Brief description of the drawings
The present invention will be described, by way of example, with reference to the accompanying drawings, in which:
Figure 1 shows a cross-sectional view of a mould for encapsulating the device according to the prior art; and,
Figure 2 shows the pre-moulding of an isolation layer according to the present invention.
Detailed description of a preferred example
Figure 1 shows a cross-section of a mould apparatus for encapsulating a die pad 2 and component 4 according to a prior art of method. The apparatus comprises an upper mould element 12 and a lower mould element 14 defining between them a mould cavity 10. The lower mould element 14 is provided on an ejector plate, and the die pad 2 on which the component 4 is mounted is held within the mould cavity 10. Electrical contacts 8 connect the component 4 to the in the end of leads 6, which also supports the die pad or heat sink 4. The upper mould element 12 is located over the lower mould element 14 to define the mould cavity 10. The end of the die pad 2 not supported by the inner end of the leads 6 is supported by a pair of retractable pins 16, each of which are spring biased by spring 18. The two retractable pins 16 support the free end of the die pad 2 from above and below to hold this in place.'
Mould compound is injected into the mould cavity 10, surrounding all sides of the die pad 2, component 4, contacts 8 and leads 6. As the mould compound is introduced, the retractable pins 16 are retracted to enable the mould compound to completely fill the cavity.
During the filling of the mould cavity, there is a risk that the die pad 2 will move. Accordingly, the thickness of mould material on the rear of the die pad 2 as shown in Figure 1 may not be consistent across the entire' surface of the die pad 2. This may result in undesirable electrical and mechanical properties of the finished package.
The present invention is illustrated in Figure 2. As can be seen, the die pad or heat sink 2 is formed with the component 4 provided on one surface, with electrical contacts between the component 4 and the inner end of leads 6, and with one end of the die pad 2 supported by the inner end of the leads 6. However, prior to introduction of the die pad 2 and component 4 into a mould cavity, an isolation layer 22 is formed on the rear of the die pad 2. This isolation layer 22 is formed on the rear of the die pad 2 by a transfer moulding technique. In particular, the isolation layer 22 is formed in a mould cavity 20, and is then provided on the rear of the die pad 2. In this way, an isolation
layer of uniform thickness and properties can be formed on the rear of the die pad 2.
After forming the isolation layer 22 on the rear of the die pad 2, the resulting device may be provided in a. mould cavity and mould compound can be injected around the resulting device in a manner known from the prior art. Ideally, the mould compound used to encapsulate the device is of the same material as the isolation layer to ensure optimum mechanical and electrical properties of the resulting device.
Claims
1. A method of forming a component package comprises:
providing the die pad or heat sink;
forming an isolation layer on the rear surface of the die pad or heat sink;
encapsulating the die pad with encapsulating material in a mould cavity after forming the isolation layer on the rear of the die pad or heat sink.
2. The method according to Claim 1 , in which the isolation layer is formed from insulating material.
3. The method according to Claim 1 or Claim 2, in which the isolation material is formed from the same material as the encapsulating used to encapsulate the device.
4. The method according to any one of the preceding claims, in which the isolation layer is formed by a moulding process.
5. The method according to Claim 4, in which the isolation layer is formed by a transfer moulding process.
6. The method according to any one of the preceding claims, in which the die pad or heat sink is supported by pins within the mould cavity during encapsulation.
7. The method according to Claim 6, in which the pins are retracted during encapsulation.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/SG2005/000362 WO2007046771A1 (en) | 2005-10-19 | 2005-10-19 | Method of forming component package |
| US12/049,276 US7723165B2 (en) | 2005-10-19 | 2008-03-15 | Method of forming component package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/SG2005/000362 WO2007046771A1 (en) | 2005-10-19 | 2005-10-19 | Method of forming component package |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/049,276 Continuation US7723165B2 (en) | 2005-10-19 | 2008-03-15 | Method of forming component package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2007046771A1 true WO2007046771A1 (en) | 2007-04-26 |
| WO2007046771A8 WO2007046771A8 (en) | 2007-07-12 |
Family
ID=35789122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/SG2005/000362 WO2007046771A1 (en) | 2005-10-19 | 2005-10-19 | Method of forming component package |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7723165B2 (en) |
| WO (1) | WO2007046771A1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5989940A (en) * | 1994-05-26 | 1999-11-23 | Nec Corporation | Semiconductor device capable of accomplishing a high moisture proof |
| US20040026776A1 (en) * | 2002-08-08 | 2004-02-12 | Brand Joseph M. | Microelectronic devices and methods for manufacturing and operating packaged microelectronic device assemblies |
| US20040065945A1 (en) * | 1999-12-06 | 2004-04-08 | Smith Steven R. | Semiconductor package having polymer members configured to provide selected package characteristics |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1197469A (en) | 1997-09-17 | 1999-04-09 | Shinko Electric Ind Co Ltd | Manufacture of premold package |
| JP3737673B2 (en) * | 2000-05-23 | 2006-01-18 | 株式会社ルネサステクノロジ | Semiconductor device |
| EP1403926A2 (en) | 2002-09-27 | 2004-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
| US8334583B2 (en) * | 2005-07-20 | 2012-12-18 | Infineon Technologies Ag | Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component |
-
2005
- 2005-10-19 WO PCT/SG2005/000362 patent/WO2007046771A1/en active Application Filing
-
2008
- 2008-03-15 US US12/049,276 patent/US7723165B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5989940A (en) * | 1994-05-26 | 1999-11-23 | Nec Corporation | Semiconductor device capable of accomplishing a high moisture proof |
| US20040065945A1 (en) * | 1999-12-06 | 2004-04-08 | Smith Steven R. | Semiconductor package having polymer members configured to provide selected package characteristics |
| US20040026776A1 (en) * | 2002-08-08 | 2004-02-12 | Brand Joseph M. | Microelectronic devices and methods for manufacturing and operating packaged microelectronic device assemblies |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007046771A8 (en) | 2007-07-12 |
| US20080160677A1 (en) | 2008-07-03 |
| US7723165B2 (en) | 2010-05-25 |
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