WO2007054871A3 - Control device with flag registers for synchronization of communications between cores - Google Patents

Control device with flag registers for synchronization of communications between cores Download PDF

Info

Publication number
WO2007054871A3
WO2007054871A3 PCT/IB2006/054104 IB2006054104W WO2007054871A3 WO 2007054871 A3 WO2007054871 A3 WO 2007054871A3 IB 2006054104 W IB2006054104 W IB 2006054104W WO 2007054871 A3 WO2007054871 A3 WO 2007054871A3
Authority
WO
WIPO (PCT)
Prior art keywords
cores
control device
address
synchronization
communications
Prior art date
Application number
PCT/IB2006/054104
Other languages
French (fr)
Other versions
WO2007054871A2 (en
Inventor
Francois Chancel
Patrick Fulcheri
Original Assignee
Nxp Bv
Francois Chancel
Patrick Fulcheri
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Francois Chancel, Patrick Fulcheri filed Critical Nxp Bv
Priority to JP2008538485A priority Critical patent/JP4940436B2/en
Priority to CN2006800415183A priority patent/CN101305356B/en
Priority to US12/092,615 priority patent/US7890736B2/en
Priority to EP06821324A priority patent/EP1949249A2/en
Publication of WO2007054871A2 publication Critical patent/WO2007054871A2/en
Publication of WO2007054871A3 publication Critical patent/WO2007054871A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1,C2) coupled, via buses (BCl, BC2), to a memory (M) arranged to store data to be transferred between these cores (Cl, C2). This control device (D) comprises at least one flag register (FRl, FR2) coupled to the cores (C1,C2) via the buses (BCl, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1,C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2,C1) by means of a command designating the second address.
PCT/IB2006/054104 2005-11-08 2006-11-03 Control device with flag registers for synchronization of communications between cores WO2007054871A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008538485A JP4940436B2 (en) 2005-11-08 2006-11-03 Control device having flag register for synchronization of inter-core communication
CN2006800415183A CN101305356B (en) 2005-11-08 2006-11-03 Control device with flag registers for synchronization of communications between cores
US12/092,615 US7890736B2 (en) 2005-11-08 2006-11-03 Control device with flag registers for synchronization of communications between cores
EP06821324A EP1949249A2 (en) 2005-11-08 2006-11-03 Control device with flag registers for synchronization of communications between cores

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05300900.7 2005-11-08
EP05300900 2005-11-08

Publications (2)

Publication Number Publication Date
WO2007054871A2 WO2007054871A2 (en) 2007-05-18
WO2007054871A3 true WO2007054871A3 (en) 2008-04-17

Family

ID=37938484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/054104 WO2007054871A2 (en) 2005-11-08 2006-11-03 Control device with flag registers for synchronization of communications between cores

Country Status (7)

Country Link
US (1) US7890736B2 (en)
EP (1) EP1949249A2 (en)
JP (1) JP4940436B2 (en)
KR (1) KR101029392B1 (en)
CN (1) CN101305356B (en)
TW (1) TWI416340B (en)
WO (1) WO2007054871A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9760526B1 (en) 2011-09-30 2017-09-12 EMC IP Holdings Company LLC Multiprocessor messaging system
US9037838B1 (en) 2011-09-30 2015-05-19 Emc Corporation Multiprocessor messaging system
CN104583936B (en) 2012-06-15 2019-01-04 英特尔公司 With composition sequentially from the semaphore method and system of the out-of-order load in the memory consistency model for the load that memory is read out
KR101660022B1 (en) * 2015-09-10 2016-09-27 아둘람테크 주식회사 Apparatus and method for improving efficiency of bus interface

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594657A (en) * 1983-04-22 1986-06-10 Motorola, Inc. Semaphore for memory shared by two asynchronous microcomputers
US6907503B2 (en) * 2001-09-27 2005-06-14 Daimlerchrysler Corporation Dual port RAM communication protocol

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US690750A (en) * 1901-02-09 1902-01-07 Nat Carbon Co Sparking-coil.
JPH0656603B2 (en) * 1986-02-10 1994-07-27 株式会社日立マイコンシステム Data processing system
JPS63654A (en) * 1986-06-19 1988-01-05 Fujitsu Ltd Inter-processor communication control system
US5611053A (en) * 1994-01-21 1997-03-11 Advanced Micro Devices, Inc. Apparatus and method for integrating bus master ownership of local bus load by plural data transceivers
JP2859178B2 (en) * 1995-09-12 1999-02-17 日本電気通信システム株式会社 Data transfer method between processors and ring buffer memory for data transfer between processors
US5649125A (en) * 1995-10-30 1997-07-15 Motorola, Inc. Method and apparatus for address extension across a multiplexed communication bus
US6711667B1 (en) * 1996-06-28 2004-03-23 Legerity, Inc. Microprocessor configured to translate instructions from one instruction set to another, and to store the translated instructions
US5951659A (en) * 1997-04-07 1999-09-14 Ncr Corporation Communications-oriented computer system backplane including a PCI input/output bus for transmission of address, data, and control information, and a time-domain multiplexed signal bus (TDMSB) for transmission of high-speed digitized signal information
JP2001508214A (en) * 1997-10-29 2001-06-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Block structured data transfer synchronization method and system
JP4123315B2 (en) * 1999-02-19 2008-07-23 株式会社安川電機 Data transfer apparatus and method for dual port RAM
TW476029B (en) * 1999-07-12 2002-02-11 Matsushita Electric Ind Co Ltd Data processing apparatus
DE19951541C1 (en) * 1999-10-26 2000-10-26 Siemens Ag Integrated circuit component, e.g. ASIC
WO2002061591A1 (en) * 2001-01-31 2002-08-08 Hitachi,Ltd Data processing system and data processor
US6823441B1 (en) * 2001-04-20 2004-11-23 Daimlerchrysler Corporation Method of multiplexed address and data bus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594657A (en) * 1983-04-22 1986-06-10 Motorola, Inc. Semaphore for memory shared by two asynchronous microcomputers
US6907503B2 (en) * 2001-09-27 2005-06-14 Daimlerchrysler Corporation Dual port RAM communication protocol

Also Published As

Publication number Publication date
JP2009514118A (en) 2009-04-02
KR101029392B1 (en) 2011-04-14
TWI416340B (en) 2013-11-21
US20080294876A1 (en) 2008-11-27
CN101305356B (en) 2010-09-01
WO2007054871A2 (en) 2007-05-18
CN101305356A (en) 2008-11-12
EP1949249A2 (en) 2008-07-30
TW200811666A (en) 2008-03-01
US7890736B2 (en) 2011-02-15
JP4940436B2 (en) 2012-05-30
KR20080077150A (en) 2008-08-21

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