WO2007061482A3 - Memory interface to bridge memory buses - Google Patents

Memory interface to bridge memory buses Download PDF

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Publication number
WO2007061482A3
WO2007061482A3 PCT/US2006/034831 US2006034831W WO2007061482A3 WO 2007061482 A3 WO2007061482 A3 WO 2007061482A3 US 2006034831 W US2006034831 W US 2006034831W WO 2007061482 A3 WO2007061482 A3 WO 2007061482A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
interface
bridge
buses
memory interface
Prior art date
Application number
PCT/US2006/034831
Other languages
French (fr)
Other versions
WO2007061482A2 (en
Inventor
Larry Wu
Gang Shan
Stephen Tai
Howard Yang
Zhen-Dong Guo
Original Assignee
Montage Technology Group Ltd
Larry Wu
Gang Shan
Stephen Tai
Howard Yang
Zhen-Dong Guo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/281,211 external-priority patent/US7368950B2/en
Priority claimed from US11/277,650 external-priority patent/US7558124B2/en
Application filed by Montage Technology Group Ltd, Larry Wu, Gang Shan, Stephen Tai, Howard Yang, Zhen-Dong Guo filed Critical Montage Technology Group Ltd
Priority to EP06803101A priority Critical patent/EP1949380A2/en
Publication of WO2007061482A2 publication Critical patent/WO2007061482A2/en
Publication of WO2007061482A3 publication Critical patent/WO2007061482A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Abstract

A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.
PCT/US2006/034831 2005-11-16 2006-09-08 Memory interface to bridge memory buses WO2007061482A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06803101A EP1949380A2 (en) 2005-11-16 2006-09-08 Memory interface to bridge memory buses

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/281,211 2005-11-16
US11/281,211 US7368950B2 (en) 2005-11-16 2005-11-16 High speed transceiver with low power consumption
US11/277,650 US7558124B2 (en) 2005-11-16 2006-03-28 Memory interface to bridge memory buses
US11/277,650 2006-03-28
US11/463,822 US7577039B2 (en) 2005-11-16 2006-08-10 Memory interface to bridge memory buses
US11/463,822 2006-08-10

Publications (2)

Publication Number Publication Date
WO2007061482A2 WO2007061482A2 (en) 2007-05-31
WO2007061482A3 true WO2007061482A3 (en) 2009-04-16

Family

ID=38067685

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/034831 WO2007061482A2 (en) 2005-11-16 2006-09-08 Memory interface to bridge memory buses

Country Status (4)

Country Link
US (1) US7577039B2 (en)
EP (1) EP1949380A2 (en)
TW (1) TW200741461A (en)
WO (1) WO2007061482A2 (en)

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Also Published As

Publication number Publication date
TW200741461A (en) 2007-11-01
EP1949380A2 (en) 2008-07-30
WO2007061482A2 (en) 2007-05-31
US20070162670A1 (en) 2007-07-12
US7577039B2 (en) 2009-08-18

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