WO2007062383A3 - Integration of pore sealing liner into dual-damascene methods and devices - Google Patents

Integration of pore sealing liner into dual-damascene methods and devices Download PDF

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Publication number
WO2007062383A3
WO2007062383A3 PCT/US2006/061185 US2006061185W WO2007062383A3 WO 2007062383 A3 WO2007062383 A3 WO 2007062383A3 US 2006061185 W US2006061185 W US 2006061185W WO 2007062383 A3 WO2007062383 A3 WO 2007062383A3
Authority
WO
WIPO (PCT)
Prior art keywords
sealing liner
pore sealing
integration
dual
devices
Prior art date
Application number
PCT/US2006/061185
Other languages
French (fr)
Other versions
WO2007062383A8 (en
WO2007062383A2 (en
Inventor
Edward Raymond Engbrecht
Rao Satyavolu Srinivas Papa
Sameer Kumar Ajmera
Stephan Grunow
Original Assignee
Texas Instruments Inc
Edward Raymond Engbrecht
Rao Satyavolu Srinivas Papa
Sameer Kumar Ajmera
Stephan Grunow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc, Edward Raymond Engbrecht, Rao Satyavolu Srinivas Papa, Sameer Kumar Ajmera, Stephan Grunow filed Critical Texas Instruments Inc
Priority to JP2008542516A priority Critical patent/JP2009519587A/en
Priority to CN2006800434841A priority patent/CN101443894B/en
Publication of WO2007062383A2 publication Critical patent/WO2007062383A2/en
Publication of WO2007062383A8 publication Critical patent/WO2007062383A8/en
Publication of WO2007062383A3 publication Critical patent/WO2007062383A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners

Abstract

A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect (302) is formed over the semiconductor body. A dielectric layer (308) is formed over the metal interconnect layer. A conductive trench feature (316) and a conductive via feature (314) are formed in the dielectric layer. A pore sealing liner (318) is formed only along a sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.
PCT/US2006/061185 2005-11-23 2006-11-22 Integration of pore sealing liner into dual-damascene methods and devices WO2007062383A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008542516A JP2009519587A (en) 2005-11-23 2006-11-22 Integration of pore sealing liners into dual damascene methods and devices
CN2006800434841A CN101443894B (en) 2005-11-23 2006-11-22 Methods and devices for integration of pore sealing liner into dual-damascene

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/286,877 US7338893B2 (en) 2005-11-23 2005-11-23 Integration of pore sealing liner into dual-damascene methods and devices
US11/286,877 2005-11-23

Publications (3)

Publication Number Publication Date
WO2007062383A2 WO2007062383A2 (en) 2007-05-31
WO2007062383A8 WO2007062383A8 (en) 2008-08-14
WO2007062383A3 true WO2007062383A3 (en) 2008-12-04

Family

ID=38054113

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/061185 WO2007062383A2 (en) 2005-11-23 2006-11-22 Integration of pore sealing liner into dual-damascene methods and devices

Country Status (4)

Country Link
US (1) US7338893B2 (en)
JP (1) JP2009519587A (en)
CN (1) CN101443894B (en)
WO (1) WO2007062383A2 (en)

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EP1989733A1 (en) * 2006-02-28 2008-11-12 STMicroelectronics (Crolles 2) SAS Metal interconnects in a dielectric material
US7432195B2 (en) * 2006-03-29 2008-10-07 Tokyo Electron Limited Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features
US7473634B2 (en) * 2006-09-28 2009-01-06 Tokyo Electron Limited Method for integrated substrate processing in copper metallization
US7759244B2 (en) * 2007-05-10 2010-07-20 United Microelectronics Corp. Method for fabricating an inductor structure or a dual damascene structure
KR100950553B1 (en) * 2007-08-31 2010-03-30 주식회사 하이닉스반도체 Method for forming contact in semiconductor device
JP2009147096A (en) * 2007-12-14 2009-07-02 Panasonic Corp Semiconductor device and method of manufacturing same
US8236684B2 (en) * 2008-06-27 2012-08-07 Applied Materials, Inc. Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer
US7910491B2 (en) * 2008-10-16 2011-03-22 Applied Materials, Inc. Gapfill improvement with low etch rate dielectric liners
JP5173863B2 (en) * 2009-01-20 2013-04-03 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP2010287831A (en) * 2009-06-15 2010-12-24 Renesas Electronics Corp Semiconductor device and method for manufacturing the same
DE102009031156B4 (en) * 2009-06-30 2012-02-02 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Semiconductor device with non-insulating strained material layers in a contact plane and method for its production
CN102412192A (en) * 2011-05-23 2012-04-11 上海华力微电子有限公司 Process method for metal interconnection sidewall mending
US20130341762A1 (en) * 2012-06-20 2013-12-26 Macronix International Co., Ltd. Semiconductor hole structure
CN104412376B (en) * 2012-07-17 2017-02-08 三井化学株式会社 Semiconductor device and method for manufacturing same, and rinsing fluid
CN105097658B (en) * 2014-05-15 2018-05-25 中芯国际集成电路制造(上海)有限公司 The production method of semiconductor devices, interconnection layer and interconnection layer
CN104152863B (en) * 2014-08-27 2019-10-25 上海华力微电子有限公司 A method of it improving cobalt barrier deposition and selects ratio
CN105990218A (en) * 2015-01-30 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
KR20160116618A (en) 2015-03-30 2016-10-10 삼성전자주식회사 A semiconductor device and method of manufacturing the semiconductor device
US20160300757A1 (en) * 2015-04-07 2016-10-13 Applied Materials, Inc. Dielectric constant recovery
US9536826B1 (en) 2015-06-15 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (finFET) device structure with interconnect structure
US20190109090A1 (en) * 2017-08-15 2019-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure lined by isolation layer
CN109411358B (en) * 2017-08-15 2023-03-17 台湾积体电路制造股份有限公司 Isolation layer lined interconnect structure and semiconductor device
US10629478B2 (en) 2017-08-22 2020-04-21 International Business Machines Corporation Dual-damascene formation with dielectric spacer and thin liner
US10964587B2 (en) 2018-05-21 2021-03-30 Tokyo Electron Limited Atomic layer deposition for low-K trench protection during etch
US11004773B2 (en) * 2019-04-23 2021-05-11 Sandisk Technologies Llc Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same
US11004736B2 (en) 2019-07-19 2021-05-11 International Business Machines Corporation Integrated circuit having a single damascene wiring network
US11164815B2 (en) * 2019-09-28 2021-11-02 International Business Machines Corporation Bottom barrier free interconnects without voids
CN111490005A (en) * 2020-05-26 2020-08-04 上海华虹宏力半导体制造有限公司 Gap filling method, flash memory manufacturing method and semiconductor structure

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US6836017B2 (en) * 2002-04-04 2004-12-28 Advanced Micro Devices, Inc. Protection of low-k ILD during damascene processing with thin liner

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US6836017B2 (en) * 2002-04-04 2004-12-28 Advanced Micro Devices, Inc. Protection of low-k ILD during damascene processing with thin liner

Also Published As

Publication number Publication date
JP2009519587A (en) 2009-05-14
US20070117371A1 (en) 2007-05-24
CN101443894A (en) 2009-05-27
US7338893B2 (en) 2008-03-04
WO2007062383A8 (en) 2008-08-14
CN101443894B (en) 2012-05-30
WO2007062383A2 (en) 2007-05-31

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