WO2007067954A3 - Thermal enhanced upper and dual heat sink exposed molded leadless package - Google Patents

Thermal enhanced upper and dual heat sink exposed molded leadless package Download PDF

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Publication number
WO2007067954A3
WO2007067954A3 PCT/US2006/061745 US2006061745W WO2007067954A3 WO 2007067954 A3 WO2007067954 A3 WO 2007067954A3 US 2006061745 W US2006061745 W US 2006061745W WO 2007067954 A3 WO2007067954 A3 WO 2007067954A3
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WO
WIPO (PCT)
Prior art keywords
heat sink
base
dual heat
leadless package
planar
Prior art date
Application number
PCT/US2006/061745
Other languages
French (fr)
Other versions
WO2007067954A2 (en
Inventor
Chung-Lin Wu
Original Assignee
Fairchild Semiconductor
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Publication date
Application filed by Fairchild Semiconductor filed Critical Fairchild Semiconductor
Publication of WO2007067954A2 publication Critical patent/WO2007067954A2/en
Publication of WO2007067954A3 publication Critical patent/WO2007067954A3/en

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above th plane of the base 11 by four sloped walls 13, 1-13.4. The walls slope at an acute angl with reaped, to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
PCT/US2006/061745 2005-12-09 2006-12-07 Thermal enhanced upper and dual heat sink exposed molded leadless package WO2007067954A2 (en)

Applications Claiming Priority (2)

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US11/299,270 2005-12-09
US11/299,270 US7468548B2 (en) 2005-12-09 2005-12-09 Thermal enhanced upper and dual heat sink exposed molded leadless package

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WO2007067954A2 WO2007067954A2 (en) 2007-06-14
WO2007067954A3 true WO2007067954A3 (en) 2008-06-05

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TW (1) TW200739842A (en)
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Also Published As

Publication number Publication date
US7468548B2 (en) 2008-12-23
US20110124158A1 (en) 2011-05-26
US7968982B2 (en) 2011-06-28
WO2007067954A2 (en) 2007-06-14
US8278742B2 (en) 2012-10-02
US20070132091A1 (en) 2007-06-14
TW200739842A (en) 2007-10-16
US20090072362A1 (en) 2009-03-19

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