WO2007071285A1 - Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same - Google Patents

Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same Download PDF

Info

Publication number
WO2007071285A1
WO2007071285A1 PCT/EP2005/057026 EP2005057026W WO2007071285A1 WO 2007071285 A1 WO2007071285 A1 WO 2007071285A1 EP 2005057026 W EP2005057026 W EP 2005057026W WO 2007071285 A1 WO2007071285 A1 WO 2007071285A1
Authority
WO
WIPO (PCT)
Prior art keywords
channels
package
compound
connective material
paths
Prior art date
Application number
PCT/EP2005/057026
Other languages
French (fr)
Inventor
Robert Bauer
Anton Kolbeck
Original Assignee
Freescale Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor, Inc. filed Critical Freescale Semiconductor, Inc.
Priority to CN2005800523569A priority Critical patent/CN101385139B/en
Priority to PCT/EP2005/057026 priority patent/WO2007071285A1/en
Priority to US12/158,393 priority patent/US8004069B2/en
Priority to TW095147983A priority patent/TWI389222B/en
Publication of WO2007071285A1 publication Critical patent/WO2007071285A1/en
Priority to US13/182,137 priority patent/US8283762B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This invention relates to lead frame based semiconductor packages and a method of manufacturing the same, in particular the invention relates to a lead frame based over-molded semiconductor package with patterning on the exposed pad and a method of manufacturing the same, to improve the attachment of semiconductor packages to printed circuit boards, substrates or any other circuit or semiconductor element.
  • FIG. 1 shows an example of a package assembly indicating 5 areas 100, 102, 104, 106, 108 where there are solder voids which may impact the performance of the package in some respect or another.
  • a die to be mounted is mounted on a plurality of die attached pads which are completely separate from one another. This would provide a relatively low thermal mass in the die attach area.
  • the described method uses an epoxy material in the die attached process which would not allow this method to be used in power applications.
  • the patent also discloses a complicated set of steps, including several etch back steps after molding which require special processes during production. This is generally not very efficient or desirable.
  • Figure 1 is a prior art diagram showing the nature of the problem solved by the present invention.
  • Figure 2 is a diagram of the body structure of an exposed pad in accordance with one embodiment of the invention, given by way of example.
  • Figure 3 is a diagram of the body structure of an exposed pad in accordance with another embodiment of the invention, given by way of example.
  • Figure 4 is a body structure of an exposed pad in accordance with a further embodiment of the invention, given by way of example.
  • Figure 5 is a side view of figure 4.
  • Figure 6 is a detailed top view of figure 4.
  • Figure 7 is a diagram of a package with an exposed pad featuring the cross hatch trench or grid pattern in accordance with an embodiment of the present invention, given by way of example.
  • Figure 8 is a package featuring a cross hatch trench pattern on the exposed pad in accordance of another embodiment of the invention, given by way of example.
  • Figure 9 is a cross section of a package with the pattern exposed pad of figure 2 in accordance with an embodiment of the invention, given by way of example.
  • Figure 10 is a cross section of a package with the cross hatch trench pattern exposed pad as shown in figure 3 in accordance with an embodiment of the invention, given by way of example.
  • Figure 1 1 is a cross section of a package with cross hatch trench pattern exposed pads as shown in figure 2, assembled on a printed circuit board with mirrored pattern on the PCB in accordance with an embodiment of the invention, given by way of example.
  • Figure 12 is a diagram showing the manufacturing process for a typical package in accordance with an embodiment of the present invention, given by way of example.
  • Figure 13 is a diagram showing various manufacturing process steps which may be used for a typical package in accordance with an embodiment of the present invention, given by way of example.
  • Figure 2 shows the outside surface of a die flag of a lead frame 200.
  • the lead frame is basically the substrate or "back bone" carrier of a package.
  • the lead frame is typically metallic and conductive, although not always so.
  • the lead frame includes a die flag which carries semiconductor chips.
  • the surface of the package according to an embodiment of the present invention includes a pattern of rows 202 and columns 204 of channels or trenches on the surface. The rows and columns form a regular grid pattern.
  • Figure 2 shows four rows and five columns and the grid pattern defines thereby a plurality of squares or pedestals 206.
  • Figure 2 shows one particular orientation of grid that may be patterned onto the surface of the package. It would be clear however that other patterns are equally applicable. For example, other grid orientations, curves, spirals or whatever, as long as the channels lead towards the edge of the package or away from any area which will form a potential joint in the future.
  • the cross hatch trench pattern or grid of channels on the exposed pad of the outside of the lead frame can be made in a number of different ways. This includes hatching, milling, punching or other appropriate machining procedures during the manufacturing process of the lead frame itself.
  • the way in which the grid of channels is produced could be of any appropriate type for all the various embodiments of the present invention described herein.
  • Lead frame 300 includes rows 302 and columns 304 of channels which define a grid having a number of pedestals 306. This embodiment is essentially similar to that shown in figure 2. However, the embodiment of figure 3 shows also a mold lock feature on the pad edge 308. The mold lock feature provides an enhanced mechanical interlocking between the lead frame and a molding compound in the process for manufacturing the package. SC14318EM-PCT spec Vfinal - 5 -
  • a grid of channels is shown patterned onto the exposed pad of the body structure of the lead frame but includes in this case a stiffening feature.
  • the body structure 400 includes rows 402 and columns 404 of channels as in either of figures 2 and 3. Pedestals or squares 406 are defined as previously indicated.
  • stiffening feature 408 In each channel (either rows or columns) there is a stiffening feature 408, this is shown in cross-section in figure 5 and from above in figure 6.
  • stiffening feature 408 is arcuate in cross sectional view. This means there is less chance of relative movement between the two squares or pedestals 406 of the lead frame package, thereby strengthening the package overall. It will be appreciated that other shapes of stiffening feature will provide the same advantages and this invention is not limited to the stiffener feature being arcuate.
  • stiffening feature 408 is shown between respective squares or pedestals 406 and includes a broader section closer to the pedestals and a narrower section in the central part of the channel 404 or 402. This shape is defined herein as bow shaped.
  • the stiffening feature is an integral part of the exposed pad (i.e. it is made from the same piece of material as the other leadframe features) and is manufactured/shaped during the lead frame manufacturing process using the same methods that are used to form the body structure of the exposed pad.
  • a typical package is shown with a plurality of connectors 700 and on the surface of the exposed pad of the lead frame 702 a grid pattern 704 as previously described with respect to other embodiments and drawings.
  • a package 800 is shown having a plurality of connectors 802.
  • the package includes a number of lead frame components or other devices such as an input/output (I/O) 802, 804 etc.
  • Each of the exposed pads 806 of the lead frame or devices include the grid patterning of channels on the surface thereof as previously indicated in other embodiments and drawings. It is preferred that the exposed pad should be patterned only on the outside of the package. This thus SC14318EM-PCT spec Vfinal - 6 -
  • Figure 9 shows a package 900 which includes a lead frame having an exposed pad 902 which has channels 904 therein.
  • the channels are formed in rows and columns as previously described but are not shown here as such.
  • the package further includes: multiple input/output (I/O) pads, two of which 906 and 908 are shown, in this example a power die 910; and between the power die and the lead frame a layer of die attach material such as solder, conductive epoxy or any other applicable die attach material 912.
  • I/O input/output
  • mold compound 914 which is typically in the form of an epoxy compound.
  • the mold compound enters into the channels 904 during the process of application thereof.
  • the mold compound is indicated as being an epoxy material and of course could be any other appropriate material.
  • the mold compound encapsulated package may then be soldered onto a printed circuit board (PCB) 916 using a solder joint 918, which may be formed between the PCB and any device thereon.
  • the patterned surface of the lead frame as previously described is a metallic surface whilst the channels are filled with the epoxy mold compound or any other appropriate material. Solder is unable to adhere to such epoxy materials and as a result a channel or path 920 is formed in the solder joint 918 at a position which corresponds to the mold filled channels in the lead frame.
  • These channels 920 allow for continuous out gassing of entrapped air during the reflow process in which the solder is applied. In fact, the air or other waste products from the solder process are moved away from the joint area by means of the channels. This means that there is less likelihood that the solder joint between the PCB and the lead frame is compromised and includes voids.
  • SC14318EM-PCT spec Vfinal - 7 -
  • the material in the channels this may be the mold compound or any other material if the mold compound does not have the right properties for the function required.
  • This function is that to some degree the compound is not wetted by the solder. This may be achieved by selecting the compound to have a lower wettability index with solder than the wettability of the rest of the pad. It is important that the material in the channels is not wetted by the solder in order that channels 920 are produced in the solder.
  • wetting, wettability and to wet should all be interpreted in the broadest sense and includes bonding strength and adhesion strength. It will be appreciated that the non wetting between the solder and mold compound may be achieved by using various combinations of materials. For example a connecting material other than solder may be used with a compound in the channels which does not show a high level of wettability to that connecting material. Alternatively, the two materials may react chemically to form the channels or paths in the connecting material. Also for certain materials wettability may not be the relevant factor but instead perhaps adhesion ability or bonding strength may be more relevant.
  • Figure 9 does not show all the details of connections between various elements of the package, but it will be appreciated the leads, vias, bonds and other connection means can be utilized to effect any electrical connection. Similarly other insulating materials can be used to electrically isolate various components. Also any combination of devices, pads, dies etc can be used as required for the desired package.
  • One of the advantages of this invention is that it allows the assembly of exposed pad packages or equivalent with a minimum voiding level in the board attached solder joints thereby securing optimized thermal and electrical onboard performance of the package.
  • a relatively high thermal mass is provided using a full pad for die attached at the die side. Because solder may be used the die may be attached as required in power applications.
  • Another advantage of the present invention is that the board attached solder voiding levels are minimized thereby allowing a greater percentage of the packages to be supplied at the highest level of quality. This would be applicable to all lead frame based over molded semiconductor packages with exposed pads.
  • Another advantage of the invention includes patterning of the exterior surface of a large lead frame heat sink to minimize the possibility of large voids by reducing the area to wet by solder.
  • FIG 10 a further embodiment of packages is shown.
  • This package 900 is essentially identical to that in figure 9 with the exception that the lead frame as shown in figure 3 is utilized in figure 10 (whilst that of figure 2 is utilized in figure 9).
  • the lead frame of figure 3 includes the mold lock feature 308. This is shown in figure 10 as mold lock area 922. As can be seen this allows mold compound to surround the lead frame and allows enhanced mechanical interlocking between the lead frame and the mold compound. This will generally ensure the package has a longer lifespan.
  • Figure 1 1 shows a further embodiment which is essentially similar to that of figure 9 and where common elements are numbered with the same number. The difference in this embodiment is that the contact surface 1 100 of the PCB 916 has been patterned with a grid of channels (not shown) and processed in the same manner as the channels on the lead frame, to define augmented channels or paths
  • channels 1 102 in the solder are augmentations in the illustrated example as they are formed in a corresponding position to those on the lead frame and are substantially aligned therewith. However, it will be appreciated that the position of any channels associated with the PCB may be different from those on the lead frame.
  • the channels on the PCB surface may also be treated prior to the soldering process such that they contain material which is not wetted by the solder thereby accentuating the solder channels 920 and thus thereby ensuring the out-gassing and other advantages of the invention.
  • a pattern of channels is applied to the exposed pad of a lead frame using any appropriate process for the lead frame and pattern that are required. Examples of the processes include, but are not limited to etching the channels, milling the channels, pressing or punching the channels etc (1200).
  • the various components to be connected to the lead frame may then be attached on the non patterned surface of the lead frame if required.
  • These components will typically be those which form part of a package that is to be mold encapsulated to some degree or another. The exact nature of the components will depend on the device and the ultimate use of the resulting package (1202).
  • a mold compound is then applied to the various components of the package (1204). This process can be carried out in various different ways including mold pressing or other mold compound application methods. It is important that mold compound settles into the channels on the lead frame to some extent.
  • the package is then completed as appropriate for the use required. This may include removal of some of the mold compound from certain areas for connections, addition of leads, etc. to be included (1206).
  • the package is then attached to a PCB or other device using a soldering process (1208).
  • the presence of the mold compound in the channels ensures that adequate egress of air (out-gassing) and other gases or waste material formed during the solder process is achieved due to the presence of the channels and the formation of the paths. This means that the solder will "wet" a greater proportion of the lead frame and/or PCB to thereby minimize the likelihood of voids being SC14318EM-PCTsp ⁇ c Vf ⁇ nal - 1 0 -
  • the PCB or other device may also be processed to include mold filled channels, as previously described.
  • the invention provides an easy method of implementation. This is due to the fact that these lead framed types are manufactured in an etching process and the patterning of channels on the exposed pads can be done in the same process without having additional steps to the overall process.
  • the manufacturing process of the package may include further steps that are common place in the environment of manufacturing a semiconductor package.
  • Figure 13 show one example of a set of steps but there are many other variations.
  • a single lead frame or a set (i.e. matrix) of lead frames 1300/1302 is manufactured and patterned with one or more channels on the exposed pads thereof (1350).
  • One or more different silicon wafers are split into single semiconductor dies by sawing or other appropriate means and are inspected (1352).
  • Die solder paste or any other appropriate die attach material (1304) is applied (1354), the semiconductor die(s) is/are placed into the die attach material, and then cured or reflowed.
  • a de-flux and Dl-Water rinse step may then be carried out (1356). If required an epoxy or any other appropriate die attach material is applied (1358), additional semiconductor dies are placed into the die attach material and/or a die attach cure is carried out (1360).
  • a tape (1306) is attached to the lead frames (1362) and wire bonds (1308) are applied (1364).
  • a visual check is carried out (1366).
  • a molding compound (1310) is applied (1368) and the tape is removed (1370).
  • a post mold cure (1372) and laser marking (1374) steps are followed by a cleaning stage (1376).
  • the package is then split into individual elements (1378) and inspected (1380).

Abstract

A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterised in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface.

Description

SC14318EM-PCTspβc Vfιnal - 1 -
20 December 2005
Title: Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same.
Description
Field of the invention
This invention relates to lead frame based semiconductor packages and a method of manufacturing the same, in particular the invention relates to a lead frame based over-molded semiconductor package with patterning on the exposed pad and a method of manufacturing the same, to improve the attachment of semiconductor packages to printed circuit boards, substrates or any other circuit or semiconductor element.
Background of the invention
Semiconductor packages with an exposed pad or other surfaces for attachment tend to sustain heavy solder voiding levels in the exposed package area during PCB attachment. Such voiding on the pad solder joint can have adverse effects on the thermal performance of the package. In addition, changes to the electrical and thermal path within the completed solder contact can impact certain other applications as well. In certain circumstances, depending on the location of the solder voids, this can result in the completed assembly achieving below desired board performance levels. An example of such a circumstance is when large voids occur directly underneath the position of a semiconductor die. Figure 1 shows an example of a package assembly indicating 5 areas 100, 102, 104, 106, 108 where there are solder voids which may impact the performance of the package in some respect or another.
There have been a number of proposals of methods to attempt to combat this problem. A commonly accepted industrial practice to overcome these problems has involved putting patterns in a solder paste deposit or patterns of the die attached flag inside the package. SC14318EM-PCT spec Vfinal - 2 -
20 December 2005
US 6,872,661 B1 (leadless plastic chip carrier with etch back pad singulation and a die attached pad array) describes a package which is built from a plurality of single die attached pads and contact pads which attempts to solve some of the problems identified above. However the patent does not resolve these problems for the following reasons:
- A die to be mounted is mounted on a plurality of die attached pads which are completely separate from one another. This would provide a relatively low thermal mass in the die attach area.
- The described method uses an epoxy material in the die attached process which would not allow this method to be used in power applications.
- The patent also discloses a complicated set of steps, including several etch back steps after molding which require special processes during production. This is generally not very efficient or desirable.
Summary of the invention The present invention provides a method of manufacturing a semiconductor package and such a package as described in the accompanying claims.
Brief description of the drawings
Reference will now be made, by way of example, to the accompanying drawings, in which:
Figure 1 is a prior art diagram showing the nature of the problem solved by the present invention.
Figure 2 is a diagram of the body structure of an exposed pad in accordance with one embodiment of the invention, given by way of example.
Figure 3 is a diagram of the body structure of an exposed pad in accordance with another embodiment of the invention, given by way of example.
Figure 4 is a body structure of an exposed pad in accordance with a further embodiment of the invention, given by way of example. SC14318EM-PCT spec Vfinal - 3 -
20 December 2005
Figure 5 is a side view of figure 4.
Figure 6 is a detailed top view of figure 4.
Figure 7 is a diagram of a package with an exposed pad featuring the cross hatch trench or grid pattern in accordance with an embodiment of the present invention, given by way of example.
Figure 8 is a package featuring a cross hatch trench pattern on the exposed pad in accordance of another embodiment of the invention, given by way of example.
Figure 9 is a cross section of a package with the pattern exposed pad of figure 2 in accordance with an embodiment of the invention, given by way of example.
Figure 10 is a cross section of a package with the cross hatch trench pattern exposed pad as shown in figure 3 in accordance with an embodiment of the invention, given by way of example.
Figure 1 1 is a cross section of a package with cross hatch trench pattern exposed pads as shown in figure 2, assembled on a printed circuit board with mirrored pattern on the PCB in accordance with an embodiment of the invention, given by way of example.
Figure 12 is a diagram showing the manufacturing process for a typical package in accordance with an embodiment of the present invention, given by way of example.
Figure 13 is a diagram showing various manufacturing process steps which may be used for a typical package in accordance with an embodiment of the present invention, given by way of example. SC14318EM-PCT spec Vfinal - 4 -
20 December 2005
Detailed description of the preferred embodiments
Figure 2 shows the outside surface of a die flag of a lead frame 200. The lead frame is basically the substrate or "back bone" carrier of a package. The lead frame is typically metallic and conductive, although not always so. The lead frame includes a die flag which carries semiconductor chips. The surface of the package according to an embodiment of the present invention includes a pattern of rows 202 and columns 204 of channels or trenches on the surface. The rows and columns form a regular grid pattern. Figure 2 shows four rows and five columns and the grid pattern defines thereby a plurality of squares or pedestals 206. Figure 2 shows one particular orientation of grid that may be patterned onto the surface of the package. It would be clear however that other patterns are equally applicable. For example, other grid orientations, curves, spirals or whatever, as long as the channels lead towards the edge of the package or away from any area which will form a potential joint in the future.
The cross hatch trench pattern or grid of channels on the exposed pad of the outside of the lead frame can be made in a number of different ways. This includes hatching, milling, punching or other appropriate machining procedures during the manufacturing process of the lead frame itself. The way in which the grid of channels is produced could be of any appropriate type for all the various embodiments of the present invention described herein.
The function of the channels forming the grid i.e. the rows and columns will be described in greater detail below, as will the need for them to extend away from the joint area.
Referring to figure 3 a second embodiment of the package is shown. Lead frame 300 includes rows 302 and columns 304 of channels which define a grid having a number of pedestals 306. This embodiment is essentially similar to that shown in figure 2. However, the embodiment of figure 3 shows also a mold lock feature on the pad edge 308. The mold lock feature provides an enhanced mechanical interlocking between the lead frame and a molding compound in the process for manufacturing the package. SC14318EM-PCT spec Vfinal - 5 -
20 December 2005
In another embodiment of the present invention shown in figures 4, 5 and 6 a grid of channels is shown patterned onto the exposed pad of the body structure of the lead frame but includes in this case a stiffening feature. Referring initially to figure 4, the body structure 400 includes rows 402 and columns 404 of channels as in either of figures 2 and 3. Pedestals or squares 406 are defined as previously indicated. In each channel (either rows or columns) there is a stiffening feature 408, this is shown in cross-section in figure 5 and from above in figure 6. As is shown in figure 5, stiffening feature 408 is arcuate in cross sectional view. This means there is less chance of relative movement between the two squares or pedestals 406 of the lead frame package, thereby strengthening the package overall. It will be appreciated that other shapes of stiffening feature will provide the same advantages and this invention is not limited to the stiffener feature being arcuate.
Referring now to figure 6 the form of the stiffening feature 408 is shown between respective squares or pedestals 406 and includes a broader section closer to the pedestals and a narrower section in the central part of the channel 404 or 402. This shape is defined herein as bow shaped. The stiffening feature is an integral part of the exposed pad (i.e. it is made from the same piece of material as the other leadframe features) and is manufactured/shaped during the lead frame manufacturing process using the same methods that are used to form the body structure of the exposed pad.
Referring now to figure 7, a typical package is shown with a plurality of connectors 700 and on the surface of the exposed pad of the lead frame 702 a grid pattern 704 as previously described with respect to other embodiments and drawings. Similarly in figure 8 a package 800 is shown having a plurality of connectors 802. The package includes a number of lead frame components or other devices such as an input/output (I/O) 802, 804 etc. Each of the exposed pads 806 of the lead frame or devices include the grid patterning of channels on the surface thereof as previously indicated in other embodiments and drawings. It is preferred that the exposed pad should be patterned only on the outside of the package. This thus SC14318EM-PCT spec Vfinal - 6 -
20 December 2005
provides a full cover pad on the side of the package for die attach as will be described in another part of the specification.
Referring now to figures 9, 10 and 1 1 more details of the orientation of the lead frame in the packages and how the channels overcome the problems of the prior art are described.
Figure 9 shows a package 900 which includes a lead frame having an exposed pad 902 which has channels 904 therein. The channels are formed in rows and columns as previously described but are not shown here as such. The package further includes: multiple input/output (I/O) pads, two of which 906 and 908 are shown, in this example a power die 910; and between the power die and the lead frame a layer of die attach material such as solder, conductive epoxy or any other applicable die attach material 912.
All the above described elements of the package are encased in mold compound 914 which is typically in the form of an epoxy compound. The mold compound enters into the channels 904 during the process of application thereof. The mold compound is indicated as being an epoxy material and of course could be any other appropriate material.
The mold compound encapsulated package may then be soldered onto a printed circuit board (PCB) 916 using a solder joint 918, which may be formed between the PCB and any device thereon. The patterned surface of the lead frame as previously described is a metallic surface whilst the channels are filled with the epoxy mold compound or any other appropriate material. Solder is unable to adhere to such epoxy materials and as a result a channel or path 920 is formed in the solder joint 918 at a position which corresponds to the mold filled channels in the lead frame. These channels 920 allow for continuous out gassing of entrapped air during the reflow process in which the solder is applied. In fact, the air or other waste products from the solder process are moved away from the joint area by means of the channels. This means that there is less likelihood that the solder joint between the PCB and the lead frame is compromised and includes voids. SC14318EM-PCT spec Vfinal - 7 -
20 December 2005
For the purposes of the material in the channels this may be the mold compound or any other material if the mold compound does not have the right properties for the function required. This function is that to some degree the compound is not wetted by the solder. This may be achieved by selecting the compound to have a lower wettability index with solder than the wettability of the rest of the pad. It is important that the material in the channels is not wetted by the solder in order that channels 920 are produced in the solder.
The terms wetting, wettability and to wet should all be interpreted in the broadest sense and includes bonding strength and adhesion strength. It will be appreciated that the non wetting between the solder and mold compound may be achieved by using various combinations of materials. For example a connecting material other than solder may be used with a compound in the channels which does not show a high level of wettability to that connecting material. Alternatively, the two materials may react chemically to form the channels or paths in the connecting material. Also for certain materials wettability may not be the relevant factor but instead perhaps adhesion ability or bonding strength may be more relevant.
Figure 9 does not show all the details of connections between various elements of the package, but it will be appreciated the leads, vias, bonds and other connection means can be utilized to effect any electrical connection. Similarly other insulating materials can be used to electrically isolate various components. Also any combination of devices, pads, dies etc can be used as required for the desired package.
One of the advantages of this invention is that it allows the assembly of exposed pad packages or equivalent with a minimum voiding level in the board attached solder joints thereby securing optimized thermal and electrical onboard performance of the package. A relatively high thermal mass is provided using a full pad for die attached at the die side. Because solder may be used the die may be attached as required in power applications. SC14318EM-PCT spec Vfinal - 8 -
20 December 2005
Another advantage of the present invention is that the board attached solder voiding levels are minimized thereby allowing a greater percentage of the packages to be supplied at the highest level of quality. This would be applicable to all lead frame based over molded semiconductor packages with exposed pads.
Another advantage of the invention includes patterning of the exterior surface of a large lead frame heat sink to minimize the possibility of large voids by reducing the area to wet by solder.
Referring now to figure 10 a further embodiment of packages is shown. This package 900 is essentially identical to that in figure 9 with the exception that the lead frame as shown in figure 3 is utilized in figure 10 (whilst that of figure 2 is utilized in figure 9). The lead frame of figure 3 includes the mold lock feature 308. This is shown in figure 10 as mold lock area 922. As can be seen this allows mold compound to surround the lead frame and allows enhanced mechanical interlocking between the lead frame and the mold compound. This will generally ensure the package has a longer lifespan.
Figure 1 1 shows a further embodiment which is essentially similar to that of figure 9 and where common elements are numbered with the same number. The difference in this embodiment is that the contact surface 1 100 of the PCB 916 has been patterned with a grid of channels (not shown) and processed in the same manner as the channels on the lead frame, to define augmented channels or paths
1 102 in the solder. These channels are augmentations in the illustrated example as they are formed in a corresponding position to those on the lead frame and are substantially aligned therewith. However, it will be appreciated that the position of any channels associated with the PCB may be different from those on the lead frame. The channels on the PCB surface may also be treated prior to the soldering process such that they contain material which is not wetted by the solder thereby accentuating the solder channels 920 and thus thereby ensuring the out-gassing and other advantages of the invention. SC14318EM-PCT spec Vfinal - 9 -
20 December 2005
Referring now to figure 12 a flow chart showing the main method steps of the manufacturing process are described.
A pattern of channels is applied to the exposed pad of a lead frame using any appropriate process for the lead frame and pattern that are required. Examples of the processes include, but are not limited to etching the channels, milling the channels, pressing or punching the channels etc (1200).
The various components to be connected to the lead frame may then be attached on the non patterned surface of the lead frame if required. These components will typically be those which form part of a package that is to be mold encapsulated to some degree or another. The exact nature of the components will depend on the device and the ultimate use of the resulting package (1202).
A mold compound is then applied to the various components of the package (1204). This process can be carried out in various different ways including mold pressing or other mold compound application methods. It is important that mold compound settles into the channels on the lead frame to some extent.
The package is then completed as appropriate for the use required. This may include removal of some of the mold compound from certain areas for connections, addition of leads, etc. to be included (1206).
The package is then attached to a PCB or other device using a soldering process (1208). The presence of the mold compound in the channels ensures that adequate egress of air (out-gassing) and other gases or waste material formed during the solder process is achieved due to the presence of the channels and the formation of the paths. This means that the solder will "wet" a greater proportion of the lead frame and/or PCB to thereby minimize the likelihood of voids being SC14318EM-PCTspβc Vfιnal - 1 0 -
20 December 2005
formed. The PCB or other device may also be processed to include mold filled channels, as previously described.
For packages with etched lead frames the invention provides an easy method of implementation. This is due to the fact that these lead framed types are manufactured in an etching process and the patterning of channels on the exposed pads can be done in the same process without having additional steps to the overall process.
The manufacturing process of the package may include further steps that are common place in the environment of manufacturing a semiconductor package. Figure 13 show one example of a set of steps but there are many other variations.
A single lead frame or a set (i.e. matrix) of lead frames 1300/1302 is manufactured and patterned with one or more channels on the exposed pads thereof (1350). One or more different silicon wafers are split into single semiconductor dies by sawing or other appropriate means and are inspected (1352). Die solder paste or any other appropriate die attach material (1304) is applied (1354), the semiconductor die(s) is/are placed into the die attach material, and then cured or reflowed. A de-flux and Dl-Water rinse step may then be carried out (1356). If required an epoxy or any other appropriate die attach material is applied (1358), additional semiconductor dies are placed into the die attach material and/or a die attach cure is carried out (1360).
A tape (1306) is attached to the lead frames (1362) and wire bonds (1308) are applied (1364). A visual check is carried out (1366). A molding compound (1310) is applied (1368) and the tape is removed (1370). A post mold cure (1372) and laser marking (1374) steps are followed by a cleaning stage (1376). The package is then split into individual elements (1378) and inspected (1380). SC14318EM-PCTspβc Vfιnal - 1 1 -
20 December 2005
It will be appreciated that the above described invention may include various variations and alternatives which will produce the same advantages as the features herein described, these are hereby included.

Claims

SC14318EM-PCTspβc Vfιnal - 12 -20 December 2005Claims
1. A method of manufacturing a semiconductor package, the package including a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface, the method characterised in that it comprises the steps of :-
- patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface;
- applying a compound to said one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material which correspond to the one or more channels on the surface and which allow the passage of waste material away from the joint area to the outer edge of the surface.
2. The method of claim 1 , characterised in that the method further comprises applying a compound having a wettability less than that of the surface, such that the paths are formed by the none-wetting of the connective material and the compound.
3. The method of claim 1 or claim 2, further comprising:
- forming a fluid layer of the connective material between the package and the device which fluid layer flows away from the compound in the channels to define the paths in the connective material;
-causing said fluid layer to solidify to form said joint; and
-venting any waste products formed during the steps through the paths.
4. The method of any preceding claim, further comprising introducing a strengthening element into the or each channel, wherein the channel has two elongate sides and the strengthening element is introduced at a point between the two sides to prevent movement thereof. SC14318EM-PCTspβc Vfιnal - 13 -
20 December 2005
5. The method of claim 4, further comprising forming the strengthening element to be arcuate in cross-section and bow shaped in plan view.
6. The method of any preceding claim, further comprising applying said compound as part of the step of applying a mold compound to the package to encapsulate the same.
7. The method of claim 6, further comprising pattering an indent at one or more edge of the package surface to provide a surface to which the mold compound can affix to provide an overlapping seal at the edge of the surface.
8. The method of any preceding claim, further comprising attaching one or more devices to the package.
9. The method of any preceding claim, further comprising: -patterning one or more further channels on a surface of any device,
-applying a compound to said one or more further channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the connective material has defined therein one or more further paths which correspond to the one or more further channels on the surface of the device and which allow the passage of waste material away from the joint.
10. The method of claim 9, further comprising forming the channels and further channels to substantially correspond with one another, such that the path and further paths form an augmented path.
1 1 . A semiconductor package comprising a surface for attaching the package to a device by a joint formed of a connective material in a joint area of the surface, characterised in that the package includes:-
-one or more channels on the surface which channels extend away from the joint area;
-a compound which interacts with the connective material substantially located in the or each channel, such that when the semiconductor package is attached to the SC14318EM-PCTspβc Vfιnal - 14 -
20 December 2005
device the connective material has defined therein one or more paths which correspond to the one or more channels on the surface and which allow the passage of waste material away from the joint.
12. The semiconductor package of claim 1 1 , characterised in that the surface is part of a lead frame.
PCT/EP2005/057026 2005-12-21 2005-12-21 Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same WO2007071285A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN2005800523569A CN101385139B (en) 2005-12-21 2005-12-21 Improvement in or related to semiconductor package based on lead frame and manufacturing method
PCT/EP2005/057026 WO2007071285A1 (en) 2005-12-21 2005-12-21 Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same
US12/158,393 US8004069B2 (en) 2005-12-21 2005-12-21 Lead frame based semiconductor package and a method of manufacturing the same
TW095147983A TWI389222B (en) 2005-12-21 2006-12-20 Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same
US13/182,137 US8283762B2 (en) 2005-12-21 2011-07-13 Lead frame based semiconductor package and a method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2005/057026 WO2007071285A1 (en) 2005-12-21 2005-12-21 Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/158,393 A-371-Of-International US7472028B2 (en) 2004-06-25 2005-06-21 Sensor or capacitance measuring with a microprocessor
US13/182,137 Division US8283762B2 (en) 2005-12-21 2011-07-13 Lead frame based semiconductor package and a method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2007071285A1 true WO2007071285A1 (en) 2007-06-28

Family

ID=36084248

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/057026 WO2007071285A1 (en) 2005-12-21 2005-12-21 Improvements in or relating to lead frame based semiconductor package and a method of manufacturing the same

Country Status (4)

Country Link
US (2) US8004069B2 (en)
CN (1) CN101385139B (en)
TW (1) TWI389222B (en)
WO (1) WO2007071285A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018064B2 (en) * 2007-05-31 2011-09-13 Infineon Technologies Ag Arrangement including a semiconductor device and a connecting element

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101179983B1 (en) * 2009-02-23 2012-09-07 한미반도체 주식회사 Method for Generating Laser Beam Radiation Trajectories for Processing Semiconductor Packages
US8718720B1 (en) 2010-07-30 2014-05-06 Triquint Semiconductor, Inc. Die including a groove extending from a via to an edge of the die
DE102014102917B4 (en) * 2013-03-05 2024-01-18 Flextronics Ap, Llc Component with draw-off sections, semiconductor assembly with pressure relief structure and method for preventing pressure build-up in a semiconductor packaging
US9905515B2 (en) * 2014-08-08 2018-02-27 Mediatek Inc. Integrated circuit stress releasing structure
CN107431050B (en) * 2016-01-06 2019-12-13 新电元工业株式会社 mounting table for semiconductor device and in-vehicle apparatus
WO2017119083A1 (en) 2016-01-06 2017-07-13 新電元工業株式会社 Placement base for semiconductor device, and on-vehicle device
US11830810B2 (en) * 2020-05-07 2023-11-28 Wolfspeed, Inc. Packaged transistor having die attach materials with channels and process of implementing the same
US11424177B2 (en) * 2020-05-07 2022-08-23 Wolfspeed, Inc. Integrated circuit having die attach materials with channels and process of implementing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4918511A (en) * 1985-02-01 1990-04-17 Advanced Micro Devices, Inc. Thermal expansion compensated metal lead frame for integrated circuit package
US4924351A (en) * 1985-06-20 1990-05-08 Kabushiki Kaisha Toshiba Recessed thermally conductive packaged semiconductor devices
FR2704114A1 (en) * 1993-04-12 1994-10-21 Fujitsu Ltd Casing structure for an electronic device of the surface-mounting type, and method of mounting such a structure on a printed-wiring board
US6501160B1 (en) * 1999-01-29 2002-12-31 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same and a mount structure
US6777788B1 (en) * 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2970111B2 (en) * 1991-09-19 1999-11-02 日本電気株式会社 Lead frame, semiconductor device and method of manufacturing the same
US5430331A (en) * 1993-06-23 1995-07-04 Vlsi Technology, Inc. Plastic encapsulated integrated circuit package having an embedded thermal dissipator
US6872661B1 (en) * 1998-06-10 2005-03-29 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6821878B2 (en) * 2003-02-27 2004-11-23 Freescale Semiconductor, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
US7364684B2 (en) * 2004-08-16 2008-04-29 Delphi Technologies, Inc. Method of making an encapsulated microelectronic package having fluid carrying encapsulant channels
EP2084744A2 (en) * 2006-10-27 2009-08-05 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7608484B2 (en) * 2006-10-31 2009-10-27 Texas Instruments Incorporated Non-pull back pad package with an additional solder standoff

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4918511A (en) * 1985-02-01 1990-04-17 Advanced Micro Devices, Inc. Thermal expansion compensated metal lead frame for integrated circuit package
US4924351A (en) * 1985-06-20 1990-05-08 Kabushiki Kaisha Toshiba Recessed thermally conductive packaged semiconductor devices
FR2704114A1 (en) * 1993-04-12 1994-10-21 Fujitsu Ltd Casing structure for an electronic device of the surface-mounting type, and method of mounting such a structure on a printed-wiring board
US6501160B1 (en) * 1999-01-29 2002-12-31 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same and a mount structure
US6777788B1 (en) * 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018064B2 (en) * 2007-05-31 2011-09-13 Infineon Technologies Ag Arrangement including a semiconductor device and a connecting element

Also Published As

Publication number Publication date
TW200731428A (en) 2007-08-16
US8283762B2 (en) 2012-10-09
US20090218663A1 (en) 2009-09-03
US8004069B2 (en) 2011-08-23
CN101385139B (en) 2010-06-23
CN101385139A (en) 2009-03-11
TWI389222B (en) 2013-03-11
US20110266663A1 (en) 2011-11-03

Similar Documents

Publication Publication Date Title
US8283762B2 (en) Lead frame based semiconductor package and a method of manufacturing the same
US7507603B1 (en) Etch singulated semiconductor package
US7618849B2 (en) Integrated circuit package with etched leadframe for package-on-package interconnects
US7154186B2 (en) Multi-flip chip on lead frame on over molded IC package and method of assembly
US6664615B1 (en) Method and apparatus for lead-frame based grid array IC packaging
US9130064B2 (en) Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier
US20060170081A1 (en) Method and apparatus for packaging an electronic chip
US7977161B2 (en) Method of manufacturing a semiconductor package using a carrier
KR20160041974A (en) Embedded packaging with preformed vias
KR20050071524A (en) Thermal enhanced package for block mold assembly
US8338924B2 (en) Substrate for integrated circuit package with selective exposure of bonding compound and method of making thereof
JP2010536178A (en) Packaged integrated circuit device with through-body conductive vias and method of manufacturing the same
WO2004017405A1 (en) Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US20180151461A1 (en) Stiffener for fan-out wafer level packaging and method of manufacturing
WO2007117819A2 (en) Molded semiconductor package with integrated through hole heat spreader pin(s)
KR20060042872A (en) A method of surface mounting a semiconductor device
CN106711113B (en) Semiconductor package body with integral fin
US7923835B2 (en) Package, electronic device, substrate having a separation region and a wiring layers, and method for manufacturing
US11430720B2 (en) Recess lead for a surface mount package
KR101753416B1 (en) Leadframe for ic package and method of manufacture
US7560309B1 (en) Drop-in heat sink and exposed die-back for molded flip die package
CN116724396A (en) Area shielding within packages of microelectronic devices
EP1369919A1 (en) Flip chip package
US20080116587A1 (en) Conductor polymer composite carrier with isoproperty conductive columns
US20240071889A1 (en) Recess lead for a surface mount package

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200580052356.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 12158393

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05823674

Country of ref document: EP

Kind code of ref document: A1