WO2007075312A3 - Phase interpolator - Google Patents

Phase interpolator Download PDF

Info

Publication number
WO2007075312A3
WO2007075312A3 PCT/US2006/047110 US2006047110W WO2007075312A3 WO 2007075312 A3 WO2007075312 A3 WO 2007075312A3 US 2006047110 W US2006047110 W US 2006047110W WO 2007075312 A3 WO2007075312 A3 WO 2007075312A3
Authority
WO
WIPO (PCT)
Prior art keywords
phase
signals
signal
coupled
output
Prior art date
Application number
PCT/US2006/047110
Other languages
French (fr)
Other versions
WO2007075312A2 (en
Inventor
Yongping Fan
Ian A Young
Original Assignee
Intel Corp
Yongping Fan
Ian A Young
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Yongping Fan, Ian A Young filed Critical Intel Corp
Priority to CN2006800425486A priority Critical patent/CN101310440B/en
Priority to EP06839275.2A priority patent/EP1966887B1/en
Publication of WO2007075312A2 publication Critical patent/WO2007075312A2/en
Publication of WO2007075312A3 publication Critical patent/WO2007075312A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/16—Networks for phase shifting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Abstract

A phase interpolator includes a first circuit to generate a first signal (PHINO) having a first phase delay and a second signal (PHINl) having a second phase delay and a phase mixer (105). The phase mixer (105) is coupled to receive the first and second signals from the first circuit. The phase mixer (105) includes multiple current drivers (510) each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs (01) of the current drivers (510) are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first (PHINO) and second signals. (phinl)
PCT/US2006/047110 2005-12-27 2006-12-08 Phase interpolator WO2007075312A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800425486A CN101310440B (en) 2005-12-27 2006-12-08 Phase interpolator
EP06839275.2A EP1966887B1 (en) 2005-12-27 2006-12-08 Phase interpolator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/319,879 US7593496B2 (en) 2005-12-27 2005-12-27 Phase interpolator
US11/319,879 2005-12-27

Publications (2)

Publication Number Publication Date
WO2007075312A2 WO2007075312A2 (en) 2007-07-05
WO2007075312A3 true WO2007075312A3 (en) 2008-04-03

Family

ID=38193728

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/047110 WO2007075312A2 (en) 2005-12-27 2006-12-08 Phase interpolator

Country Status (5)

Country Link
US (1) US7593496B2 (en)
EP (1) EP1966887B1 (en)
CN (1) CN101310440B (en)
TW (1) TWI331452B (en)
WO (1) WO2007075312A2 (en)

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US7593496B2 (en) 2005-12-27 2009-09-22 Intel Corporation Phase interpolator
US8086209B2 (en) * 2007-10-29 2011-12-27 Broadcom Corporation Method and apparatus for frequency mixing of radio frequency signals
TWI420818B (en) * 2009-03-10 2013-12-21 Realtek Semiconductor Corp Method and apparatus for preventing phase interpolation circuit from glitch during clock switching
CN101692608B (en) * 2009-08-03 2012-04-04 四川和芯微电子股份有限公司 High linearity variable bit width interpolator
CN101834715B (en) * 2010-04-26 2013-06-05 华为技术有限公司 Data processing method, data processing system and data processing device
US8559587B1 (en) 2012-03-21 2013-10-15 Integrated Device Technology, Inc Fractional-N dividers having divider modulation circuits therein with segmented accumulators
US8912837B2 (en) * 2012-10-12 2014-12-16 Stmicroelectronics S.R.L. Mux-based digital delay interpolator
TWI479853B (en) * 2012-12-12 2015-04-01 Mstar Semiconductor Inc Signal processing device and signal processing method
US9223385B2 (en) * 2012-12-19 2015-12-29 Intel Corporation Re-driver power management
JP6155659B2 (en) * 2013-01-28 2017-07-05 株式会社ソシオネクスト Phase interpolation circuit and receiving circuit
US8917132B2 (en) * 2013-03-11 2014-12-23 Micron Technology, Inc. Apparatuses, methods, and circuits including a delay circuit
US8947144B2 (en) 2013-06-18 2015-02-03 Micron Technology, Inc. Apparatuses and methods for duty cycle adjustment
US9503066B2 (en) 2013-07-08 2016-11-22 Micron Technology, Inc. Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
JP6372166B2 (en) * 2014-05-27 2018-08-15 富士通株式会社 Phase interpolator
US9236873B1 (en) 2014-12-17 2016-01-12 Integrated Device Technology, Inc. Fractional divider based phase locked loops with digital noise cancellation
TWI552528B (en) * 2014-12-31 2016-10-01 致茂電子股份有限公司 Clock generating device
KR101901763B1 (en) 2015-01-28 2018-09-27 후아웨이 테크놀러지 컴퍼니 리미티드 Sub-sampling phase-locked loop
KR20160113341A (en) * 2015-03-18 2016-09-29 에스케이하이닉스 주식회사 Phase interpolator circuit, clock data recovery circuit including the same and method for phase interpolation
CN105991112B (en) * 2015-07-06 2018-10-23 龙迅半导体（合肥）股份有限公司 A kind of data clock recovery circuit and its phase interpolator
US10110208B2 (en) 2015-11-25 2018-10-23 Micron Technology, Inc. Apparatuses and methods for providing a signal with a differential phase mixer
CN105634451B (en) * 2015-12-29 2018-08-28 龙迅半导体（合肥）股份有限公司 A kind of data clock recovery circuit and its phase interpolator
US9876489B1 (en) * 2016-09-07 2018-01-23 Xilinx, Inc. Method of implementing a differential integrating phase interpolator
KR102653891B1 (en) 2016-11-30 2024-04-02 삼성전자주식회사 Phase interpolator for interpolating delayed clock signal and device including the same for operating data sampling by using phase interpolated clock signal
CN106502298B (en) * 2016-12-20 2017-11-14 中国电子科技集团公司第五十八研究所 One kind is applied to current generating circuit in low pressure phase interpolator
CN109217849B (en) * 2017-06-30 2020-10-27 华为技术有限公司 Phase interpolator
CN110266293A (en) * 2019-06-13 2019-09-20 中国科学技术大学 A kind of low delay synchronizing device and method
US11296684B2 (en) * 2020-03-31 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Gated tri-state inverter, and low power reduced area phase interpolator system including same, and method of operating same
US11171584B1 (en) * 2020-05-11 2021-11-09 Pix Art Imaging Inc. Interpolation circuit and motor driving circuit
US11626865B1 (en) * 2021-09-22 2023-04-11 Qualcomm Incorporated Low-power high-speed CMOS clock generation circuit
TWI806416B (en) * 2022-02-10 2023-06-21 瑞昱半導體股份有限公司 Clock generating circuit and method for generating clock signals

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EP1093228A1 (en) * 1999-10-12 2001-04-18 Fujitsu Limited Delay interpolator circuit and semiconductor integrated circuit having same
US20030002607A1 (en) * 2001-06-28 2003-01-02 Intel Corporation Clock recovery using clock phase interpolator
US20030218486A1 (en) * 2002-05-21 2003-11-27 Jong-Tae Kwak Digital DLL apparatus for correcting duty cycle and method thereof

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Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
EP1093228A1 (en) * 1999-10-12 2001-04-18 Fujitsu Limited Delay interpolator circuit and semiconductor integrated circuit having same
US20030002607A1 (en) * 2001-06-28 2003-01-02 Intel Corporation Clock recovery using clock phase interpolator
US20030218486A1 (en) * 2002-05-21 2003-11-27 Jong-Tae Kwak Digital DLL apparatus for correcting duty cycle and method thereof

Also Published As

Publication number Publication date
US7593496B2 (en) 2009-09-22
US20070147564A1 (en) 2007-06-28
EP1966887B1 (en) 2016-02-17
TW200742260A (en) 2007-11-01
CN101310440B (en) 2011-07-27
WO2007075312A2 (en) 2007-07-05
EP1966887A2 (en) 2008-09-10
CN101310440A (en) 2008-11-19
TWI331452B (en) 2010-10-01

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