WO2007098044A3 - Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same - Google Patents

Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same Download PDF

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Publication number
WO2007098044A3
WO2007098044A3 PCT/US2007/004163 US2007004163W WO2007098044A3 WO 2007098044 A3 WO2007098044 A3 WO 2007098044A3 US 2007004163 W US2007004163 W US 2007004163W WO 2007098044 A3 WO2007098044 A3 WO 2007098044A3
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WO
WIPO (PCT)
Prior art keywords
memory cell
floating body
electrically floating
bit memory
programming
Prior art date
Application number
PCT/US2007/004163
Other languages
French (fr)
Other versions
WO2007098044A2 (en
WO2007098044A8 (en
Inventor
Eric Carman
Serguei Okhonin
Mark-Eric Jones
Original Assignee
Innovative Silicon Sa
Eric Carman
Serguei Okhonin
Mark-Eric Jones
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innovative Silicon Sa, Eric Carman, Serguei Okhonin, Mark-Eric Jones filed Critical Innovative Silicon Sa
Priority to EP07750961A priority Critical patent/EP1987520A4/en
Publication of WO2007098044A2 publication Critical patent/WO2007098044A2/en
Publication of WO2007098044A8 publication Critical patent/WO2007098044A8/en
Publication of WO2007098044A3 publication Critical patent/WO2007098044A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells

Abstract

Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)
PCT/US2007/004163 2006-02-16 2007-02-15 Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same WO2007098044A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07750961A EP1987520A4 (en) 2006-02-16 2007-02-15 Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US77427506P 2006-02-16 2006-02-16
US60/774,275 2006-02-16
US11/703,429 2007-02-07
US11/703,429 US7542345B2 (en) 2006-02-16 2007-02-07 Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same

Publications (3)

Publication Number Publication Date
WO2007098044A2 WO2007098044A2 (en) 2007-08-30
WO2007098044A8 WO2007098044A8 (en) 2007-11-29
WO2007098044A3 true WO2007098044A3 (en) 2008-10-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/004163 WO2007098044A2 (en) 2006-02-16 2007-02-15 Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same

Country Status (3)

Country Link
US (1) US7542345B2 (en)
EP (1) EP1987520A4 (en)
WO (1) WO2007098044A2 (en)

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