WO2007102141A3 - Multi-bit-per-cell flash memory device with non-bijective mapping - Google Patents

Multi-bit-per-cell flash memory device with non-bijective mapping Download PDF

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Publication number
WO2007102141A3
WO2007102141A3 PCT/IL2006/001251 IL2006001251W WO2007102141A3 WO 2007102141 A3 WO2007102141 A3 WO 2007102141A3 IL 2006001251 W IL2006001251 W IL 2006001251W WO 2007102141 A3 WO2007102141 A3 WO 2007102141A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit
per
memory device
flash memory
mapping
Prior art date
Application number
PCT/IL2006/001251
Other languages
French (fr)
Other versions
WO2007102141A2 (en
Inventor
Simon Litsyn
Eran Sharon
Idan Alrod
Original Assignee
Univ Ramot
Simon Litsyn
Eran Sharon
Idan Alrod
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Ramot, Simon Litsyn, Eran Sharon, Idan Alrod filed Critical Univ Ramot
Priority to EP06809811A priority Critical patent/EP1999591B1/en
Priority to JP2008557892A priority patent/JP5534675B2/en
Priority to KR1020087020296A priority patent/KR101462961B1/en
Publication of WO2007102141A2 publication Critical patent/WO2007102141A2/en
Publication of WO2007102141A3 publication Critical patent/WO2007102141A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Abstract

To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to one or may be an 'into' generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.
PCT/IL2006/001251 2006-03-06 2006-10-30 Multi-bit-per-cell flash memory device with non-bijective mapping WO2007102141A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06809811A EP1999591B1 (en) 2006-03-06 2006-10-30 Multi-bit-per-cell flash memory device with non-bijective mapping
JP2008557892A JP5534675B2 (en) 2006-03-06 2006-10-30 Multi-bit cell flash memory device using non-bijective mapping
KR1020087020296A KR101462961B1 (en) 2006-03-06 2006-10-30 Multi­bit­per­cell flash memory device with non­bijective mapping

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US77904406P 2006-03-06 2006-03-06
US60/779,044 2006-03-06
US11/540,560 2006-10-02
US11/540,560 US7388781B2 (en) 2006-03-06 2006-10-02 Multi-bit-per-cell flash memory device with non-bijective mapping

Publications (2)

Publication Number Publication Date
WO2007102141A2 WO2007102141A2 (en) 2007-09-13
WO2007102141A3 true WO2007102141A3 (en) 2009-04-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2006/001251 WO2007102141A2 (en) 2006-03-06 2006-10-30 Multi-bit-per-cell flash memory device with non-bijective mapping

Country Status (5)

Country Link
US (5) US7388781B2 (en)
EP (1) EP1999591B1 (en)
JP (2) JP5534675B2 (en)
KR (1) KR101462961B1 (en)
WO (1) WO2007102141A2 (en)

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