WO2007130818A2 - Method and apparatus for approximate pattern matching - Google Patents

Method and apparatus for approximate pattern matching Download PDF

Info

Publication number
WO2007130818A2
WO2007130818A2 PCT/US2007/067319 US2007067319W WO2007130818A2 WO 2007130818 A2 WO2007130818 A2 WO 2007130818A2 US 2007067319 W US2007067319 W US 2007067319W WO 2007130818 A2 WO2007130818 A2 WO 2007130818A2
Authority
WO
WIPO (PCT)
Prior art keywords
patterns
allowable error
pattern
data stream
matching
Prior art date
Application number
PCT/US2007/067319
Other languages
French (fr)
Other versions
WO2007130818A3 (en
Inventor
David Edward Taylor
Original Assignee
Exegy Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exegy Incorporated filed Critical Exegy Incorporated
Priority to CA2650571A priority Critical patent/CA2650571C/en
Priority to JP2009509952A priority patent/JP5240475B2/en
Priority to EP07761209.1A priority patent/EP2014054B1/en
Publication of WO2007130818A2 publication Critical patent/WO2007130818A2/en
Publication of WO2007130818A3 publication Critical patent/WO2007130818A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
    • H04L63/0227—Filtering policies
    • H04L63/0245—Filtering by information in the payload
    • G—PHYSICS
    • G16—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS
    • G16B—BIOINFORMATICS, i.e. INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR GENETIC OR PROTEIN-RELATED DATA PROCESSING IN COMPUTATIONAL MOLECULAR BIOLOGY
    • G16B30/00—ICT specially adapted for sequence analysis involving nucleotides or amino acids
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/14—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic
    • H04L63/1408—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic by monitoring network traffic
    • H04L63/1416—Event detection, e.g. attack signature detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/14—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic
    • H04L63/1441—Countermeasures against malicious traffic
    • H04L63/145—Countermeasures against malicious traffic the attack involving the propagation of malware through the network, e.g. viruses, trojans or worms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W12/00—Security arrangements; Authentication; Protecting privacy or anonymity
    • H04W12/60—Context-dependent security
    • H04W12/69—Identity-dependent
    • H04W12/71—Hardware identity

Definitions

  • the present invention relates to the field of approximate pattern matching with a large set of patterns.
  • the present invention relates to a scalable filtering circuit and reduction stage for approximate pattern matching with a large group of patterns.
  • Approximate pattern or string matching is a significant problem that arises in many important applications. These can include, but are not limited to, computational biology, databases and computer communications. This task includes searching for matches between the specified pattern or set of patterns while typically permitting a specified number of errors. As an example, one may desire to search for the word "queuing” while allowing for two errors. This could return results such as the word “queueing” with one character insertion and “cueing” with one character substitution and one character deletion. By allowing a specified number of errors, this allows the search to catch typical spelling variations or errors and still find the desired pattern. Approximate pattern matching is not only a complex task but requires a tremendous amount of computer resources.
  • FIG. 1 An example of this prior art filtering technique is shown by referring to FIG. 1 and is generally indicated by numeral 10.
  • This typical approach is to slice a pattern "P", as indicated by numeral 12, into k + 1 pattern pieces, which are a sequence of non-overlapping sub-patterns, and search for exact matches between the text and the pattern pieces.
  • "k” is equal to the number of allowable errors, which is the maximum edit distance ed(r, j ,P), which is indicated in this nonlimiting example by the numeral two (2) as indicated by numeral 14.
  • a data string T 1 7 16 is then analyzed for an occurrence of at least one substring of the data string 16 that matches at least one of the non-overlapping sub- patterns associated with pattern "P" 12.
  • m+ ⁇ j includes at least m-k characters of P where m is the size of the pattern (in characters) c. Therefore, if we slice P into k+ ⁇ pieces (non-overlapping sub- patterns), then at least one of the pieces must match exactly
  • a method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine includes filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms each configured to detect one or more patterns each with an associated allowable error, detecting a plurality of potential pattern piece matches with the plurality of parallel filter mechanisms, identifying a plurality of potentially matching patterns, each having an associated allowable error, from the plurality of parallel filter mechanisms, reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error with a reduction stage, providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage, and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage that includes an approximate match engine utilizing the associated data and the reduced set of potentially matching patterns.
  • a method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine includes filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms each configured to detect one or more patterns each with an associated allowable error, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator, detecting a plurality of potential pattern piece matches with the plurality of parallel filter mechanisms, identifying a plurality of potentially matching patterns, each having an associated allowable error, from the plurality of parallel filter mechanisms, reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage, and verifying presence of a pattern match in
  • a method and system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine includes utilizing a single hash key generator for extracting a plurality of hash values from a single hash value for inspecting the data stream for data segments matching one or more pattern pieces with false positive errors with at least one search engine, and utilizing the plurality of hash values with a plurality of parallel Bloom filter arrays.
  • a system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine is disclosed.
  • This system includes a filter stage, which utilizes a plurality of parallel filter mechanisms each configured to detect one or more patterns, each with an associated allowable error, that filter a data stream for a plurality of patterns of symbol combinations and detect a plurality of potential pattern piece matches, and identify a plurality of potentially matching patterns, each having an associated allowable error, a reduction stage, which reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, and a verification stage, which includes an approximate match engine, that receives and utilizes associated data and the reduced set of potentially matching patterns and associated allowable errors to verify a presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
  • a system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine includes a plurality of parallel filter mechanisms, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator, each configured to detect one or more patterns, each with an associated allowable error, that filter a data stream for a plurality of patterns of symbol combinations and detect a plurality of potential pattern piece matches and identify a plurality of potentially matching patterns, each having an associated allowable error, a reduction stage that reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, and a verification stage, which includes an approximate match engine, that receives and utilizes associated data and the reduced set of potentially matching patterns and associated allowable errors to verify a presence of a pattern match in the data
  • Illustrative, but nonlimiting, examples of potential application of the present invention include: an intrusion detection system (IDS) for computer communication networks; computational biology and genetics; text searches for structured and unstructured text; and text searches from optical character scans (OCS).
  • IDS intrusion detection system
  • OCS optical character scans
  • Additional aspects of the present invention include, but are not limited to: a filtering technique for approximate matching with multiple patterns where each pattern may specify its allowable errors that can include a large number of pattern pieces, e.g., tens of thousands of patterns or more; utilizing a parallel set of exact match engines, one for each pattern piece length, to perform parallel match operations and to support a wide variety of (pattern length, allowable error) combinations; allowing each pattern to have a specified number of errors; amenability to parallel hardware search implementation and such implementation can provide fast search results; simplifying a verification stage by limiting the number of potentially matching patterns for a region of text, allowing the verification engine to process additional potential search results in a shorter period of time, which allows the total system to scale in capacity while operating at very high speeds; and utilizing a Bloom filter array for each exact match engine; and efficiently implementing each Bloom filter array by using only one hash function generator.
  • Still another aspect of present invention is the reduction stage wherein the scope of the search in the verification stage is reduced with a smaller set of possibly matching patterns.
  • These techniques use a layer of indirection between pieces and patterns which allows each pattern and its allowable errors to be stored only once.
  • This technique includes a lookup using a bin index to retrieve the piece identifiers for the potentially matching pieces.
  • a second lookup uses the piece identifiers to retrieve the pattern identifiers for the patterns that include the pieces.
  • a third lookup uses the pattern identifiers to retrieve the pattern and associated allowable error pairs to be considered by the verification engine.
  • the pattern identifiers are used to retrieve the pairs of patterns and associated allowable errors to be considered by the verification engine.
  • FIG. 1 provides an illustrative overview of a prior art approximate pattern matching technique
  • FIG. 2 provides an exemplary block diagram of the present invention including a data source, a filter circuit, a reduction stage and a verification stage
  • FIG. 1 provides an illustrative overview of a prior art approximate pattern matching technique
  • FIG. 3 is an illustrative, but nonlimiting, block diagram of the present invention including Bloom filters with a match detection function; a reduction stage and a verification stage having approximate pattern matching;
  • FIG. 4 provides an exemplary block diagram of a first filtering stage processing technique using a Bloom filter array;
  • FIG. 5 provides an exemplary block diagram of a second filtering stage processing technique using a Bloom filter array with a single hash function generator;
  • FIG. 6 provides an exemplary block diagram of a first reduction stage processing technique;
  • FIG. 7 provides an exemplary block diagram of a second reduction stage processing technique.
  • the present invention is a scalable filtering circuit for approximate pattern matching with a large set of patterns.
  • the filtering circuit checks for potential matches between a set of stored patterns, where each pattern specifies the number of allowable errors, and an input stream of characters.
  • the number of allowable errors is predetermined or specified using the general edit distance measure that counts the number of single character additions, deletions, and substitutions.
  • the location or locations in the input data stream is identified as well as the matching pattern or plurality of potentially matching patterns.
  • the present invention is designed to operate in concert with a verification stage that looks for an approximate match in the data segment(s) of the input data stream utilizing the previously identified potentially matching pattern(s) from the total number of potentially matching patterns.
  • the methodology for searching for a single pattern can be stated as follows: identifying instances of pattern "P" in text "T” with "k” allowable errors, where "k” is the maximum edit distance.
  • the edit distance is defined as the number of single character insertions, deletions, and substitutions with all errors typically, but not necessarily share the same weighting. In general, other types of errors such as transpositions may be included in the distance measure and each type of error may be assigned a unique weight.
  • the error level and the size of the alphabet from which the pattern and text are constructed, " ⁇ ,” affect the probability that matches will be found.
  • An expression for the match probability, "f(m,k)" assuming a randomly constructed text and a randomly constructed pattern is provided by the following equation:
  • filtering algorithms achieve better performance for a variety of approximate pattern matching problems.
  • the general approach being to perform a simple search on a small section of text to identify potential matches. When a potential match is found, the region of text is examined to see if it is, in fact, an approximate match for a specified pattern.
  • verification is performed by any approximate pattern matching algorithm and may be tightly or loosely coupled to a filtering operation.
  • FIG. 2 A general schematic of the system of the present invention is shown in FIG. 2 and is indicated by numeral 30.
  • Large amounts of data can be provided as input through either a communication link, a disk, a redundant array of independent disks (RAID), or storage area network (SAN), as well as a wide variety of other data sources capable of feeding a filter circuit with high data speed.
  • This data input is indicated by numeral 32 can also be provided through a network input that is indicated by numeral 34.
  • High speed data can be provided through a high-bandwidth interconnect indicated by numeral 36 at high speeds. This high speed data is then passed through a filter circuit 38 that scans the input data for potential matches for a set of input patterns.
  • a reduction stage 40 between the filter circuit 38 and a verification stage 42 that narrows the set of potentially matching patterns that must be considered by the verification stage 42 when processing data segments that produce a match in the filter circuit 38.
  • the verification stage 42 performs a full approximate operation to verify whether or not there is a match for a set of input patterns 46. Search results are then provided as indicated by numeral 44. Predetermined input patterns 46 are provided to the filter circuit 38, the reduction stage 40 and the verification stage 42.
  • FIG. 3 which is the schematic of the basic hardware implementation of the present invention is indicated by numeral 50 and includes a number of Bloom filters indicated by numeral 54.
  • elements are inserted into a set using "b" hash values were the element is utilized as the key and where each hash value identifies a bit position in a B-bit vector.
  • the bits at each of the b bit positions are preferably set to one (1). If a bit is already set to one (1), then no change will be made.
  • the element and the same b hash functions are utilized to compute b hash values. If all the b bits in the vector are set to one (1), then the element is declared to be a member of the set.
  • a Bloom filter 54 will not produce a false negative. If an element is a member of a set, then the b bit positions in the B-bit vector are set to one (1) when the element is inserted into the set. The insertion of additional elements in the set does not reset any of the bits in the vector. However, Bloom filters 54 do produce false positives with a determined probability. This probability can be computed by the equation:
  • the bloom filters 54 store fixed-length elements with one bloom filter circuit 54 for each possible pattern piece length. Therefore, the range of possible pattern piece lengths are constrained within a range.
  • I,TM is the minimum pattern piece length then l mm is less than or equal to the value of the size of the pattern m divided by the maximum edit distance k plus one
  • l max is the maximum piece length, then l max is greater than or equal to the value of the size of the pattern m divided by the maximum edit distance k plus one
  • the total number of Bloom filters 54 that are required when each Bloom filter of the Bloom filters 54 corresponds to a pattern piece length is:
  • a preferred approach is to query each of the Bloom filters 54 in parallel, as shown by the schematic provided by numeral 50 in FIG. 3.
  • Each one of the Bloom filters 54 correspond to a pattern piece length so that various strides of the text window can be selected as an input key to each Bloom filter 54.
  • the segment of data or text window 58, the location of the segment of data in the input stream 59 and additional match meta data 60 are sent to a reduction stage 40.
  • the techniques utilized in the reduction stage 40 can narrow the potentially matching patterns significantly, e.g., over 10,000 to less than 10.
  • RAM random access memory
  • the bits in the "q"-bit Bloom filters 54 are set, during programming, and then checked, during queries, using "b" hash functions. Querying a Bloom filter array 54 requires one (1) memory read to fetch the "q"-bit vector. Using a register 80 and bit- select circuitry 82, checking the bit locations specified by "b" hash functions may be performed on-chip, in a pipelined fashion, as shown in FIG. 4 and generally indicated by numeral 70.
  • a key i.e. pattern piece
  • the key is used by the pre-filter hash function 73 to identify a particular "q"-bit vector in the listing of "w” vectors.
  • the particular "q"-bit vector in the listing of "w” vectors is indicated by column 74 in memory, e.g., RAM, wherein a particular and illustrative vector is identified by numeral 76.
  • These queries are checked with series of "b" hash functions indicated by numeral 78 identifying bit positions within a register 80, which is then provided to a match detection function 82. If all "b" bit positions are set to a one (1), then the key is a pattern piece for a potentially matching pattern.
  • the amount of logic required to implement a Bloom filter array 54 can be minimized, as shown in FIG. 5.
  • This logic is generally indicated by numeral 90.
  • the particular "q"-bit vector in the listing of "w" vectors is indicated by column 96 in memory, e.g., RAM, wherein a particular and illustrative vector is identified by numeral 98. This particular vector 98 is passed to a register 100 and then on to a match pattern detection function 102.
  • This Bit select value 94 must be at least log 2 (W) + (b * Iog 2 (q)) bits in size.
  • the H 3 class of hash functions 92 is an illustrative, but nonlimiting, example of hash functions that can produce wide enough values for this application.
  • An illustrated, but nonlimiting example of reconfigurable hardware that could be utilized includes FPGAs, i.e., field programmable gate arrays, which includes a Xilinx® VirtexII® 4000 series FPGA.
  • Xilinx, Inc. is a Delaware corporation, having a place of business at 2100 Logic Drive, San Jose, California 95124-3400.
  • An illustrated, but nonlimiting, example of the embedded memory in the VirtexII® series of devices include One Hundred and Twenty (120) of the eighteen (18) kilobyte block random access memories (BlockRAMs). These BlockRAMs can be configured to various size words with an illustrative, but nonlimiting, maximum word length of thirty-six (36) bits by Five Hundred and Twelve (512) words.
  • the Bloom filter array 54 implemented with an eighteen (18) kilobyte BlockRAM can represent a set of 3,194 elements with a false probability of 0.063 when the number of b bit positions equals four (4).
  • number of b bit positions equals three (3) the capacity increases to 4,259 elements but the false positive probability increases to 0.125.
  • one Bloom filter array 54 is required for each unique pattern piece length. There is also consideration of the number of parallel circuits that are required to keep pace with the data input rate. In an illustrative, but nonlimiting example, a system that accepts eight (8) new ASCII characters per cycle (64-bit interface) requires eight (8) instances of the circuit operating in parallel. For the VirtexII 4000® FPGA, there are at most fifteen (15) BlockRAMs available for each circuit instance. In order to have BlockRAM resources available for interface buffers, this results in limiting the BlockRAMs to a lower number, e.g., fourteen BlockRAMs.
  • ⁇ ratio of the number of errors divided by the size of the pattern.
  • a rough capacity estimate can be developed by assuming that pieces are uniformly distributed over a range of allowable lengths. In an illustrative, but nonlimiting example, if each Bloom filter array 54 has a capacity of approximately Three Thousand (3,000) pattern pieces then the system has an aggregate capacity of Forty-Two Thousand (42,000) pattern pieces. If it is assumed that each pattern can be divided into three (3) pattern pieces, then the system has a capacity of Fourteen Thousand (14,000) patterns.
  • the region of text must be examined by the verification stage 42 in order to determine whether or not there is an approximate match for one of the "r" patterns. Since "r" may be on the order of 10,000 patterns or more, there is a need to narrow the scope of the search that the verification stage 42 must perform. This is where the reduction stage 40 provides a valuable role of reducing the set of possible matching patterns (pattern set) for the verification stage 42 to consider. As long as the parameters fall within the constraints, there is an assumption that the number of allowable errors may be specified for each pattern.
  • the filter stage 38, the reduction stage 40 and/or the verification stage 42, as shown in FIG. 3, can use at least one reconfigurable logic device, e.g., Field Programmable Gate Array (“FPGA") or at least one integrated circuit, e.g., Application-Specific Integrated Circuit (“ASIC").
  • FPGA Field Programmable Gate Array
  • ASIC Application-Specific Integrated Circuit
  • the first approach is to simplify data searches utilized to resolve the pattern set indicated by numeral 120 in FIG. 6. This allows a data string to come into a shift register 52, which then passes into a filter stage or circuit 38 that preferably includes a Bloom filter array 54. With this approach, the objective is to utilize some, if not all, of the hash values computed by the Bloom filter array 54 in the filter stage or circuit 38 as an index into a table 128, e.g., Binlndex 124.
  • a pattern piece 121 can be received by the filter stage or circuit
  • the entries in this first table 128 contain identifiers 127 for the pattern pieces, e.g., PiecelDs, which map to the hash values 126 comprising the Binlndex 124.
  • identifiers 127 for the pattern pieces e.g., PiecelDs
  • there is an illustrative identifier e.g., PIeCeID 1 and PieceID 4 , which is associated with the example pattern piece 121.
  • the identifiers 127 for the pattern pieces, e.g., PiecelDs are a unique binary tag assigned to each pattern piece.
  • a second table 132 that utilizes the identifiers 128 for the pattern pieces, e.g., PiecelDs, to index one or more pattern identifiers for the set of potentially matching patterns. Since one or more patterns may specify a particular pattern piece, the entries in the second table 132 contain one or more pattern identifiers, e.g., PIDs. Pattern identifiers, e.g., PIDs, are unique binary tags associated with each pattern. For example, with the illustrative identifier, 131, relates to two patterns 137 and 138.
  • a third table 134 that utilizes the pattern identifiers, e.g. PIDs, to index one or more (pattern, allowable error) pairs.
  • This pattern set of potential matches 136 is passed onto the verification stage
  • pattern piece identifiers 128, e.g., PiecelDs, pattern identifiers 132, e.g., PIDs and patterns 134 so long as the number of lookups per cycle does not exceed the amount of lookups supported by the memories.
  • FIG. 7 There is a second and preferred methodology for the reduction stage 40, which is generally indicated by numeral 150 in FIG. 7.
  • This allows a data string to pass into a filter stage or circuit 38 that preferably includes a Bloom filter array 54.
  • actual data segments or pieces that produce a match in the Bloom filter array 54 are utilized to resolve the pattern identifiers for the patterns 162 that specify those pattern pieces.
  • the data segments or pieces that produce a match are used to identify one or more entries in data structures, indicated by numerals 156, 158 and 160, which store pattern identifiers, e.g., PIDs, for the patterns that specify the associated pattern pieces.
  • Illustrative, but nonlimiting examples of suitable data structures are a hash table and a balanced search tree.
  • the methodology may include one or more data structures. In the illustrative, but nonlimiting example 150 in FIG. 7, one data structure is allocated for each pattern piece length.
  • two data segments or pieces that produce a match in the Bloom filter array 54 are identified by numerals 121 and 123.
  • Data piece 121 identifies the entry 157 in the data structure as part of the reduction stage 40.
  • These data structures 156, 158 and 160 can include a wide variety of different structures, e.g., decision tree, hash table, and so forth.
  • the result of these lookup(s) is a set of pattern identifiers for the patterns in the pattern set.
  • these pattern identifiers, e.g., PIDs, 156, 158 and 160 are utilized to retrieve patterns and associated allowable errors from a table 40 prior to a step of verification.
  • the previously referenced entry 157 identify patterns 163 and 165 and associated allowable errors to produce a set of potential matches 164.
  • the set of potential matches and associated predetermined allowable errors 164 is then evaluated by an approximate match engine 166 in the verification stage 42.
  • This approach resolves the set of pattern identifiers in a single step instead of two steps and also eliminates false positive errors produced by the Bloom filter arrays 54. Also, since the actual data segment is utilized to locate entries in the pattern identifier structure(s), an explicit match is performed. If there is no entry in the table, then a false positive is detected and no pattern identifiers, e.g., PIDs, are passed onto the verification stage 42 for that particular pattern piece length.
  • PIDs pattern identifiers
  • the expected number of patterns that specify a given pattern piece 131 include: r
  • the expected pattern size is:
  • the expected pattern set size is less than ten (10) for practical values of m and k (pattern length and allowable errors).
  • the expected pattern set size quickly approaches one (1) as the alphabet size and/or pattern size increases.

Abstract

A system and method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error, which includes filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms, detecting a plurality of potential pattern piece matches, identifying a plurality of potentially matching patterns, reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns with a reduction stage, providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage, and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage.

Description

METHOD AND APPARATUS FOR APPROXIMATE PATTERN MATCHING
FIELD OF THE INVENTION
[0001] The present invention relates to the field of approximate pattern matching with a large set of patterns. In particular, the present invention relates to a scalable filtering circuit and reduction stage for approximate pattern matching with a large group of patterns.
BACKGROUND OF THE INVENTION
[0002] Approximate pattern or string matching is a significant problem that arises in many important applications. These can include, but are not limited to, computational biology, databases and computer communications. This task includes searching for matches between the specified pattern or set of patterns while typically permitting a specified number of errors. As an example, one may desire to search for the word "queuing" while allowing for two errors. This could return results such as the word "queueing" with one character insertion and "cueing" with one character substitution and one character deletion. By allowing a specified number of errors, this allows the search to catch typical spelling variations or errors and still find the desired pattern. Approximate pattern matching is not only a complex task but requires a tremendous amount of computer resources.
[0003] Typically, there is a fast filtering step that is followed by the verification step that performs the full approximate matching function. An example of this prior art filtering technique is shown by referring to FIG. 1 and is generally indicated by numeral 10. This typical approach is to slice a pattern "P", as indicated by numeral 12, into k + 1 pattern pieces, which are a sequence of non-overlapping sub-patterns, and search for exact matches between the text and the pattern pieces. In this case, "k" is equal to the number of allowable errors, which is the maximum edit distance ed(r, j,P), which is indicated in this nonlimiting example by the numeral two (2) as indicated by numeral 14.
[0004] A data string T1 7 16 is then analyzed for an occurrence of at least one substring of the data string 16 that matches at least one of the non-overlapping sub- patterns associated with pattern "P" 12. This approach relies on the following properties: a. If string S = Ta j, matches pattern P with at most k errors, and P - pi. , .pj (a sequence of non-overlapping sub-patterns), then some substring of S matches at least one of them's with at most \_k/j] errors b. If there are character positions / ≤j such that ed(r, PP) ≤ k, then Tj.m+ι j includes at least m-k characters of P where m is the size of the pattern (in characters) c. Therefore, if we slice P into k+\ pieces (non-overlapping sub- patterns), then at least one of the pieces must match exactly
[0005] Therefore, if we slice "P" 12 by the total number of errors "k" 14 plus one (1) into non-overlapping sub-pattern pieces then at least one of the non-overlapping sub- pattern pieces must match exactly. As shown in the Example of FIG. 1, the data string T1 } 16 is divided into k+1 or three (3) pieces of non-overlapping sub-patterns. Therefore the three (3) pieces are "abra" indicated by numeral 18, "cada" indicated by numeral 20, and "bra" indicated by numeral 22. In this example, "cada" indicated by numeral 20 is an exact match with two errors where the letters "br" are replaced and the letter "b" is deleted.
[0006] There is a significant need for a fast and cost effective mechanism for pattern matching utilizing a substantial amount of input data with a considerable set of potentially matching patterns.
SUMMARY OF INVENTION
[0007] In one aspect of this invention, a method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine is disclosed. This method includes filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms each configured to detect one or more patterns each with an associated allowable error, detecting a plurality of potential pattern piece matches with the plurality of parallel filter mechanisms, identifying a plurality of potentially matching patterns, each having an associated allowable error, from the plurality of parallel filter mechanisms, reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error with a reduction stage, providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage, and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage that includes an approximate match engine utilizing the associated data and the reduced set of potentially matching patterns.
[0008] In another aspect of this invention, a method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine is disclosed. This method includes filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms each configured to detect one or more patterns each with an associated allowable error, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator, detecting a plurality of potential pattern piece matches with the plurality of parallel filter mechanisms, identifying a plurality of potentially matching patterns, each having an associated allowable error, from the plurality of parallel filter mechanisms, reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage, and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage that includes an approximate match engine utilizing the associated data and the reduced set of potentially matching patterns.
[0009] In still another aspect of this invention, a method and system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine is disclosed. This method includes utilizing a single hash key generator for extracting a plurality of hash values from a single hash value for inspecting the data stream for data segments matching one or more pattern pieces with false positive errors with at least one search engine, and utilizing the plurality of hash values with a plurality of parallel Bloom filter arrays. [0010] In yet another aspect of this invention, a system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine is disclosed. This system includes a filter stage, which utilizes a plurality of parallel filter mechanisms each configured to detect one or more patterns, each with an associated allowable error, that filter a data stream for a plurality of patterns of symbol combinations and detect a plurality of potential pattern piece matches, and identify a plurality of potentially matching patterns, each having an associated allowable error, a reduction stage, which reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, and a verification stage, which includes an approximate match engine, that receives and utilizes associated data and the reduced set of potentially matching patterns and associated allowable errors to verify a presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
[0011] In yet another aspect of this invention, a system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine is disclosed. The system includes a plurality of parallel filter mechanisms, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator, each configured to detect one or more patterns, each with an associated allowable error, that filter a data stream for a plurality of patterns of symbol combinations and detect a plurality of potential pattern piece matches and identify a plurality of potentially matching patterns, each having an associated allowable error, a reduction stage that reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, and a verification stage, which includes an approximate match engine, that receives and utilizes associated data and the reduced set of potentially matching patterns and associated allowable errors to verify a presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
[0012] Illustrative, but nonlimiting, examples of potential application of the present invention include: an intrusion detection system (IDS) for computer communication networks; computational biology and genetics; text searches for structured and unstructured text; and text searches from optical character scans (OCS).
[0013] Additional aspects of the present invention include, but are not limited to: a filtering technique for approximate matching with multiple patterns where each pattern may specify its allowable errors that can include a large number of pattern pieces, e.g., tens of thousands of patterns or more; utilizing a parallel set of exact match engines, one for each pattern piece length, to perform parallel match operations and to support a wide variety of (pattern length, allowable error) combinations; allowing each pattern to have a specified number of errors; amenability to parallel hardware search implementation and such implementation can provide fast search results; simplifying a verification stage by limiting the number of potentially matching patterns for a region of text, allowing the verification engine to process additional potential search results in a shorter period of time, which allows the total system to scale in capacity while operating at very high speeds; and utilizing a Bloom filter array for each exact match engine; and efficiently implementing each Bloom filter array by using only one hash function generator.
[0014] Still another aspect of present invention is the reduction stage wherein the scope of the search in the verification stage is reduced with a smaller set of possibly matching patterns. These techniques use a layer of indirection between pieces and patterns which allows each pattern and its allowable errors to be stored only once. There is a first illustrative technique that simplifies the data structures, making them amenable to hardware implementation. This technique includes a lookup using a bin index to retrieve the piece identifiers for the potentially matching pieces. A second lookup uses the piece identifiers to retrieve the pattern identifiers for the patterns that include the pieces. A third lookup uses the pattern identifiers to retrieve the pattern and associated allowable error pairs to be considered by the verification engine. There is a second illustrative, but nonlimiting technique that utilizes the text pieces that produced matches in the exact match engines to resolve the pattern identifiers for the patterns that include the piece. The pattern identifiers are used to retrieve the pairs of patterns and associated allowable errors to be considered by the verification engine.
[0015] These are merely some of the innumerable aspects of the present invention and should not be deemed an all-inclusive listing of the innumerable aspects associated with the present invention. BRIEF DESCRIPTION OF DRAWINGS [0016] For a better understanding of the present invention, reference may be made to the accompanying drawings in which: [0017] FIG. 1 provides an illustrative overview of a prior art approximate pattern matching technique; [0018] FIG. 2 provides an exemplary block diagram of the present invention including a data source, a filter circuit, a reduction stage and a verification stage; [0019] FIG. 3 is an illustrative, but nonlimiting, block diagram of the present invention including Bloom filters with a match detection function; a reduction stage and a verification stage having approximate pattern matching; [0020] FIG. 4 provides an exemplary block diagram of a first filtering stage processing technique using a Bloom filter array; [0021] FIG. 5 provides an exemplary block diagram of a second filtering stage processing technique using a Bloom filter array with a single hash function generator; [0022] FIG. 6 provides an exemplary block diagram of a first reduction stage processing technique; and [0023] FIG. 7 provides an exemplary block diagram of a second reduction stage processing technique.
DETAILED DESCRIPTION OF THE INVENTION
[0024] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as to obscure the present invention.
[0025] The present invention is a scalable filtering circuit for approximate pattern matching with a large set of patterns. The filtering circuit checks for potential matches between a set of stored patterns, where each pattern specifies the number of allowable errors, and an input stream of characters. The number of allowable errors is predetermined or specified using the general edit distance measure that counts the number of single character additions, deletions, and substitutions. When a potential match is detected, the location or locations in the input data stream is identified as well as the matching pattern or plurality of potentially matching patterns. The present invention is designed to operate in concert with a verification stage that looks for an approximate match in the data segment(s) of the input data stream utilizing the previously identified potentially matching pattern(s) from the total number of potentially matching patterns.
[0026] The methodology for searching for a single pattern can be stated as follows: identifying instances of pattern "P" in text "T" with "k" allowable errors, where "k" is the maximum edit distance. The edit distance is defined as the number of single character insertions, deletions, and substitutions with all errors typically, but not necessarily share the same weighting. In general, other types of errors such as transpositions may be included in the distance measure and each type of error may be assigned a unique weight.
[0027] Assuming that "m" is the size of the pattern in characters and "n" is the size of the text in characters, then the error level can be defined for a particular pattern as the ratio of the number of allowable errors and the size of the pattern, which is "α = k/m". The error level and the size of the alphabet from which the pattern and text are constructed, "σ," affect the probability that matches will be found. An expression for the match probability, "f(m,k)" assuming a randomly constructed text and a randomly constructed pattern is provided by the following equation:
Figure imgf000008_0001
This is where "e" is the base of the natural logarithm.
[0028] It is believed that filtering algorithms achieve better performance for a variety of approximate pattern matching problems. The general approach being to perform a simple search on a small section of text to identify potential matches. When a potential match is found, the region of text is examined to see if it is, in fact, an approximate match for a specified pattern. In general, verification is performed by any approximate pattern matching algorithm and may be tightly or loosely coupled to a filtering operation.
[0029] A general schematic of the system of the present invention is shown in FIG. 2 and is indicated by numeral 30. Large amounts of data can be provided as input through either a communication link, a disk, a redundant array of independent disks (RAID), or storage area network (SAN), as well as a wide variety of other data sources capable of feeding a filter circuit with high data speed. This data input is indicated by numeral 32 can also be provided through a network input that is indicated by numeral 34. High speed data can be provided through a high-bandwidth interconnect indicated by numeral 36 at high speeds. This high speed data is then passed through a filter circuit 38 that scans the input data for potential matches for a set of input patterns. There is then a reduction stage 40 between the filter circuit 38 and a verification stage 42 that narrows the set of potentially matching patterns that must be considered by the verification stage 42 when processing data segments that produce a match in the filter circuit 38. The verification stage 42 performs a full approximate operation to verify whether or not there is a match for a set of input patterns 46. Search results are then provided as indicated by numeral 44. Predetermined input patterns 46 are provided to the filter circuit 38, the reduction stage 40 and the verification stage 42.
[0030] In a particular window of text, it is possible to search for an exact match and any of the pattern pieces specified by a predetermined number "r" patterns. If a specific pattern "i" allows "kj" errors, then the total number of pattern pieces is indicated by the equation:
ι=l
[0031] This filtering approach is utilized with parallel filter mechanisms which can include a parallel set of Bloom filters, a set of parallel Bloom filter arrays, or a set of Bloom filter arrays that utilize a single hash function generator. As shown in FIG. 3, which is the schematic of the basic hardware implementation of the present invention is indicated by numeral 50 and includes a number of Bloom filters indicated by numeral 54. In a classical Bloom filter 54, elements are inserted into a set using "b" hash values were the element is utilized as the key and where each hash value identifies a bit position in a B-bit vector. The bits at each of the b bit positions are preferably set to one (1). If a bit is already set to one (1), then no change will be made. In order to test whether or not a particular element is a member of the set represented by a Bloom filter 54, the element and the same b hash functions are utilized to compute b hash values. If all the b bits in the vector are set to one (1), then the element is declared to be a member of the set.
[0032] A Bloom filter 54 will not produce a false negative. If an element is a member of a set, then the b bit positions in the B-bit vector are set to one (1) when the element is inserted into the set. The insertion of additional elements in the set does not reset any of the bits in the vector. However, Bloom filters 54 do produce false positives with a determined probability. This probability can be computed by the equation:
Figure imgf000010_0001
If the following relationship holds:
b = — In 2 then: / =(1 /2)" P
[0033] Approximate match filtering on multiple patterns and allowing each pattern to specify its allowable errors produces sets of pattern pieces of various lengths. Preferably, but not necessarily, the bloom filters 54 store fixed-length elements with one bloom filter circuit 54 for each possible pattern piece length. Therefore, the range of possible pattern piece lengths are constrained within a range.
[0034] If I,™ is the minimum pattern piece length then lmm is less than or equal to the value of the size of the pattern m divided by the maximum edit distance k plus one
(1):
Figure imgf000010_0002
[0035] If lmax is the maximum piece length, then lmax is greater than or equal to the value of the size of the pattern m divided by the maximum edit distance k plus one
(1): m "L J Jt + I " ™
[0036] The total number of Bloom filters 54 that are required when each Bloom filter of the Bloom filters 54 corresponds to a pattern piece length is:
1 max - 1 mm + One (1).
[0037] A preferred approach is to query each of the Bloom filters 54 in parallel, as shown by the schematic provided by numeral 50 in FIG. 3. Each one of the Bloom filters 54 correspond to a pattern piece length so that various strides of the text window can be selected as an input key to each Bloom filter 54.
[0038] If any of the Bloom filters 54 result in a detected match 56, then the segment of data or text window 58, the location of the segment of data in the input stream 59 and additional match meta data 60 are sent to a reduction stage 40. The techniques utilized in the reduction stage 40 can narrow the potentially matching patterns significantly, e.g., over 10,000 to less than 10.
[0039] The result passing from the reduction stage 40 goes to the verification stage
42, which includes the approximate match search engine. By reducing the number of candidate patterns to be considered by the verification stage 42, allowing the verification stage to process more potential search results in a given amount of time, and thus allowing the total system to scale in capacity while operating at high speeds.
[0040] A Bloom filter array 54 typically minimizes the number of memory accesses, e.g., random access memory (RAM), required for a set membership query. Moreover, the Bloom filter array 54 partitions the B-bit vector into "W" vectors of size "q = B/W" where "q" is the word size of the memory. There can preferably be an even distribution of stored elements over the "W" vectors (memory words) using a pre- filter hash function. This creates an array of "W" "q"-bit Bloom filters.
[0041] The bits in the "q"-bit Bloom filters 54 are set, during programming, and then checked, during queries, using "b" hash functions. Querying a Bloom filter array 54 requires one (1) memory read to fetch the "q"-bit vector. Using a register 80 and bit- select circuitry 82, checking the bit locations specified by "b" hash functions may be performed on-chip, in a pipelined fashion, as shown in FIG. 4 and generally indicated by numeral 70.
[0042] In this application, a key (i.e. pattern piece) is indicated by numeral 72. The key is used by the pre-filter hash function 73 to identify a particular "q"-bit vector in the listing of "w" vectors. The particular "q"-bit vector in the listing of "w" vectors is indicated by column 74 in memory, e.g., RAM, wherein a particular and illustrative vector is identified by numeral 76. These queries are checked with series of "b" hash functions indicated by numeral 78 identifying bit positions within a register 80, which is then provided to a match detection function 82. If all "b" bit positions are set to a one (1), then the key is a pattern piece for a potentially matching pattern. [0043] Preferably, the amount of logic required to implement a Bloom filter array 54 can be minimized, as shown in FIG. 5. This logic is generally indicated by numeral 90. There is a single hash function indicated by numeral 92. There is the generation of a single random value. A subset of the bits from this random value are utilized to construct the pre-filter hash address and "b" filter bit-positions that is indicated by numeral 94. The particular "q"-bit vector in the listing of "w" vectors is indicated by column 96 in memory, e.g., RAM, wherein a particular and illustrative vector is identified by numeral 98. This particular vector 98 is passed to a register 100 and then on to a match pattern detection function 102. This Bit select value 94 must be at least log2 (W) + (b * Iog2 (q)) bits in size. The H3 class of hash functions 92 is an illustrative, but nonlimiting, example of hash functions that can produce wide enough values for this application.
[0044] An illustrated, but nonlimiting example of reconfigurable hardware that could be utilized includes FPGAs, i.e., field programmable gate arrays, which includes a Xilinx® VirtexII® 4000 series FPGA. Xilinx, Inc., is a Delaware corporation, having a place of business at 2100 Logic Drive, San Jose, California 95124-3400. An illustrated, but nonlimiting, example of the embedded memory in the VirtexII® series of devices include One Hundred and Twenty (120) of the eighteen (18) kilobyte block random access memories (BlockRAMs). These BlockRAMs can be configured to various size words with an illustrative, but nonlimiting, maximum word length of thirty-six (36) bits by Five Hundred and Twelve (512) words.
[0045] Utilizing the previous expression for probability of a false positive and assuming uniform hashing performance, the Bloom filter array 54 implemented with an eighteen (18) kilobyte BlockRAM can represent a set of 3,194 elements with a false probability of 0.063 when the number of b bit positions equals four (4). When number of b bit positions equals three (3), the capacity increases to 4,259 elements but the false positive probability increases to 0.125.
[0046] As previously stated, one Bloom filter array 54 is required for each unique pattern piece length. There is also consideration of the number of parallel circuits that are required to keep pace with the data input rate. In an illustrative, but nonlimiting example, a system that accepts eight (8) new ASCII characters per cycle (64-bit interface) requires eight (8) instances of the circuit operating in parallel. For the VirtexII 4000® FPGA, there are at most fifteen (15) BlockRAMs available for each circuit instance. In order to have BlockRAM resources available for interface buffers, this results in limiting the BlockRAMs to a lower number, e.g., fourteen BlockRAMs. This illustrative, but nonlimiting, resource allocation can place a constraint on the length of pattern pieces and the combination of pattern piece and allowable error. This in turn places a limit on the maximum error level. When "m" is equal to the size of the pattern, "p" is equal to number of pattern pieces and "k" is the number of allowable errors or edit distance then the following equations are applicable:
Figure imgf000013_0001
k k
«max
where α = ratio of the number of errors divided by the size of the pattern.
[0047] The following Table 1 is when "α ", i.e., ratio of the number of errors divided by the size of the pattern is less than or equal to one (1):
[0048]
Figure imgf000013_0002
[0049] The following Table 3 is when "α" , i.e., ratio of the number of errors divided by the size of the pattern is less than or equal to one-third (1/3):
Figure imgf000014_0001
[0050] Therefore in the second example and Table 2, when "α" , i.e., ratio of the number of errors divided by the size of the pattern is less than or equal to one-half (1/2) and when the pattern allows no errors, i.e., "k = 0", there must be at least two (2) characters and no more than fifteen (15) characters. A pattern that allows one error, i.e., "k = 1", must contain at least four (4) characters and no more than thirty (30) characters. Although a wide variety of admissible pattern sizes and allowable errors can be utilized, it is believed that a pattern is at least two (2) characters and no more than fifteen (15) characters will be a workable constraint for most text searches in English, however, this should not be construed as a limit.
[0051] A rough capacity estimate can be developed by assuming that pieces are uniformly distributed over a range of allowable lengths. In an illustrative, but nonlimiting example, if each Bloom filter array 54 has a capacity of approximately Three Thousand (3,000) pattern pieces then the system has an aggregate capacity of Forty-Two Thousand (42,000) pattern pieces. If it is assumed that each pattern can be divided into three (3) pattern pieces, then the system has a capacity of Fourteen Thousand (14,000) patterns.
[0052] Once a potential match has been detected one or more pattern piece lengths 56, as shown in FIG. 3, then the region of text must be examined by the verification stage 42 in order to determine whether or not there is an approximate match for one of the "r" patterns. Since "r" may be on the order of 10,000 patterns or more, there is a need to narrow the scope of the search that the verification stage 42 must perform. This is where the reduction stage 40 provides a valuable role of reducing the set of possible matching patterns (pattern set) for the verification stage 42 to consider. As long as the parameters fall within the constraints, there is an assumption that the number of allowable errors may be specified for each pattern.
[0053] Throughout this patent application as shown in FIG. 3, the filter stage 38, the reduction stage 40 and/or the verification stage 42, as shown in FIG. 3, can use at least one reconfigurable logic device, e.g., Field Programmable Gate Array ("FPGA") or at least one integrated circuit, e.g., Application-Specific Integrated Circuit ("ASIC").
[0054] There are two illustrative, but nonlimiting, approaches to perform the reduction stage 40. The first approach is to simplify data searches utilized to resolve the pattern set indicated by numeral 120 in FIG. 6. This allows a data string to come into a shift register 52, which then passes into a filter stage or circuit 38 that preferably includes a Bloom filter array 54. With this approach, the objective is to utilize some, if not all, of the hash values computed by the Bloom filter array 54 in the filter stage or circuit 38 as an index into a table 128, e.g., Binlndex 124.
[0055] For example a pattern piece 121 can be received by the filter stage or circuit
38 and is received as hash values 126 comprising the Binlndex 124. The entries in this first table 128 contain identifiers 127 for the pattern pieces, e.g., PiecelDs, which map to the hash values 126 comprising the Binlndex 124. For example, there is an illustrative identifier, e.g., PIeCeID1 and PieceID4, which is associated with the example pattern piece 121. The identifiers 127 for the pattern pieces, e.g., PiecelDs, are a unique binary tag assigned to each pattern piece.
[0056] There is a second table 132 that utilizes the identifiers 128 for the pattern pieces, e.g., PiecelDs, to index one or more pattern identifiers for the set of potentially matching patterns. Since one or more patterns may specify a particular pattern piece, the entries in the second table 132 contain one or more pattern identifiers, e.g., PIDs. Pattern identifiers, e.g., PIDs, are unique binary tags associated with each pattern. For example, with the illustrative identifier, 131, relates to two patterns 137 and 138.
[0057] There is a third table 134 that utilizes the pattern identifiers, e.g. PIDs, to index one or more (pattern, allowable error) pairs. The identified set or plurality of potentially matching patterns, each with predetermined allowable errors, e.g. (pattern, allowable error) pairs 137 and 138, is then created as indicated by numeral 136. [0058] This pattern set of potential matches 136 is passed onto the verification stage
42, which includes evaluation by an approximate match engine 142 for matching patterns and associated predetermined allowable errors. There only needs to be one copy of tables for the pattern piece identifiers 128, e.g., PiecelDs, pattern identifiers 132, e.g., PIDs and patterns 134 so long as the number of lookups per cycle does not exceed the amount of lookups supported by the memories.
[0059] There is a second and preferred methodology for the reduction stage 40, which is generally indicated by numeral 150 in FIG. 7. This allows a data string to pass into a filter stage or circuit 38 that preferably includes a Bloom filter array 54. With this approach, actual data segments or pieces that produce a match in the Bloom filter array 54 are utilized to resolve the pattern identifiers for the patterns 162 that specify those pattern pieces. The data segments or pieces that produce a match are used to identify one or more entries in data structures, indicated by numerals 156, 158 and 160, which store pattern identifiers, e.g., PIDs, for the patterns that specify the associated pattern pieces. Illustrative, but nonlimiting examples of suitable data structures are a hash table and a balanced search tree. The methodology may include one or more data structures. In the illustrative, but nonlimiting example 150 in FIG. 7, one data structure is allocated for each pattern piece length.
[0060] In an illustrative, but nonlimiting example, two data segments or pieces that produce a match in the Bloom filter array 54 are identified by numerals 121 and 123. Data piece 121 identifies the entry 157 in the data structure as part of the reduction stage 40. These data structures 156, 158 and 160 can include a wide variety of different structures, e.g., decision tree, hash table, and so forth. The result of these lookup(s) is a set of pattern identifiers for the patterns in the pattern set. As with the prior approach, these pattern identifiers, e.g., PIDs, 156, 158 and 160 are utilized to retrieve patterns and associated allowable errors from a table 40 prior to a step of verification. The previously referenced entry 157 identify patterns 163 and 165 and associated allowable errors to produce a set of potential matches 164. The set of potential matches and associated predetermined allowable errors 164 is then evaluated by an approximate match engine 166 in the verification stage 42.
[0061] This approach resolves the set of pattern identifiers in a single step instead of two steps and also eliminates false positive errors produced by the Bloom filter arrays 54. Also, since the actual data segment is utilized to locate entries in the pattern identifier structure(s), an explicit match is performed. If there is no entry in the table, then a false positive is detected and no pattern identifiers, e.g., PIDs, are passed onto the verification stage 42 for that particular pattern piece length. The tradeoff is that the data structures can be more complex and the implementation more resource intensive depending on the implementation.
[0062] Therefore, this is a scalable design for a filtering circuit 38 and reduction stage
40 for approximate pattern matching on multiple patterns that are amenable to hardware implementation. In addition to the thousands of patterns, multiple filter circuits can support multiple input symbols per cycle. Utilizing the high performance filtering circuit 38 and the reduction stage 40, the performance requirements placed on a verification stage 40 can be analyzed. For the purpose of this analysis, we assume that all patterns specify the same number of allowable errors, "k". Effective load on the verification stage is determined as the probability of a match and the expected size of the set of potentially matching patterns. The probability of match is simply the sum of the probability that any of the "r( k+1)" pieces produce a match in a text window and the false positive probability of the Bloom filter arrays 54 where "r" is the predetermined number of "r" pattern pieces and "k" is the number of predetermined errors.
[0063] If "L" is the number of Bloom filter arrays 54 and assuming random text on an alphabet of "σ" characters, the probability of any of these pieces matching would be:
Eψiatch - — π — r
[0064] The addition of the false positive probability of the Bloom filter arrays provides:
E[match] = -r + Lf rU+i
[0065] By utilizing illustrative, but nonlimiting, example values L = 14, σ = 40, r =
14,000 and f = 0.0034, the match probability is highly sensitive to the minimum piece length. For example, when m = 5 and k = 1 (a minimum piece length of two (2) characters), then the match probability is one (1). If the pattern size is increased to six (6) (a minimum pattern piece length of three (3) characters), then the match probability is 0.079. This result suggests that the minimum pattern piece size should be three (3) characters or more. In this situation, there will be an expectation of one match every twelve (12) cycles.
[0066] Utilizing the reduction stage 40 methodology shown in FIG. 6 with a series of index lookups, then given that at least one Bloom filter array 54 produces a match, the expected number of Bloom filter arrays 54 that will produce a match, i.e., the expected number of bin index lookups, is:
Figure imgf000018_0001
[0067] Under the assumption that the pattern pieces are uniformly distributed over
"L" Bloom filter arrays 54 (pattern piece lengths) and uniformly distributed over the bins, the expected number of pattern piece identifiers 128, as shown in FIG. 6, per bin is:
E[PieceIds I bin] ≤
Figure imgf000018_0002
where "B" is the size of memory used to implement the Bloom filter array 54, "W" is the number of words in the Bloom filter array 54 and "b" is the number of hash functions used in each Bloom filter in the Bloom filter array 54.
[0068] Finally, the expected number of patterns that specify a given pattern piece 131, as shown in FIG. 6, include: r
E\patterns I PiecelDs] ≤ 1 + ■ σ1
[0069] Therefore, provided that at least one Bloom filter array 54 produces a match, the expected pattern size is:
E\patterns\ ≤
Figure imgf000018_0003
[0070] Assuming uniform text, uniform distribution of piece lengths, uniform distributions (good hash functions) and with L = 14, σ = 40, r = 14,000, b = 3 and W = 512, then the expected pattern set size is less than ten (10) for practical values of m and k (pattern length and allowable errors). The expected pattern set size quickly approaches one (1) as the alphabet size and/or pattern size increases.
[0071] The expression for the expected pattern set size when using other reduction stage approach indicated by FIG. 7 with the text segment as an index are similar and produce a slightly smaller pattern set size. In combination with the previous result, which is one pattern match every twelve (12) cycles, a conservative constraint for the average throughput of the verification stage 42 is approximately one (1) match on one pattern per every cycle.
[0072] Thus, there has been shown and described several embodiments of a novel invention. As is evident from the foregoing description, certain aspects of the present invention are not limited by the particular details of the examples illustrated herein, and it is therefore contemplated that other modifications and applications, or equivalents thereof, will occur to those skilled in the art. The terms "have," "having," "includes" and "including" and similar terms as used in the foregoing specification are used in the sense of "optional" or "may include" and not as "required." Many changes, modifications, variations and other uses and applications of the present construction will, however, become apparent to those skilled in the art after considering the specification and the accompanying drawings. All such changes, modifications, variations and other uses and applications which do not depart from the spirit and scope of the invention are deemed to be covered by the invention which is limited only by the claims that follow.

Claims

1. A method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine comprising: filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms each configured to detect one or more patterns each with an associated allowable error; detecting a plurality of potential pattern piece matches with the plurality of parallel filter mechanisms; identifying a plurality of potentially matching patterns, each having an associated allowable error, from the plurality of parallel filter mechanisms; reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error with a reduction stage; providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage; and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage that includes an approximate match engine utilizing the associated data and the reduced set of potentially matching patterns.
2. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 1, further comprising providing the data stream prior to the step of filtering a data stream from the group consisting of a communication link, a redundant array of independent disks ("RAID"), or a storage area network ("SAN").
3. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 1, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator.
4. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 1, wherein the plurality of parallel filter mechanisms is selected from the group consisting of at least one reconfigurable logic device or at least one integrated circuit, the reduction stage is selected from the group consisting of at least one reconfigurable logic=device or at least one integrated circuit.
5. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 4, wherein the plurality of parallel filter mechanisms is selected from the group consisting of at least one Field Programmable Gate Array ("FPGA") or the at least one=Application- Specific Integrated Circuit ("ASIC"), the reduction stage is selected from the group consisting of at least one Field Programmable Gate Array ("FPGA") or the at least one Application- Specific Integrated Circuit ("ASIC")
6. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 1, wherein the plurality of parallel filter mechanisms include at least one Bloom filter array that utilizes a single hash key generator for computing hash values that correspond to a bit vector and positions in the bit vector that identify whether an inputted data segment is a match with one of the pattern pieces stored in the Bloom filter array.
7. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 1, wherein the step of reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, further includes: utilizing data from the plurality of parallel filter mechanisms to lookup one or more pattern piece identifiers for each data segment piece that produced a match in the plurality of parallel filter mechanisms; utilizing the one or more pattern piece identifiers for retrieving at least one pattern identifier; utilizing the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error; and utilizing the at least one potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations with a verification stage.
8. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 7, wherein the step of reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, further includes utilizing a first lookup function with a bin index.
9. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 8, wherein the bin index is selected from the group consisting of different hash keys or portions of hash keys.
10. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 1, wherein the step of reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, further includes: utilizing the at least one data segment that produced a match from the step of filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms for retrieving at least one pattern identifier; utilizing the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error; and utilizing the potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
11. A method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine comprising: filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms each configured to detect one or more patterns each with an associated allowable error, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator; detecting a plurality of potential pattern piece matches with the plurality of parallel filter mechanisms; identifying a plurality of potentially matching patterns, each having an associated allowable error, from the plurality of parallel filter mechanisms; reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error; providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage; and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage that includes an approximate match engine utilizing the associated data and the reduced set of potentially matching patterns.
12. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 11, wherein the step of reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, further includes: utilizing data from the plurality of parallel filter mechanisms to lookup one or more pattern piece identifiers for each data segment piece that produced a match in the plurality of parallel filter mechanisms; utilizing a plurality of pattern piece identifiers for retrieving at least one pattern identifier; utilizing the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error; and utilizing the at least one potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream.
13. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 11, wherein the step of reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, further includes: utilizing the at least one data segment that produced a match from the step of filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms for retrieving at least one pattern identifier; utilizing the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error; and utilizing the potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
14. The method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 1, wherein the step of reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, further includes utilizing a plurality of parallel Bloom filter arrays, where each Bloom filter array utilizes a single hash key generator for extracting a plurality of hash values from a single hash value for inspecting the data stream for data segments matching one or more pattern pieces with false positive errors.
15. A system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine comprising: a filter stage, which utilizes a plurality of parallel filter mechanisms each configured to detect one or more patterns, each with an associated allowable error, that filter a data stream for a plurality of patterns of symbol combinations and detect a plurality of potential pattern piece matches, and identify a plurality of potentially matching patterns, each having an associated allowable error; a reduction stage, which reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error; and a verification stage, which includes an approximate match engine, that receives and utilizes associated data and the reduced set of potentially matching patterns and associated allowable errors to verify a presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
16. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 15, further comprising a data stream provider from the group consisting of a communication link, a redundant array of independent disks ("RAID"), or a storage area network ("SAN").
17. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 15, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator.
18. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 15, wherein the filter stage is selected from the group consisting of at least one reconfigurable logic device or at least one integrated circuit, the reduction stage is selected from the group consisting of at least one reconfigurable logic device or at least one integrated circuit
19. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 18, wherein the filter stage is selected from the group consisting of at least one Field Programmable Gate Array ("FPGA") or the at least one Application-Specific Integrated Circuit ("ASIC"), the reduction stage is selected from the group consisting of at least one Field Programmable Gate Array ("FPGA") or the at least one Application-Specific Integrated Circuit ("ASIC").
20. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 15, wherein the filter stage includes a plurality of parallel filter mechanisms which includes at least one Bloom filter array that utilizes a single hash key generator for computing hash values that correspond to the position of a Bloom filter in the at least one Bloom filter array and the positions of bits in the Bloom filter that identify whether an inputted piece of a data segment is a match with at least one of the plurality of potentially matching pattern pieces.
21. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 15, wherein the reduction stage that reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, also utilizes data from the plurality of parallel filter mechanisms to lookup one or more pattern piece identifiers for each data segment piece that produced a match in the plurality of parallel filter mechanisms and utilizes a plurality of pattern piece identifiers for retrieving at least one pattern identifier and utilizes the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error and utilizes the at least one potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
22. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 21, wherein the reduction stage utilizes a first lookup function with a bin index.
23. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 22, wherein the bin index is selected from the group consisting of different hash keys or portions of hash keys.
24. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 15, wherein the reduction stage that reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, also utilizes the at least one data segment that produced a match from the step of filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms for retrieving at least one pattern identifier and utilizes the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error and utilizes the potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
25. A system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine comprising: a plurality of parallel filter mechanisms, wherein the plurality of parallel filter mechanisms is a group consisting of a set of parallel Bloom filters, a set of parallel Bloom filter arrays or a set of parallel Bloom filter arrays that utilize a single hash key generator; each configured to detect one or more patterns, each with an associated allowable error, that filter a data stream for a plurality of patterns of symbol combinations and detect a plurality of potential pattern piece matches and identify a plurality of potentially matching patterns, each having an associated allowable error; a reduction stage that reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error; and a verification stage, which includes an approximate match engine, that receives and utilizes associated data and the reduced set of potentially matching patterns and associated allowable errors to verify a presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
26. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 25, wherein the reduction stage that reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, also utilizes data from the plurality of parallel filter mechanisms to lookup one or more pattern piece identifiers for each data segment piece that produced a match in the plurality of parallel filter mechanisms and utilizes a plurality of pattern piece identifiers for retrieving at least one pattern identifier and utilizes the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error and utilizes the at least one potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
27. The system for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error with at least one search engine according to Claim 25, wherein the reduction stage that reduces the identified plurality of potentially matching patterns to a set of potentially matching patterns, each having an associated allowable error, also utilizes the at least one data segment that produced a match from the step of filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mecham'sms for retrieving at least one pattern identifier and utilizes the at least one pattern identifier for retrieving at least one potentially matching pattern and an associated allowable error and utilizes the potentially matching pattern and the associated allowable error for verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations.
PCT/US2007/067319 2006-05-02 2007-04-24 Method and apparatus for approximate pattern matching WO2007130818A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA2650571A CA2650571C (en) 2006-05-02 2007-04-24 Method and apparatus for approximate pattern matching
JP2009509952A JP5240475B2 (en) 2006-05-02 2007-04-24 Approximate pattern matching method and apparatus
EP07761209.1A EP2014054B1 (en) 2006-05-02 2007-04-24 Method and apparatus for approximate pattern matching

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/381,214 US7636703B2 (en) 2006-05-02 2006-05-02 Method and apparatus for approximate pattern matching
US11/381,214 2006-05-02

Publications (2)

Publication Number Publication Date
WO2007130818A2 true WO2007130818A2 (en) 2007-11-15
WO2007130818A3 WO2007130818A3 (en) 2008-02-28

Family

ID=38617510

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/067319 WO2007130818A2 (en) 2006-05-02 2007-04-24 Method and apparatus for approximate pattern matching

Country Status (5)

Country Link
US (1) US7636703B2 (en)
EP (2) EP2014054B1 (en)
JP (1) JP5240475B2 (en)
CA (1) CA2650571C (en)
WO (1) WO2007130818A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009177335A (en) * 2008-01-22 2009-08-06 Nippon Telegr & Teleph Corp <Ntt> Stream data processing method, stream data processing program, and stream data processing system

Families Citing this family (151)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7835966B2 (en) * 2001-09-17 2010-11-16 Recognia Inc. Technical analysis formation recognition using pivot points
GB2418999A (en) 2004-09-09 2006-04-12 Surfcontrol Plc Categorizing uniform resource locators
EP1859378A2 (en) 2005-03-03 2007-11-28 Washington University Method and apparatus for performing biosequence similarity searching
US7634584B2 (en) 2005-04-27 2009-12-15 Solarflare Communications, Inc. Packet validation in virtual network interface architecture
US7702629B2 (en) 2005-12-02 2010-04-20 Exegy Incorporated Method and device for high performance regular expression pattern matching
US7954114B2 (en) 2006-01-26 2011-05-31 Exegy Incorporated Firmware socket module for FPGA-based pipeline processing
US8379841B2 (en) 2006-03-23 2013-02-19 Exegy Incorporated Method and system for high throughput blockwise independent encryption/decryption
US7840482B2 (en) 2006-06-19 2010-11-23 Exegy Incorporated Method and system for high speed options pricing
US7921046B2 (en) 2006-06-19 2011-04-05 Exegy Incorporated High speed processing of financial information using FPGA devices
US8615800B2 (en) 2006-07-10 2013-12-24 Websense, Inc. System and method for analyzing web content
US8020206B2 (en) 2006-07-10 2011-09-13 Websense, Inc. System and method of analyzing web content
US8326819B2 (en) 2006-11-13 2012-12-04 Exegy Incorporated Method and system for high performance data metatagging and data indexing using coprocessors
US7660793B2 (en) 2006-11-13 2010-02-09 Exegy Incorporated Method and system for high performance integration, processing and searching of structured and unstructured data using coprocessors
TW200821913A (en) * 2006-11-15 2008-05-16 Univ Nat Chiao Tung String matching system by using bloom filter to achieve sub-linear computation time and method thereof
US9654495B2 (en) 2006-12-01 2017-05-16 Websense, Llc System and method of analyzing web addresses
GB2458094A (en) 2007-01-09 2009-09-09 Surfcontrol On Demand Ltd URL interception and categorization in firewalls
GB2445764A (en) 2007-01-22 2008-07-23 Surfcontrol Plc Resource access filtering system and database structure for use therewith
CN101622849B (en) 2007-02-02 2014-06-11 网圣公司 System and method for adding context to prevent data leakage over a computer network
US8015174B2 (en) * 2007-02-28 2011-09-06 Websense, Inc. System and method of controlling access to the internet
GB0709527D0 (en) 2007-05-18 2007-06-27 Surfcontrol Plc Electronic messaging system, message processing apparatus and message processing method
US7849399B2 (en) * 2007-06-29 2010-12-07 Walter Hoffmann Method and system for tracking authorship of content in data
EP2186250B1 (en) 2007-08-31 2019-03-27 IP Reservoir, LLC Method and apparatus for hardware-accelerated encryption/decryption
US9158837B2 (en) * 2007-10-10 2015-10-13 International Business Machines Corporation Methods and apparatus for adaptive source filtering and load shedding for data stream processing
US8478544B2 (en) 2007-11-21 2013-07-02 Cosmosid Inc. Direct identification and measurement of relative populations of microorganisms with direct DNA sequencing and probabilistic methods
EP2229587B1 (en) * 2007-11-21 2016-08-03 Cosmosid Inc. Genome identification system
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
EP2235836A4 (en) * 2008-01-24 2012-08-29 Sra International Inc System and method for variant string matching
US8028000B2 (en) * 2008-02-28 2011-09-27 Microsoft Corporation Data storage structure
US8005868B2 (en) * 2008-03-07 2011-08-23 International Business Machines Corporation System and method for multiple distinct aggregate queries
US8370948B2 (en) 2008-03-19 2013-02-05 Websense, Inc. System and method for analysis of electronic information dissemination events
US9015842B2 (en) 2008-03-19 2015-04-21 Websense, Inc. Method and system for protection against information stealing software
US8407784B2 (en) 2008-03-19 2013-03-26 Websense, Inc. Method and system for protection against information stealing software
US9130986B2 (en) 2008-03-19 2015-09-08 Websense, Inc. Method and system for protection against information stealing software
US8374986B2 (en) 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
US8549581B1 (en) * 2008-05-28 2013-10-01 Zscaler, Inc. Distributed network security system deploying guard tables
EP2318955A1 (en) 2008-06-30 2011-05-11 Websense, Inc. System and method for dynamic and real-time categorization of webpages
US8018940B2 (en) * 2008-08-13 2011-09-13 Alcatel Lucent Network address lookup based on bloom filters
US7990973B2 (en) * 2008-08-13 2011-08-02 Alcatel-Lucent Usa Inc. Hash functions for applications such as network address lookup
US20100057737A1 (en) 2008-08-29 2010-03-04 Oracle International Corporation Detection of non-occurrences of events using pattern matching
CN103793522B (en) * 2008-10-20 2018-01-12 王英 Fast signature scan
JP5871619B2 (en) 2008-12-15 2016-03-01 アイ・ピー・リザブワー・エル・エル・シー Method and apparatus for high-speed processing of financial market depth data
US8145859B2 (en) * 2009-03-02 2012-03-27 Oracle International Corporation Method and system for spilling from a queue to a persistent store
US9130972B2 (en) 2009-05-26 2015-09-08 Websense, Inc. Systems and methods for efficient detection of fingerprinted data and information
US8321450B2 (en) 2009-07-21 2012-11-27 Oracle International Corporation Standardized database connectivity support for an event processing server in an embedded context
US8387076B2 (en) 2009-07-21 2013-02-26 Oracle International Corporation Standardized database connectivity support for an event processing server
US8527458B2 (en) 2009-08-03 2013-09-03 Oracle International Corporation Logging framework for a data stream processing server
US8386466B2 (en) 2009-08-03 2013-02-26 Oracle International Corporation Log visualization tool for a data stream processing server
US8332624B2 (en) * 2009-08-26 2012-12-11 Nokia Corporation Method and apparatus for encoding decision diagrams
US20110055221A1 (en) * 2009-08-26 2011-03-03 Sovio Sampo Juhani Method and apparatus for obtaining decision diagrams from unknown hash identifiers
GB201013195D0 (en) 2009-09-28 2010-09-22 Qinetiq Ltd Processor
JP5568277B2 (en) * 2009-10-22 2014-08-06 株式会社日立ハイテクノロジーズ Pattern matching method and pattern matching apparatus
US8959106B2 (en) 2009-12-28 2015-02-17 Oracle International Corporation Class loading using java data cartridges
US9305057B2 (en) 2009-12-28 2016-04-05 Oracle International Corporation Extensible indexing framework using data cartridges
US9430494B2 (en) 2009-12-28 2016-08-30 Oracle International Corporation Spatial data cartridge for event processing systems
US8478934B2 (en) * 2010-07-19 2013-07-02 Lsi Corporation Managing extended RAID caches using counting bloom filters
US9501795B1 (en) 2010-08-23 2016-11-22 Seth Gregory Friedman Validating an electronic order transmitted over a network between a client server and an exchange server with a hardware device
US8713049B2 (en) 2010-09-17 2014-04-29 Oracle International Corporation Support for a parameterized query/view in complex event processing
US8332367B2 (en) 2010-10-20 2012-12-11 International Business Machines Corporation Parallel data redundancy removal
US9189280B2 (en) 2010-11-18 2015-11-17 Oracle International Corporation Tracking large numbers of moving objects in an event processing system
US8407245B2 (en) 2010-11-24 2013-03-26 Microsoft Corporation Efficient string pattern matching for large pattern sets
US20120150887A1 (en) * 2010-12-08 2012-06-14 Clark Christopher F Pattern matching
JP6045505B2 (en) 2010-12-09 2016-12-14 アイピー レザボア, エルエルシー.IP Reservoir, LLC. Method and apparatus for managing orders in a financial market
US9674318B2 (en) 2010-12-09 2017-06-06 Solarflare Communications, Inc. TCP processing for devices
US9600429B2 (en) 2010-12-09 2017-03-21 Solarflare Communications, Inc. Encapsulated accelerator
US10873613B2 (en) 2010-12-09 2020-12-22 Xilinx, Inc. TCP processing for devices
US9258390B2 (en) 2011-07-29 2016-02-09 Solarflare Communications, Inc. Reducing network latency
US8996644B2 (en) 2010-12-09 2015-03-31 Solarflare Communications, Inc. Encapsulated accelerator
EP2656293B1 (en) 2010-12-22 2019-10-09 HyannisPort Research, Inc. Data capture and real time risk controls for electronic markets
US8990416B2 (en) 2011-05-06 2015-03-24 Oracle International Corporation Support for a new insert stream (ISTREAM) operation in complex event processing (CEP)
US9276911B2 (en) * 2011-05-13 2016-03-01 Indiana University Research & Technology Corporation Secure and scalable mapping of human sequencing reads on hybrid clouds
JP4944266B1 (en) * 2011-06-08 2012-05-30 義尚 神山 2-part character search software
US9329975B2 (en) 2011-07-07 2016-05-03 Oracle International Corporation Continuous query language (CQL) debugger in complex event processing (CEP)
JP5780036B2 (en) * 2011-07-26 2015-09-16 富士通株式会社 Extraction program, extraction method and extraction apparatus
US8763018B2 (en) 2011-08-22 2014-06-24 Solarflare Communications, Inc. Modifying application behaviour
EP2574000B1 (en) 2011-09-22 2020-04-08 Xilinx, Inc. Message acceleration
US8990070B2 (en) 2011-11-18 2015-03-24 International Business Machines Corporation Computer-based construction of arbitrarily complex formal grammar expressions
US9002772B2 (en) 2011-11-18 2015-04-07 International Business Machines Corporation Scalable rule-based processing system with trigger rules and rule evaluator
US9047243B2 (en) 2011-12-14 2015-06-02 Ip Reservoir, Llc Method and apparatus for low latency data distribution
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US10650452B2 (en) 2012-03-27 2020-05-12 Ip Reservoir, Llc Offload processing of data packets
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data
US9391840B2 (en) 2012-05-02 2016-07-12 Solarflare Communications, Inc. Avoiding delayed data
US9391841B2 (en) 2012-07-03 2016-07-12 Solarflare Communications, Inc. Fast linkup arbitration
US8977626B2 (en) 2012-07-20 2015-03-10 Apple Inc. Indexing and searching a data collection
US9563663B2 (en) 2012-09-28 2017-02-07 Oracle International Corporation Fast path evaluation of Boolean predicates
US11288277B2 (en) 2012-09-28 2022-03-29 Oracle International Corporation Operator sharing for continuous queries over archived relations
US10505747B2 (en) 2012-10-16 2019-12-10 Solarflare Communications, Inc. Feed processing
US10133802B2 (en) 2012-10-23 2018-11-20 Ip Reservoir, Llc Method and apparatus for accelerated record layout detection
US9633093B2 (en) 2012-10-23 2017-04-25 Ip Reservoir, Llc Method and apparatus for accelerated format translation of data in a delimited data format
EP2912579B1 (en) 2012-10-23 2020-08-19 IP Reservoir, LLC Method and apparatus for accelerated format translation of data in a delimited data format
US9241259B2 (en) 2012-11-30 2016-01-19 Websense, Inc. Method and apparatus for managing the transfer of sensitive information to mobile devices
US10956422B2 (en) 2012-12-05 2021-03-23 Oracle International Corporation Integrating event processing with map-reduce
US9117054B2 (en) 2012-12-21 2015-08-25 Websense, Inc. Method and aparatus for presence based resource management
US10298444B2 (en) 2013-01-15 2019-05-21 Oracle International Corporation Variable duration windows on continuous data streams
US9098587B2 (en) 2013-01-15 2015-08-04 Oracle International Corporation Variable duration non-event pattern matching
US9390135B2 (en) 2013-02-19 2016-07-12 Oracle International Corporation Executing continuous event processing (CEP) queries in parallel
US9047249B2 (en) 2013-02-19 2015-06-02 Oracle International Corporation Handling faults in a continuous event processing (CEP) system
US10742604B2 (en) 2013-04-08 2020-08-11 Xilinx, Inc. Locked down network interface
US9426124B2 (en) 2013-04-08 2016-08-23 Solarflare Communications, Inc. Locked down network interface
US9646035B1 (en) * 2013-04-26 2017-05-09 Veritas Technologies Llc Centralized metaobject ingest using a temporally-expanded bloom filter
US9418113B2 (en) 2013-05-30 2016-08-16 Oracle International Corporation Value based windows on relations in continuous data streams
EP2809033B1 (en) 2013-05-30 2018-03-21 Solarflare Communications Inc Packet capture in a network
US9092321B2 (en) * 2013-07-24 2015-07-28 NXGN Data, Inc. System and method for performing efficient searches and queries in a storage node
US9021189B2 (en) * 2013-07-24 2015-04-28 NXGN Data, Inc. System and method for performing efficient processing of data stored in a storage node
US10394751B2 (en) 2013-11-06 2019-08-27 Solarflare Communications, Inc. Programmed input/output mode
US10366452B2 (en) 2013-11-07 2019-07-30 Chicago Mercantile Exchange Inc. Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance
US10332206B2 (en) 2013-11-07 2019-06-25 Chicago Mercantile Exchange Inc. Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance
US11037239B2 (en) 2013-11-07 2021-06-15 Chicago Mercantile Exchange Inc. Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance
US10929926B2 (en) 2013-11-07 2021-02-23 Chicago Mercantile Exchange Inc. Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance
US20150127509A1 (en) 2013-11-07 2015-05-07 Chicago Mercantile Exchange Inc. Transactionally Deterministic High Speed Financial Exchange Having Improved, Efficiency, Communication, Customization, Performance, Access, Trading Opportunities, Credit Controls, and Fault Tolerance
US9691102B2 (en) 2013-11-07 2017-06-27 Chicago Mercantile Exchange Inc. Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance
US10692143B2 (en) 2013-11-07 2020-06-23 Chicago Mercantile Exchange Inc. Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance
US10467693B2 (en) 2013-11-07 2019-11-05 Chicago Mercantile Exchange Inc. Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance
US9934279B2 (en) 2013-12-05 2018-04-03 Oracle International Corporation Pattern matching across multiple input data streams
JP6517468B2 (en) 2014-01-10 2019-05-22 日本電気株式会社 INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, MONITORING APPARATUS, MONITORING METHOD, AND PROGRAM
JP5930228B2 (en) 2014-02-25 2016-06-08 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Information processing apparatus, method, and program
GB2541577A (en) 2014-04-23 2017-02-22 Ip Reservoir Llc Method and apparatus for accelerated data translation
US9244978B2 (en) 2014-06-11 2016-01-26 Oracle International Corporation Custom partitioning of a data stream
US9712645B2 (en) 2014-06-26 2017-07-18 Oracle International Corporation Embedded event processing
US10824952B2 (en) * 2014-09-22 2020-11-03 International Business Machines Corporation Reconfigurable array processor for pattern matching
US9886486B2 (en) 2014-09-24 2018-02-06 Oracle International Corporation Enriching events with dynamically typed big data for event processing
US10120907B2 (en) 2014-09-24 2018-11-06 Oracle International Corporation Scaling event processing using distributed flows and map-reduce operations
US9608863B2 (en) * 2014-10-17 2017-03-28 Cisco Technology, Inc. Address autoconfiguration using bloom filter parameters for unique address computation
US9891912B2 (en) 2014-10-31 2018-02-13 International Business Machines Corporation Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements
US10372700B2 (en) 2015-03-30 2019-08-06 International Business Machines Corporation Data filtering using a plurality of hardware accelerators
US9298934B1 (en) 2015-06-30 2016-03-29 Linkedin Corporation Managing presentation of online content
WO2017018901A1 (en) 2015-07-24 2017-02-02 Oracle International Corporation Visually exploring and analyzing event streams
US11164248B2 (en) 2015-10-12 2021-11-02 Chicago Mercantile Exchange Inc. Multi-modal trade execution with smart order routing
US11288739B2 (en) 2015-10-12 2022-03-29 Chicago Mercantile Exchange Inc. Central limit order book automatic triangulation system
US10942943B2 (en) 2015-10-29 2021-03-09 Ip Reservoir, Llc Dynamic field data translation to support high performance stream data processing
US10691731B2 (en) * 2015-11-26 2020-06-23 International Business Machines Corporation Efficient lookup in multiple bloom filters
WO2017135837A1 (en) 2016-02-01 2017-08-10 Oracle International Corporation Pattern based automated test data generation
WO2017135838A1 (en) 2016-02-01 2017-08-10 Oracle International Corporation Level of detail control for geostreaming
US20170286420A1 (en) * 2016-03-30 2017-10-05 Intel Corporation Pattern matching circuit
US10580100B2 (en) 2016-06-06 2020-03-03 Chicago Mercantile Exchange Inc. Data payment and authentication via a shared data structure
US11514448B1 (en) 2016-07-11 2022-11-29 Chicago Mercantile Exchange Inc. Hierarchical consensus protocol framework for implementing electronic transaction processing systems
US10417217B2 (en) 2016-08-05 2019-09-17 Chicago Mercantile Exchange Inc. Systems and methods for blockchain rule synchronization
US10748210B2 (en) 2016-08-09 2020-08-18 Chicago Mercantile Exchange Inc. Systems and methods for coordinating processing of scheduled instructions across multiple components
US10943297B2 (en) 2016-08-09 2021-03-09 Chicago Mercantile Exchange Inc. Systems and methods for coordinating processing of instructions across multiple components
US10678506B2 (en) * 2017-08-01 2020-06-09 Arm Limited Matching consecutive values in a data processing apparatus
US10699074B2 (en) * 2018-05-22 2020-06-30 Microsoft Technology Licensing, Llc Phrase-level abbreviated text entry and translation
CN109150161B (en) * 2018-07-02 2022-01-14 宁波大学 Bloom filter circuit for approximate member query in Hamming space
US10248646B1 (en) * 2018-08-22 2019-04-02 Cognigo Research Ltd. Token matching in large document corpora
US10664658B2 (en) 2018-08-23 2020-05-26 Microsoft Technology Licensing, Llc Abbreviated handwritten entry translation
US10880211B2 (en) 2019-05-06 2020-12-29 Seth Gregory Friedman Transaction encoding and verification by way of data-link layer fields
JP2022532230A (en) 2019-05-14 2022-07-13 エクセジー インコーポレイテッド Methods and systems for generating and delivering transaction signals from financial market data with low latency
US10868707B1 (en) 2019-09-16 2020-12-15 Liquid-Markets-Holdings, Incorporated Zero-latency message processing with validity checks
WO2021252423A1 (en) 2020-06-08 2021-12-16 Liquid-Markets-Holdings, Incorporated Hardware-based transaction exchange
GB202020155D0 (en) * 2020-12-18 2021-02-03 Palantir Technologies Inc Enforcing data security constraints in a data pipeline
US20220261900A1 (en) 2021-02-16 2022-08-18 Exegy Incorporated Methods and Systems for Joining Market Making at Low Latency

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3601808A (en) * 1968-07-18 1971-08-24 Bell Telephone Labor Inc Advanced keyword associative access memory system
US3611314A (en) * 1969-09-09 1971-10-05 Texas Instruments Inc Dynamic associative data processing system
US3824375A (en) * 1970-08-28 1974-07-16 Financial Security Syst Inc Memory system
US3729712A (en) * 1971-02-26 1973-04-24 Eastman Kodak Co Information storage and retrieval system
US3848235A (en) * 1973-10-24 1974-11-12 Ibm Scan and read control apparatus for a disk storage drive in a computer system
US3906455A (en) * 1974-03-15 1975-09-16 Boeing Computer Services Inc Associative memory device
CA1056504A (en) * 1975-04-02 1979-06-12 Visvaldis A. Vitols Keyword detection in continuous speech using continuous asynchronous correlation
US4298898A (en) * 1979-04-19 1981-11-03 Compagnie Internationale Pour L'informatique Cii Honeywell Bull Method of and apparatus for reading data from reference zones of a memory
US4314356A (en) * 1979-10-24 1982-02-02 Bunker Ramo Corporation High-speed term searcher
FR2481026B1 (en) * 1980-04-21 1984-06-15 France Etat
US4464718A (en) * 1982-07-30 1984-08-07 International Business Machines Corporation Associative file processing method and apparatus
US4550436A (en) * 1983-07-26 1985-10-29 At&T Bell Laboratories Parallel text matching methods and apparatus
US4941178A (en) * 1986-04-01 1990-07-10 Gte Laboratories Incorporated Speech recognition using preclassification and spectral normalization
US4823306A (en) * 1987-08-14 1989-04-18 International Business Machines Corporation Text search system
US5179626A (en) * 1988-04-08 1993-01-12 At&T Bell Laboratories Harmonic speech coding arrangement where a set of parameters for a continuous magnitude spectrum is determined by a speech analyzer and the parameters are used by a synthesizer to determine a spectrum which is used to determine senusoids for synthesis
US5023910A (en) * 1988-04-08 1991-06-11 At&T Bell Laboratories Vector quantization in a harmonic speech coding arrangement
US5050075A (en) * 1988-10-04 1991-09-17 Bell Communications Research, Inc. High performance VLSI data filter
US5249292A (en) * 1989-03-31 1993-09-28 Chiappa J Noel Data packet switch using a primary processing unit to designate one of a plurality of data stream control circuits to selectively handle the header processing of incoming packets in one data packet stream
JPH0314075A (en) * 1989-06-13 1991-01-22 Ricoh Co Ltd Document retrieval device
AU620994B2 (en) * 1989-07-12 1992-02-27 Digital Equipment Corporation Compressed prefix matching database searching
US5163131A (en) * 1989-09-08 1992-11-10 Auspex Systems, Inc. Parallel i/o network file server architecture
EP0565738A1 (en) * 1990-01-05 1993-10-20 Symbol Technologies, Inc. System for encoding and decoding data in machine readable graphic form
US5319776A (en) * 1990-04-19 1994-06-07 Hilgraeve Corporation In transit detection of computer virus with safeguard
US5497488A (en) * 1990-06-12 1996-03-05 Hitachi, Ltd. System for parallel string search with a function-directed parallel collation of a first partition of each string followed by matching of second partitions
GB9016341D0 (en) * 1990-07-25 1990-09-12 British Telecomm Speed estimation
US5255136A (en) * 1990-08-17 1993-10-19 Quantum Corporation High capacity submicro-winchester fixed disk drive
US5101424A (en) * 1990-09-28 1992-03-31 Northern Telecom Limited Method for generating a monitor program for monitoring text streams and executing actions when pre-defined patterns, are matched using an English to AWK language translator
GB9023096D0 (en) * 1990-10-24 1990-12-05 Int Computers Ltd Database search processor
US5339411A (en) * 1990-12-21 1994-08-16 Pitney Bowes Inc. Method for managing allocation of memory space
DE69229521T2 (en) * 1991-04-25 2000-03-30 Nippon Steel Corp Database discovery system
US5477451A (en) * 1991-07-25 1995-12-19 International Business Machines Corp. Method and system for natural language translation
US5488725A (en) * 1991-10-08 1996-01-30 West Publishing Company System of document representation retrieval by successive iterated probability sampling
US5265065A (en) * 1991-10-08 1993-11-23 West Publishing Company Method and apparatus for information retrieval from a database by replacing domain specific stemmed phases in a natural language to create a search query
US5826075A (en) * 1991-10-16 1998-10-20 International Business Machines Corporation Automated programmable fireware store for a personal computer system
WO1993018505A1 (en) * 1992-03-02 1993-09-16 The Walt Disney Company Voice transformation system
US5388259A (en) * 1992-05-15 1995-02-07 Bell Communications Research, Inc. System for accessing a database with an iterated fuzzy query notified by retrieval response
US5524268A (en) * 1992-06-26 1996-06-04 Cirrus Logic, Inc. Flexible processor-driven control of SCSI buses utilizing tags appended to data bytes to determine SCSI-protocol phases
GB9220404D0 (en) * 1992-08-20 1992-11-11 Nat Security Agency Method of identifying,retrieving and sorting documents
US5721898A (en) * 1992-09-02 1998-02-24 International Business Machines Corporation Method and system for data search in a data processing system
US6044407A (en) * 1992-11-13 2000-03-28 British Telecommunications Public Limited Company Interface for translating an information message from one protocol to another
US5481735A (en) * 1992-12-28 1996-01-02 Apple Computer, Inc. Method for modifying packets that meet a particular criteria as the packets pass between two layers in a network
US5440723A (en) * 1993-01-19 1995-08-08 International Business Machines Corporation Automatic immune system for computers and computer networks
US5432822A (en) * 1993-03-12 1995-07-11 Hughes Aircraft Company Error correcting decoder and decoding method employing reliability based erasure decision-making in cellular communication system
US5546462A (en) * 1993-04-09 1996-08-13 Washington University Method and apparatus for fingerprinting and authenticating various magnetic media
US5544352A (en) * 1993-06-14 1996-08-06 Libertech, Inc. Method and apparatus for indexing, searching and displaying data
DE69429061T2 (en) * 1993-10-29 2002-07-18 Advanced Micro Devices Inc Superskalarmikroprozessoren
US5371794A (en) * 1993-11-02 1994-12-06 Sun Microsystems, Inc. Method and apparatus for privacy and authentication in wireless networks
US5813000A (en) * 1994-02-15 1998-09-22 Sun Micro Systems B tree structure and method
US5465353A (en) * 1994-04-01 1995-11-07 Ricoh Company, Ltd. Image matching and retrieval by multi-access redundant hashing
US5461712A (en) * 1994-04-18 1995-10-24 International Business Machines Corporation Quadrant-based two-dimensional memory manager
US5623652A (en) * 1994-07-25 1997-04-22 Apple Computer, Inc. Method and apparatus for searching for information in a network and for controlling the display of searchable information on display devices in the network
JP2964879B2 (en) * 1994-08-22 1999-10-18 日本電気株式会社 Post filter
SE505156C2 (en) * 1995-01-30 1997-07-07 Ericsson Telefon Ab L M Procedure for noise suppression by spectral subtraction
US5819290A (en) * 1995-04-10 1998-10-06 Sony Corporation Data recording and management system and method for detecting data file division based on quantitative number of blocks
US5943421A (en) 1995-09-11 1999-08-24 Norand Corporation Processor having compression and encryption circuitry
JPH0981574A (en) * 1995-09-14 1997-03-28 Fujitsu Ltd Method and system for data base retrieval using retrieval set display picture
US6134551A (en) * 1995-09-15 2000-10-17 Intel Corporation Method of caching digital certificate revocation lists
US5701464A (en) * 1995-09-15 1997-12-23 Intel Corporation Parameterized bloom filters
US5774839A (en) * 1995-09-29 1998-06-30 Rockwell International Corporation Delayed decision switched prediction multi-stage LSF vector quantization
US5864738A (en) * 1996-03-13 1999-01-26 Cray Research, Inc. Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
US5781921A (en) * 1996-05-06 1998-07-14 Ohmeda Inc. Method and apparatus to effect firmware upgrades using a removable memory device under software control
GB2314433A (en) * 1996-06-22 1997-12-24 Xerox Corp Finding and modifying strings of a regular language in a text
US6147976A (en) * 1996-06-24 2000-11-14 Cabletron Systems, Inc. Fast network layer packet filter
US5995963A (en) * 1996-06-27 1999-11-30 Fujitsu Limited Apparatus and method of multi-string matching based on sparse state transition list
US5991881A (en) * 1996-11-08 1999-11-23 Harris Corporation Network surveillance system
JP3231673B2 (en) * 1996-11-21 2001-11-26 シャープ株式会社 Character and character string search method and recording medium used in the method
DE19651075A1 (en) * 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
US6073160A (en) * 1996-12-18 2000-06-06 Xerox Corporation Document communications controller
US6028939A (en) * 1997-01-03 2000-02-22 Redcreek Communications, Inc. Data security system and method
US6070172A (en) * 1997-03-06 2000-05-30 Oracle Corporation On-line free space defragmentation of a contiguous-file file system
US5930753A (en) * 1997-03-20 1999-07-27 At&T Corp Combining frequency warping and spectral shaping in HMM based speech recognition
JP3372455B2 (en) * 1997-07-03 2003-02-04 富士通株式会社 Packet relay control method, packet relay device, and program storage medium
US6067569A (en) * 1997-07-10 2000-05-23 Microsoft Corporation Fast-forwarding and filtering of network packets in a computer system
US6317795B1 (en) * 1997-07-22 2001-11-13 International Business Machines Corporation Dynamic modification of multimedia content
JPH11110320A (en) 1997-10-03 1999-04-23 Matsushita Electric Ind Co Ltd Message exchange device
US6138176A (en) * 1997-11-14 2000-10-24 3Ware Disk array controller with automated processor which routes I/O data according to addresses and commands received from disk drive controllers
WO1999027684A1 (en) 1997-11-25 1999-06-03 Packeteer, Inc. Method for automatically classifying traffic in a packet communications network
US5987610A (en) 1998-02-12 1999-11-16 Ameritech Corporation Computer virus screening methods and systems
KR100441171B1 (en) * 1998-02-20 2004-10-14 삼성전자주식회사 Firmware composing method using flash rom and ram
US6279113B1 (en) * 1998-03-16 2001-08-21 Internet Tools, Inc. Dynamic signature inspection-based network intrusion detection
US6389532B1 (en) * 1998-04-20 2002-05-14 Sun Microsystems, Inc. Method and apparatus for using digital signatures to filter packets in a network
US6397259B1 (en) 1998-05-29 2002-05-28 Palm, Inc. Method, system and apparatus for packet minimized communications
US6105067A (en) * 1998-06-05 2000-08-15 International Business Machines Corp. Connection pool management for backend servers using common interface
US6289461B1 (en) * 1998-06-09 2001-09-11 Placeware, Inc. Bi-directional process-to-process byte stream protocol
US6169969B1 (en) * 1998-08-07 2001-01-02 The United States Of America As Represented By The Director Of The National Security Agency Device and method for full-text large-dictionary string matching using n-gram hashing
GB9819183D0 (en) * 1998-09-04 1998-10-28 Int Computers Ltd Multiple string search method
US6226676B1 (en) * 1998-10-07 2001-05-01 Nortel Networks Corporation Connection establishment and termination in a mixed protocol network
US7181548B2 (en) * 1998-10-30 2007-02-20 Lsi Logic Corporation Command queueing engine
US6499107B1 (en) 1998-12-29 2002-12-24 Cisco Technology, Inc. Method and system for adaptive network security using intelligent packet analysis
US6578147B1 (en) 1999-01-15 2003-06-10 Cisco Technology, Inc. Parallel intrusion detection sensors with load balancing for high speed networks
US6765918B1 (en) 1999-06-16 2004-07-20 Teledata Networks, Ltd. Client/server based architecture for a telecommunications network
US6463474B1 (en) 1999-07-02 2002-10-08 Cisco Technology, Inc. Local authentication of a client at a network device
GB2352548B (en) 1999-07-26 2001-06-06 Sun Microsystems Inc Method and apparatus for executing standard functions in a computer system
US6804667B1 (en) 1999-11-30 2004-10-12 Ncr Corporation Filter for checking for duplicate entries in database
US20010047473A1 (en) * 2000-02-03 2001-11-29 Realtime Data, Llc Systems and methods for computer initialization
US6877044B2 (en) * 2000-02-10 2005-04-05 Vicom Systems, Inc. Distributed storage management platform architecture
US6711558B1 (en) * 2000-04-07 2004-03-23 Washington University Associative database scanning and information retrieval
US7139743B2 (en) * 2000-04-07 2006-11-21 Washington University Associative database scanning and information retrieval using FPGA devices
US6381242B1 (en) * 2000-08-29 2002-04-30 Netrake Corporation Content processor
US6807156B1 (en) 2000-11-07 2004-10-19 Telefonaktiebolaget Lm Ericsson (Publ) Scalable real-time quality of service monitoring and analysis of service dependent subscriber satisfaction in IP networks
US7325249B2 (en) * 2001-04-30 2008-01-29 Aol Llc Identifying unwanted electronic messages
US6785677B1 (en) 2001-05-02 2004-08-31 Unisys Corporation Method for execution of query to search strings of characters that match pattern with a target string utilizing bit vector
US7152151B2 (en) * 2002-07-18 2006-12-19 Ge Fanuc Embedded Systems, Inc. Signal processing resource for selective series processing of data in transit on communications paths in multi-processor arrangements
US7835966B2 (en) * 2001-09-17 2010-11-16 Recognia Inc. Technical analysis formation recognition using pivot points
US6772345B1 (en) 2002-02-08 2004-08-03 Networks Associates Technology, Inc. Protocol-level malware scanner
US6901461B2 (en) * 2002-12-31 2005-05-31 Intel Corporation Hardware assisted ATA command queuing
TW591532B (en) * 2003-03-07 2004-06-11 Mediatek Inc Firmware structuring method and related apparatus for unifying handling of execution responses of subroutines
US7444515B2 (en) * 2003-08-14 2008-10-28 Washington University Method and apparatus for detecting predefined signatures in packet payload using Bloom filters
US7411957B2 (en) * 2004-03-26 2008-08-12 Cisco Technology, Inc. Hardware filtering support for denial-of-service attacks
US7660865B2 (en) * 2004-08-12 2010-02-09 Microsoft Corporation Spam filtering with probabilistic secure hashes
EP1859378A2 (en) * 2005-03-03 2007-11-28 Washington University Method and apparatus for performing biosequence similarity searching
US7801910B2 (en) * 2005-11-09 2010-09-21 Ramp Holdings, Inc. Method and apparatus for timed tagging of media content
US20070179935A1 (en) * 2006-01-31 2007-08-02 Tsern-Huei Lee Apparatus and method for efficient data pre-filtering in a data stream

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LANCASTER, JOSEPH M.: "WUCSE-2006-21: Design and Evaluation of a BLAST Ungapped Extension Accelerator, Master's Thesis", May 2006, WASHINGTON UNIVERSITY IN ST. LOUIS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009177335A (en) * 2008-01-22 2009-08-06 Nippon Telegr & Teleph Corp <Ntt> Stream data processing method, stream data processing program, and stream data processing system

Also Published As

Publication number Publication date
EP2421223A2 (en) 2012-02-22
EP2421223A3 (en) 2012-05-09
EP2421223B1 (en) 2016-06-29
US20070260602A1 (en) 2007-11-08
US7636703B2 (en) 2009-12-22
EP2014054A2 (en) 2009-01-14
JP5240475B2 (en) 2013-07-17
CA2650571C (en) 2015-08-18
CA2650571A1 (en) 2007-11-15
WO2007130818A3 (en) 2008-02-28
EP2014054B1 (en) 2015-12-02
JP2009535747A (en) 2009-10-01

Similar Documents

Publication Publication Date Title
CA2650571C (en) Method and apparatus for approximate pattern matching
US11568674B2 (en) Fast signature scan
Kumar et al. Advanced algorithms for fast and scalable deep packet inspection
US20220093210A1 (en) System and method for characterizing biological sequence data through a probabilistic data structure
US9952983B2 (en) Programmable intelligent search memory enabled secure flash memory
Pao et al. A memory-efficient pipelined implementation of the aho-corasick string-matching algorithm
CN112866023B (en) Network detection method, model training method, device, equipment and storage medium
US20060184556A1 (en) Compression algorithm for generating compressed databases
US7868792B2 (en) Generating a boundary hash-based hierarchical data structure associated with a plurality of known arbitrary-length bit strings and using the generated hierarchical data structure for detecting whether an arbitrary-length bit string input matches one of a plurality of known arbitrary-length bit springs
US20060193159A1 (en) Fast pattern matching using large compressed databases
JP2014238892A (en) Method, computer system and computer program for retrieving secured data
Cheng et al. Scalable multi-match packet classification using TCAM and SRAM
KR20230170891A (en) In-memory efficient multistep search
US20120158635A1 (en) Storage efficient programmable state machine
Jin et al. Efficient string sort with multi-character encoding and adaptive sampling
Wang et al. GenMatcher: A generic clustering-based arbitrary matching framework
CN110110177B (en) Graph-based malicious software family clustering evaluation method and device
Pinkas et al. A simple recursive tree oblivious ram
Hedström et al. Improved Pattern Generation for Bloom Filters with Bit Patterns Optimizing bit patterns for use in blocked Bloom filters
Gupta et al. N-Dimensional Structure: A Data Structure with Fast Access and Sorting of Integers
Natarajan et al. Payload inspection using parallel Bloom filter in dual core processor
Sahni et al. Context and Content Aware Routing of Managed Information Objects
Yoon et al. Asymmetric Sparse Bloom Filter
Song Design and Evaluation of Packet Classification Systems, Doctoral Dissertation, December 2006

Legal Events

Date Code Title Description
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2009509952

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2650571

Country of ref document: CA

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007761209

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07761209

Country of ref document: EP

Kind code of ref document: A2