WO2007149495A3 - Program binding system, method and software for a resilient integrated circuit architecture - Google Patents

Program binding system, method and software for a resilient integrated circuit architecture Download PDF

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Publication number
WO2007149495A3
WO2007149495A3 PCT/US2007/014395 US2007014395W WO2007149495A3 WO 2007149495 A3 WO2007149495 A3 WO 2007149495A3 US 2007014395 W US2007014395 W US 2007014395W WO 2007149495 A3 WO2007149495 A3 WO 2007149495A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
computational
type
software
communication
Prior art date
Application number
PCT/US2007/014395
Other languages
French (fr)
Other versions
WO2007149495A2 (en
Inventor
Steven Hennick Kelem
Original Assignee
Element Cxi Llc
Steven Hennick Kelem
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/471,832 external-priority patent/US7427871B2/en
Priority claimed from US11/471,875 external-priority patent/US7429870B2/en
Application filed by Element Cxi Llc, Steven Hennick Kelem filed Critical Element Cxi Llc
Publication of WO2007149495A2 publication Critical patent/WO2007149495A2/en
Publication of WO2007149495A3 publication Critical patent/WO2007149495A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17362—Indirect interconnection networks hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re¬ assigned and new data routings established.
PCT/US2007/014395 2006-06-21 2007-06-20 Program binding system, method and software for a resilient integrated circuit architecture WO2007149495A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/471,832 2006-06-21
US11/471,832 US7427871B2 (en) 2006-06-21 2006-06-21 Fault tolerant integrated circuit architecture
US11/471,875 2006-06-21
US11/471,875 US7429870B2 (en) 2006-06-21 2006-06-21 Resilient integrated circuit architecture

Publications (2)

Publication Number Publication Date
WO2007149495A2 WO2007149495A2 (en) 2007-12-27
WO2007149495A3 true WO2007149495A3 (en) 2008-12-18

Family

ID=38834089

Family Applications (5)

Application Number Title Priority Date Filing Date
PCT/US2007/014465 WO2007149527A2 (en) 2006-06-21 2007-06-20 Fault tolerant integrated circuit architecture
PCT/US2007/014395 WO2007149495A2 (en) 2006-06-21 2007-06-20 Program binding system, method and software for a resilient integrated circuit architecture
PCT/US2007/014394 WO2007149494A2 (en) 2006-06-21 2007-06-20 Resilient integrated circuit architecture
PCT/US2007/014474 WO2007149532A2 (en) 2006-06-21 2007-06-20 Compiler system, method and software for a resilient integrated circuit architecture
PCT/US2007/014353 WO2007149472A2 (en) 2006-06-21 2007-06-20 Element controller for a resilient integrated circuit architecture

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2007/014465 WO2007149527A2 (en) 2006-06-21 2007-06-20 Fault tolerant integrated circuit architecture

Family Applications After (3)

Application Number Title Priority Date Filing Date
PCT/US2007/014394 WO2007149494A2 (en) 2006-06-21 2007-06-20 Resilient integrated circuit architecture
PCT/US2007/014474 WO2007149532A2 (en) 2006-06-21 2007-06-20 Compiler system, method and software for a resilient integrated circuit architecture
PCT/US2007/014353 WO2007149472A2 (en) 2006-06-21 2007-06-20 Element controller for a resilient integrated circuit architecture

Country Status (6)

Country Link
US (17) US8850411B2 (en)
EP (2) EP2033316A4 (en)
JP (2) JP5420401B2 (en)
KR (1) KR101444075B1 (en)
TW (3) TWI436590B (en)
WO (5) WO2007149527A2 (en)

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US20080036488A1 (en) 2008-02-14
JP2009541853A (en) 2009-11-26
EP2033316A4 (en) 2010-08-11
WO2007149494A3 (en) 2008-12-04
US20080040722A1 (en) 2008-02-14
WO2007149527A3 (en) 2009-02-05
US7750672B2 (en) 2010-07-06
US8072239B2 (en) 2011-12-06
WO2007149494A2 (en) 2007-12-27
US8850411B2 (en) 2014-09-30
KR101444075B1 (en) 2014-09-26
WO2007149495A2 (en) 2007-12-27
JP5420401B2 (en) 2014-02-19
US7880497B2 (en) 2011-02-01
US20080036493A1 (en) 2008-02-14
JP2009542098A (en) 2009-11-26
WO2007149532A3 (en) 2008-12-18
US20100244889A1 (en) 2010-09-30
WO2007149527A2 (en) 2007-12-27
TW200901032A (en) 2009-01-01
US20100308862A1 (en) 2010-12-09
US8384416B2 (en) 2013-02-26
US20130305205A1 (en) 2013-11-14
TW200901624A (en) 2009-01-01
TW200900916A (en) 2009-01-01
US20120153989A1 (en) 2012-06-21
TWI436590B (en) 2014-05-01
US20130127491A1 (en) 2013-05-23
US20080040727A1 (en) 2008-02-14
US20080036489A1 (en) 2008-02-14
US8516427B2 (en) 2013-08-20
US7397275B2 (en) 2008-07-08
US20110260750A1 (en) 2011-10-27
EP2033315B1 (en) 2013-11-27
KR20090051158A (en) 2009-05-21
US20140351782A1 (en) 2014-11-27
US20130229204A1 (en) 2013-09-05
JP5491176B2 (en) 2014-05-14
US7548084B2 (en) 2009-06-16
EP2033315A2 (en) 2009-03-11
WO2007149472A3 (en) 2009-02-26
US7982489B2 (en) 2011-07-19
US8446166B2 (en) 2013-05-21
US8776001B2 (en) 2014-07-08
WO2007149472A2 (en) 2007-12-27
US20120098565A1 (en) 2012-04-26
EP2033315A4 (en) 2010-08-11
EP2033316A2 (en) 2009-03-11
US20100033207A1 (en) 2010-02-11
WO2007149532A2 (en) 2007-12-27
TWI441078B (en) 2014-06-11
US20080297196A1 (en) 2008-12-04
US8618830B2 (en) 2013-12-31
US20150135191A1 (en) 2015-05-14
US7616024B2 (en) 2009-11-10

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