WO2008005592A1

WO2008005592A1 - Computation of a mod (2 n - 1)

Info

Publication number: WO2008005592A1
Application number: PCT/US2007/064370
Authority: WO
Inventors: Qiang Shen
Original assignee: Via Telecom Co., Ltd.
Priority date: 2006-07-07
Filing date: 2007-03-20
Publication date: 2008-01-10
Also published as: EP1876523A1; US7849125B2; CN101021777B; CN101021777A; US20080010332A1

Abstract

A system and method for computing A mod (2n-1), where A is an m bit quantity, where n is a positive integer, where m is greater than or equal to n. The quantity A may be partitioned into a plurality of sections, each being at most n bits long. The value A mod (2n-1) may be computed by adding the sections in mod(2n-1) fashion. This addition of the sections of A may be performed in a single clock cycle using an adder tree, or, sequentially in multiple clock cycles using a two-input adder circuit provided the output of the adder circuit is coupled to one of the two inputs. The computation A mod (2n-1) may be performed as a part of an interleaving/deinterleaving operation, or, as part of an encryption/decryption operation.

Description

COMPUTATION OF A MOD (2 N - 1)

Field of the Invention

[0001] The present invention relates generally to the field of fixed-point arithmetic realizations, more specifically, to systems and methods for computing the modulo operation corresponding to divisor (2ⁿ-l).

Description of the Related Art

[0002] As used herein the expression ^vlx mod r", where x is an integer and r is a positive integer, is defined as the nonnegative integer y. less than r, in the set {x-kr: ke Z}, where Z represents the set of integers. For example, 8 mod 5 equals 3. As another example, 101 mod 10 equals 1. When x is positive, '"x mod r" may be interpreted as the remainder resulting from the division of x by r.

[0003] There are many situations in which A mod (2ⁿ-l) needs to be computed, where

A is an m bit binary word, where in and n are positive integers. For example, A mod

(2ⁿ-l) needs to be computed when performing data interleaving or deinterleaving according to the CDMA2000 High Rate Packet Data Air Interface Specification,

3GPP2 C.S0024-A, Ver2.0, July 2005.

[0004] When m is less than n. A mod (2ⁿ-l) is simply A itself. Thus, in the case m<n, the computation of A mod (2ⁿ-l) is trivial.

[0005] When m is greater than or equal to n, the computation of A mod (2ⁿ-l) is nontrivial.

[0006] Re to Zimmeπnann discloses a method for the computation of X mod (2ⁿ-l) in the case where X is (n+1) bits in length, i.e., the case m=nϊ 1. See the paper entitled

"Efficient VLSI implementation of modulo (2" ± 1) addition and multiplication." published in the Proceedings of 14th IEEE Symposium on Computer Arithmetic,

1999. However, Zimmermann's method does not generalize to other values of m.

[0007] Thus, there exists a need for circuits, systems and methods for computing A mod (2ⁿ-l) in the case where m is greater than or equal to n. Summary of the Invention

[0008] In one set of embodiments, a system for computing A mod (2ⁿ-l ), where A is an m-bit quantity, where m is an integer greater than or equal to two, where n is a positive integer less than or equal to m, may include a plurality of adder circuits. Each of the adder circuits may be configured to operate on two n-bit operands in order to produce an n-bit output The plurality of adder circuits may be coupled to form a tree structure. The quantity A is partitioned into a plurality of sections, where each of the sections includes up to n consecutive bits of the quantity A. Each of the sections may be supplied to exactly one of the adder circuits to determine one of the two n-bit input operands of that adder circuit.

[0009] Each of the adder circuits may include: a first n-bit adder configured to operate on the two n-bit operands in order to produce an intermediate n-bit result; and a second n-bit adder configured to operate on the intermediate n-bit result and on a carryout signal from the first n-bit adder in order to produce the n-bit output. [0010] In another set of embodiments, a system for computing A mod (2ⁿ-l). where A is an m-bit quantity, where m is an integer greater than or equal to two, where n is a positive integer less than or equal to m, may include an adder circuit. The adder circuit may be configured to operate on two n-bit inputs and to produce an n-bit output. The output of the adder circuit may be coupled to a first of the two inputs. [0011] The adder circuit may include: a first n-bit adder configured to operate on the two n-bit operands in order to produce an intermediate n-bit result; and a second n-bit adder configured to operate on the intermediate n-bit result and on a carryout signal from the first n-bit adder in order to produce the n-bit output.

[0012] A plurality of sections of the quantity A may be presented to a second of the two inputs in a plurality of cycles (of a clock signal) respectively. Each of the sections may include up to n consecutive bits of the quantity A. [0013] In yet another set of embodiments, a method for computing A mod (2ⁿ-l ), where A is an m-bit quantity, where m is an integer greater than or equal to two, where n is a positive integer less than or equal to m, may involve: (a) receiving the m-bit quantity A; (b) extracting a section of the quantity A, where the section includes up to n consecutive bits of the quantity Λ;

(c) adding the section to a value of a register;

(d) adding one to the register value if the register value is greater than 2ⁿ- 1 , where said adding of one is performed modulo 2ⁿ;

(e) repeating (b), (c) and (d) until the quantity A is exhausted; and

(f) setting the register value equal to 7ero if the register value equals 2ⁿ-l . [0014] In yet another set of embodiments, a method for computing A mod (2ⁿ-l), where A is an m-bit quantity, where m is an integer greater than or equal to two, where n is a positive integer less than or equal to m, may involve performing a number of addition operations in a sequence of stages. Each of the stages may include performing a corresponding subset of the number of addition operations in a parallel fashion. The subset of addition operations of each stage may receive corresponding input data and generate corresponding output data. The input data of each stage, except for a first of the stages, may include at least a portion of the output data of a previous one of the stages. The input data of the first stage may include a plurality of sections of the quantity A. Each of the sections may include at most n consecutive bits of the quantity A. Each of the number of addition operations may include performing a first n-bit addition and a second n-bit addition, where the second n-bit addition operates on an intermediate result and a carry out produced by the first n-bit addition.

[0015] The method may further comprise selecting either the value zero or the output data from a last of the stages depending on a comparison of the value (2ⁿ-l) and the output data from the last stage, where the selected value equals A mod f2ⁿ-l). [0016] Any of the various method embodiments disclosed herein (or any combinations thereof or portions thereof) may be implemented in terms of program instructions. The program instructions may be stored in (or on) any of various memory media. A memory medium is a medium configured for the storage of information. Examples of memory media include various kinds of magnetic media (e.g.. magnetic tape, magnetic disk, magnetic strips, and magnetic film); various kinds of optical media (e.g., CD-ROM); various kinds of semiconductor RAM and ROM; various media based on the storage of electrical charge or other physical quantities; etc.

[0017] Furthermore, various embodiments of a system including a memory and a processor are contemplated, where the memory is configured to store program instructions and the processor is configured to read and execute the program instructions from the memory. In various embodiments, the program instructions encode corresponding ones of the method embodiments described herein (or combinations thereof or portions thereof).

Brief Description of the Drawings

[0018] The following detailed description makes reference to the accompanying drawings, which are now briefly described.

[0019] Figure IA illustrates an adder circuit employing feedback in order to compute the value A mod (2ⁿ-l) in a number of clock cycles.

[0020] Figure IB illustrates one embodiment of a system configured to extract sections of an m-bit quantity A and to operate on the sections in order to compute A mod (2ⁿ-l) in a number of clock cycles.

[0021] Figure 1C one embodiment of a circuit configured to extract successive sections of the quantity A.

[0022] Figure 2A illustrates one embodiment of an adder tree configured to compute

A mod (2^π- 1) in the case m=35 and n=4.

[0023] Figure 2B illustrates another embodiment of an adder tree configured to compute Λ mod (2ⁿ-l) in the case m=35 and n=4.

[0024] Figure 3Λ illustrates yet another embodiment of an adder tree configured to compute A mod (2ⁿ-l ) in the case m=35 and n=4,

[0025] Figure 3B illustrates one embodiment of an adder tree configured to compute

A mod (2ⁿ-l) in the case m=31 and n=4.

[0026] Figure 3C illustrates one embodiment of an adder tree configured to compute

A mod (2ⁿ-l) in the case m=21 and n=8.

[0027] Figure 3D illustrates one embodiment of an adder tree configured to compute

A mod (2ⁿ-l) in the case m=l 1 and n=6.

[0028] Figure 4 illustrates one embodiment of an adder tree configured to compute A mod (2ⁿ-l) in the case m=15 and n=3.

[0029] Figure 5 illustrates one embodiment of an adder circuit V_n configured to implement the computation (X+ Y) mod(2ⁿ-l) on two n bit operands X and Y.

[0030] Figure 6 illustrates one embodiment of a circuit G_n including two n-bit adders.

[0031] Figure 7 illustrates one embodiment of an adder tree employing copies of the circuit G_n in the case n=4. [0032] Figure 8 illustrates one embodiment of a system for computing A mod (2ⁿ-l), the system including an adder tree structure and a mapping circuit. [0033] Figure 9 illustrates one embodiment of a system for computing Λ mod (2ⁿ-l) hi a number of computational cycles using feedback.

[0034] Figure 1OA illustrates one embodiment of a method (e.g., a computer- implemented method) for computing A mod (2ⁿ-l) in a sequential fashion. [0035] Figure 1OB illustrates one embodiment of a method for computing A mod (2ⁿ- 1) in a plurality of stages, each including a number of parallel addition operations. [0036] Figure IOC illustrates one embodiment of a method for accessing a data symbol from memory as part of an interleaving operation or deinterleaving operation. [0037] Figure 11 illustrates one embodiment of a computer system for computing A mod (2ⁿ-l ) on an m bit quantity A.

[0038] While the invention is described herein by way of example for several embodiments and illustrative drawings, those skilled in the art will recognize that the invention is not limited to the embodiments or drawings described. It should be understood, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description or the claims. As used throughout this specification, the word "may" is used in a permissive sense (i.e., in the sense of "having the potential to"), rather than in the mandatory sense (i.e., in the sense of "must"). Furthermore, the phrase "A includes B" is used to mean 'A includes B. but is not limited to B".

Detailed Description of the Invention

[0039] Let A<m> denote an m-bit binary word, where m is an integer greater than or equal to two.

[0040] Let n be a positive integer less than or equal to m.

[0041] Let k =

ln , where \_x\ denotes the floor of x, i.e., the greatest integer which is less than or equal to x, In other words, k is the result of dividing m by n and then rounding down to the nearest integer.

[0042] Observe that the m-bit word A<m> can be represented as a concatenation of k consecutive n-bit sections and a terminal section having (m-kn) bits:

A < m > = A₁ < m - kn > A_k_ < n > A_k_₂ < n > . , . A₁ < n > A₀ < n > , (1)

[0043] In general, the notation X<r> is meant to indicate an r-bit binary word X. [0044] The value of the binary word A can be expressed in terms of the values of the sections as follows:

A = i, 2^fø i- A_k__{ 2^(k-^ϊ)n + Λ_t__? 2⁽ⁱ-²⁾" 4- . . . t- A₁2" - A₆ . (2)

[0045] It is a basic mathematical fact that 2^β mod (2ⁿ- 1) = 1. Furthermore,

T mod (2ⁿ- I) = I where j is any non-negative integer. [0046] Thus, it follows that

A mod(2" - 1) = ( 4 + A_k__x 4- A_L_₂ + . . . + A^ A₀) mod(2" - 1) . (3)

[0047] Therefore, given an adder circuit V_n 10 that implements the compulation X4-Y mod (2ⁿ-l) on two n-bit quantities X and Y to produce an n-bit output Z, the computation of A modulo (2¹M) may be implemented in a sequential fashion as suggested by Figure IA. The quantities Ao, Ai, A₂, ..., Ak i, A^ may be supplied to the X input of the adder circuit V_n 10 in successive cycles of the clock signal CLK. The output 2 of the adder circuit V_n 10 may be fed back to the input Y so that the adder circuit V_n 10 implements the iterative computation:

Z_J = A^ Z_J i mod (2ⁿ-l) (4) for j=0, 1. 2, ... , k. The output Z_k from the last cycle represents A mod (2ⁿ-l). Because addition operation (based on any modulus) is both commutative and associative, the order of presentation of the quantities Ao, Ai, A₂, ..., A_{k 1}, A^ to the adder circuit V_n 10 does not matter so far as the final output is concerned. [0048] In some embodiments, a section extraction circuit SEC 50 may be provided to extract the quantities Ao, Ai, A₂, ..., A_k-i, A^ from the binary word A and to present the quantities Ao, Ai, A₂, ..., A_U , A^ to the adder circuit V_n in successive clock cycles, e.g., as suggested in Figure I B.

[0049] The section extraction circuit SEC 50 may include a multiplexer 51, an m-bit register 52, a shift unit 53 and a control unit 54 as illustrated in Figure 1C. In a first clock cycle, the multiplexer 51 may initially select the m-bit binary word A and forward the binary word A to the m-bit register 52. Register 52 receives and stores the binary word A. The m-bit output of the register 52 is provided to the shift unit 53. The least significant n bits of the register output may be interpreted as the output of the section extraction unit SEC. The shift unit 53 receives the m-bit output of the register 52 and shifts the register output by n-bits to the right in order to generate a shifted value. In a second clock cycle, the control unit 54 directs multiplexer 51 to select the shifted value from the shift unit 53. Thus, the shifted value gets stored in register 52 and gets shifted again by shift unit 53. In a third clock cycle, the control unit 54 directs multiplexer 51 to select the doubly shifted value. In every clock cycle after the first clock cycle the control unit 54 may direct the multiplexer to select the output of the shift unit Therefore, in successive clock cycles, successive ones of the sections Ao, Ai, A₂, ..., An, A^ will appear at the output of the section extraction unit SEC 50. The control unit 54 may receive the clock signal CLK and control the selection action of the multiplexer 51, the storage action of the register 52, and the shifting action of the shift unit 53. For example, the control unit may induce the register 52 to capture data on rising edges of the clock CLK and induce the shift unit

53 to perform the shifting action on falling edges of the clock CLK. The control unit

54 may reinitialize itself, in anticipation of the next binary word A to be processed, in response to the assertion of an initialization signal TNIT.

[0050] If nα is a multiple of n, the value (m-kn) equals zero, and thus, the quantity A^ is vacuous. Therefore, in this case, only the quantities Ao, Ai, Aj, ..., A^ ₁ need be presented to the adder circuit V_n, and the computation of A mod (2ⁿ-l) may be completed in k computational cycles.

[0051] In one set of embodiments, the computation of A modulo (2¹M) may be implemented, e.g., in one clock cycle, by an adder tree formed from copies of the adder circuit V_n. Figure 2 A illustrates one embodiment of an adder tree 100 configured for the case m=35 and n=4. The adder tree 100 has four stages including eight copies of the adder circuit V₄. In the first stage, adder circuits 101 , 102, 103 and

104 each receive a corresponding pair of the 4-bit quantities Ao, Ai, A₂, ..., A? The 4-bit outputs of these adder circuits are fed to adder circuits 105 and 106 of the second stage. In particular, adder circuits 101 and 102 feed adder circuit 105, while adder circuits 103 and 104 feed adder circuit 106. The 4-bit outputs of adder circuits

105 and 106 feed adder circuit 107 of the third stage. The adder circuit 108 of the fourth stage receives the 4-bit output of adder circuit 107 and also receives the 3 -bit quantity Ag, the only quantity that didn't get consumed in the first stage. The 4-bit output of adder circuit 108 represents the result A mod (2 -1), i.e., A mod 15. [0052] In general, the number c of inputs to the adder tree is given by: c = \ m l n , where [^ denotes the ceiling of x. Furthermore, the number n_L of levels in the adder tree is given by the expressions:

c

In other words, the adder tree depth ni, equals the ceiling of the base-2 logarithm of the ceiling of vain. For example, in the case illustrated in Figure 2A, m=35 and n=4.

Thus, c=9, d=3.17 and n_L=4.

In general, whenever the number c is not even, one of the c quantities supplied as input to the adder tree will remain unconsumed in the first stage. This quantity is referred to herein as the "first stage remainder"'. In the adder tree 100 of Figure 2A, the quantity A% is the first stage remainder.

[0053] It is not essential that the consumption of the first- stage remainder be deferred until the last stage. For example, Figure 2B illustrates an embodiment of an adder tree 200 where the first-stage remainder (quantity Ag) is consumed by an adder circuit 207 in the third stage, Li the first two stages, the adder tree 200 has a structure similar to the structure of the adder tree 100. The quantity Ag and the output of adder circuit 106 are fed to adder circuit 207. The outputs of adder circuits 105 and 207 are fed to adder circuit 208.

[0054] Moreover, it is not essential that the last quantity (Ag in the examples above) be the first- stage remainder. In general, any of the quantities Ao, Ai, A; .., A_{0 1} can be the first-stage remainder. For example, Figure 3 A illustrates an embodiment of an adder tree 300 where the quantity AQ is the first-stage remainder. In the first stage, each of adder circuits 301, 302, 303 and 304 receive a corresponding pair of the quantities Ai₃ Ai, A₃, ..., Ag. Adder circuit 305 of the second stage is supplied with quantity Ao and the output of adder circuit 301 from the first stage. The outputs of adder circuits 305 and 306 are supplied to adder circuit 307. The outputs of adder circuit 302 and 307 are fed to adder circuit 308.

[0055] Furthermore, when c is even, there need not be a first-stage remainder, i.e., all the quantities may be consumed in the first stage. For example, Figure 3B illustrates an embodiment of an adder tree 350 configured for the case m=31 and n=4. Because c=ceiling(m/n)=8, each of the quantities AQ, A_I, Az, A^, ..., A7 may be consumed in the first stage. Each of the adder circuits 351, 352, 353 and 354 receives a corresponding pair of the quantities Ao, Ai, A₂, Aj, ..., A7. Adder circuit 355 receives the outputs of adder circuits 351 and 352. Adder circuit 356 receives the outputs of adder circuits 353 and 354. Adder circuit 357 receives the outputs of adder circuits 355 and 356.

[0056] In some embodiments, an adder tree may include only two copies of the adder circuit V_n. For example, Figure 3C illustrates an embodiment of an adder tree 360 configured for the case rn=21 and n=8. Adder tree 360 includes adder circuits 36] and 362. The adder circuit 361 receives the 8 -bit quantities Ao and Ai. The adder circuit 362 receives the 8 -bit output of the adder circuit 361 and also receives the 5 -bit quantity A₂.

[0057] In some embodiments, an adder tree may include only one copy of the adder circuit V_n. For example, Figure 3D illustrates an embodiment of an adder tree configured for the case m=l ] and n=6, having only one adder circuit 370. Adder circuit 370 receives the quantities Ao and A₁.

[0058] In the case that m is a multiple of n, the quantity Ai is vacuous since (m-kn) equals zero. Thus, expressions (1) and (3) reduce to:

A < m > - A_k__λ < n > A_k_₂ < n > . . . A₁ < n > A₀ < n > , (5)

A mod(T - 1) = (A-i + A_k_₂ + , , . + A₁ + A₀) mod(2^B - 1) , (6) i.e., the vacuous quantity Ai is simply omitted. For example, Figure 4 illustrates an embodiment of an adder tree 400 configured for the case m=15 and n=3. Adder circuit 401 receives quantities Ao and Ai. Adder circuit 402 receives the quantities A₃ and A₄. Adder circuit receives the output of adder circuit 401 and the quantity A₂. Adder circuit 404 receives the outputs of adder circuits 402 and 403. [0059] A wide variety of embodiments of adder trees consistent with expression (3), or with expression (6) in the case where m is a multiple of n, will be apparent to the reader in light of the various examples given herein.

[0060] As defined above, the adder circuit V_n implements the computation (X+Y) mod(2^Η-l) on two n bit operands X and Y to produce an n-bit output Z. The adder circuit V_n may be realized as illustrated in Figure 5. The adder circuit V_n may include two n-bit adders 501 and 502. Each n-bit adder is configured to operate on two n-bit operands to produce an n-bit output, using wrap as the overflow operation. The n-bit operands X and Y are supplied to the adder 501. The output W<n> of the adder 501 may be supplied to the adder 502. Furthermore, the carryout bit from the adder 501 may be supplied to the adder 502. The output R<n> from the adder 502 is supplied to a circuit 503 for selectively mapping the state (2ⁿ-l) to zero and for passing all other states of the output R. Thus, the adder circuit V_n reports the result (X ^l Y) mod (2ⁿ-l). The circuit 503 may include a comparison unit 504 and a multiplexer 505. The comparison unit 504 may determine if the output R equals 2ⁿ-l and asserts the control signal CNTL if so. The control signal CNTL may be coupled to the select input of the multiplexer 505. If the control signal is asserted, the multiplexer 505 selects the "1" input which is tied to zero. If the control signal is not asserted, the multiplexer 505 selects the "0" input which is coupled to the output R of the adder 502. Thus, the circuit 503 passes all states of the output R except for the state R=2ⁿ-1; this exceptional state is mapped to zero. (The circuit 503 may be referred to herein as an exceptional-state mapping circuit or simply as a mapping circuit.) The output Z of the multiplexer 505 is the output of the adder circuit V_n.

[0061] Thus, the adder circuit V_n generates the output Z according to the relations: W < n > = (X t- Y) mod 2" (7) f W if X - Y < 2"

R < n > H (⁸)

[ (W -r l) if X ±Y > 2"

= (ψ -^ carry-out mod 2" (9) fo if R = 2" - I

Z < n > =\ ^J , (10)

[J? otherwise

[0062] In some embodiments, systems for computing A mod (2ⁿ-l) may be configured using copies of an adder circuit G_n as illustrated in Figure 6. Similar to the adder circuit V_n, the adder circuit G_r, includes two n-bit adders 601 and 602. However, in contrast to the adder circuit V_n, the adder circuit G_n does not include an exceptional-state mapping circuit such as circuit 503. The adder 601 receives the n-bit operands X and Y and produces an n-bit output W. The output W and the carryout signal from the adder 601 are provided to the adder 602. The adder 602 generates the output Z. Thus, the adder circuit G_n generates the output Z according to the relations: W < n > = (X T Y) mod 2" (11)

7. < n > - \ ^{W if K + Y < r} (12)

[ (W + \) if X + Y ≥ 2"

= (If - carryout mod 2" . (13)

[0063] Figure 7 illustrates one embodiment of a system 690 for computing A mod (2ⁿ-l ) including an adder tree 700. Adder tree 700 is configured using copies of adder circuit G_n instead of copies of adder circuit V_n. The adder tree 700 is configured for the case m=35 and n=4. Each of the adder circuits 701. 702, 703 and 704 receive a corresponding pair of the quantities Ao, A₁, A₂ ..., A₇. Adder circuit 705 is provided with the outputs of adder circuits 701 and 702. Adder circuit 706 is provided with the outputs of adder circuits 703 and 704. Adder circuit 707 is provided with the output of adder circuit 706 and with the quantity Ag- Adder circuit 708 is provided with the outputs of adder circuits 705 and 707.

[0064] Note that the system 690 includes an exceptional -state mapping circuit 709 coupled to the output of adder tree 700 (i.e., the output of adder circuit 708) in order to complete the computation of A mod (2ⁿ-l). The mapping circuit 709 includes a control circuit 710 and a multiplexer 71 1. The adder circuit output Z is supplied to a control circuit 710 and to multiplexer 71 1. The control circuit 710 determines if the output Z equals (2⁴-l) and drives the control signal CNTL accordingly. Thus, the multiplexer 711 selects the value zero when Z=2⁴-l and selects the value Z otherwise. The output of the multiplexer 711 is the output of the system 690 and is equal to A mod (15).

[0065] The reader will observe that the structure of adder tree 700 is similar to the structure of adder tree 200 depicted in Figure 2B. To arrive at adder tree 700, one can imagine replacing the adder circuits V₄ of adder tree 200 with adder circuits G₄. However, to complete the computation of A mod (2ⁿ-l), system 690 includes the mapping circuit 709 coupled to the output of the adder tree 700. Recall that the difference between the adder circuit V₄ and the adder circuit G₄ is the presence of a mapping circuit. Thus, system 690 performs the mapping function once at the output, whereas adder tree 200 performs the mapping function in each adder circuit. Because, system 690 does not duplicate the mapping circuit, it occupies less silicon area and consumes less power than adder tree 200.

[0066] The reader should note that any system embodiment of the kind described above in connection with Figures 2A-B, 3A-D and 4, i.e., having an adder tree T composed of copies of adder circuit V_n, may be alternatively realized by a structurally analogous adder tree T' and a mapping circuit coupled to the output of the adder tree T¹. where adder tree T' has the same structure of connections between adder circuit copies, but employs copies of adder circuit G_n instead of copies of adder circuit V_n. [0067] In some embodiments, a computer system may be configured to implement the computation of A mod (2ⁿ-l) in software. For example, a computer program may include instructions implementing the operations suggested by the following pseudo code: X=O;

For (1=0, Kceil(m/n), Ii-+) { p = min ( n*(m)-l , (m-l) );

Section=A[ p : n*I ];

X=Section+X;

If (X>2ⁿ-1) X=(X 1) mod (2ⁿ);

}

If(X==2ⁿ-l) X=O.

[0068] The notation "ceil(x)" denotes the ceiling function operating on the operand x. The notation "A[v:u]" represents the extraction Of (V-U⁺I) consecutive bits from the quantity A, i.e., the bits starting at the u* bit position and ending at the v^th bit position of A. The 0^th bit position designates the least significant bit of A. The final value of the variable X represents A mod (2ⁿ-l).

[0069] In one set of embodiments, a system for computing Λ mod (2ⁿ-l), where A is an m-bit quantity, where rn is an integer greater than or equal to two, where n is a positive integer less than or equal to m, may include a plurality 801 of adder circuits AC as suggested in Figure 8. Each of the adder circuits AC may be configured to operate on two n-bit operands in order to produce an n-bit output. The plurality of adder circuits may be coupled to form a tree structure. The quantity A is partitioned into a plurality of sections, where each of the sections includes up to n consecutive bits of the quantity A. Each of the sections is supplied to exactly one of the adder circuits in order to determine one of the two n-bit input operands of that adder circuit. Note, however, this does not imply that each of the adder circuits necessarily receives exactly one section. For example, in the embodiment of Figure 7, observe that adder circuit 701 receives two sections, adder circuit 707 receives exactly one section, and adder circuit 708 receives zero sections.

[0070] Each of the adder circuits AC may include a first n-bit adder 601 and a second n-bit adder 602, e.g., as suggested in Figure 6. The first n-bit adder may be configured to operate on the two n-bit operands in order to produce an intermediate n-bit result W. The second n-bit adder may be configured to operate on the intermediate n-bit result W and on a carryout signal from the first n-bit adder in order to produce the n- bit output Z.

[0071] The output of the adder circuit 802 corresponding to a root of the tree structure may be used in a wide variety of ways. For example, output of the adder circuit 802 may be used to perform data interleaving or deinterleaving. (See the more detailed description of interleaving/deinterleaving given below in connection with Figure

1OA.) As another example, the output of the adder circuit 802 may be used to perform encryption υr decryption of data.

[0072] In some embodiments, the system may also include a mapping circuit 805.

The mapping circuit 805 may be coupled to receive the output from an adder circuit

802 of the tree structure 801. The adder circuit 802 may correspond to a root of the tree structure 801 , The mapping circuit 805 may be configured to operate on the output of adder circuit 802 in order to map a state 2ⁿ-l to zero and to pass all other states of the adder circuit output Thus, the output of the mapping circuit 805 may equal the value A mod (2ⁿ-l).

[0073] The value A mod (2ⁿ-l ) may be used in a variety of ways. As suggested above, the value A mod (2ⁿ-l) may be used for perform data interleaving or deinterleaving. Alternatively, the value A mod (2ⁿ-l) may be used to perform data encryption or decryption.

[0074] Data flows through the tree structure from the section inputs towards the root adder circuit 802.

[0075] Various embodiments of the mapping circuit 805 are contemplated. In one embodiment, the mapping circuit may include a comparison unit and a multiplexer, e.g., as suggested by circuit 709 of Figure 7. The comparison unit 710 may be configured to determine if the output of the adder circuit 802 is equal to 2ⁿ-l and to assert a control signal CNTL in response determining that the adder circuit output is equal to 2ⁿ-l. The multiplexer 711 may be configured to select between the value zero and the adder circuit output based on the control signal.

[0076] If m is a multiple of n, it may be advantageous for each of the sections to be of length n bits. If m is not a multiple of n, it may be desirable to partition the quantity

A into k=floor(m/n) sections of length n and one section of length (m-kn). For example, the section containing the most significant bits of A may be the section of length (m-kn).

[0077] In some embodiments, the number of sections into which the quantity A is partitioned equals c=ceilingfm/n). The number of adder circuits in the tree structure may equal (c-1).

[0078] In some embodiments, the tree structure has a number of levels equal to the ceiling of the base-2 logarithm of the ceiling of m/n.

[0079] In some embodiments, n is a positive integer in the range [2,32].

[0080] In some embodiments, n is a power of two. For example, n rnay equal 2, 4, 8,

16, 32, etc.

[0081] In one set of embodiments, a system for computing A mod (2ⁿ-l), where A is an m-bit quantity, where m is an integer greater than or equal to two, where n is a positive integer less than or equal to m, may include an adder circuit, e.g., as suggested in Figure 9. The adder circuit 900 may be configured to operate on two n- bit inputs (X and Y) and to produce an n-bit output (Z). The output Z of the adder circuit may be coupled to a first input (Y) of the two inputs.

[0082] The adder circuit 900 may include a first n-bit adder and a second n-bit adder, e.g., as suggested in Figure 5 or Figure 6. The first n-bit adder may be configured to operate on the two n-bit operands (X and Y) in order to produce an intermediate n-bit result W. The second n-bit adder may be configured to operate on the intermediate n- bit result W and on a carryout signal from the first n-bit adder in order to produce the n-bit output Z.

[0083] A plurality of sections of the quantity A may be sequentially presented to a second input (X) of the two inputs of adder circuit 900 in a plurality of cycles of the clock signal respectively. Each of the sections may include up to n consecutive bits of the quantity A.

[0084] In some embodiments, the number of sections into which the quantity A is partitioned equals c=ceiling(m/n). Thus, the modulo operation may require c cycles to complete,

[0085] In one alternative embodiment, two sections may be presented to the adder circuit 900 in the first cycle, i.e., one section to the X input and one to the Y input. In succeeding cycles, sections are presented to the X input while the Y input is reserved for feedback from the output Z. In this alternative embodiment, the modulo operation may be completed in (c-1) cycles.

[0086] The output of the adder circuit 900 after a last of the plurality of cycles may be used in a variety of ways. For example, the adder circuit output may be used to perform data interleaving or deinterleaving. Alternatively, the adder circuit output may be used as part of a data encryption operation or a decryption operation . [0087] In some embodiments, the system may also include an extraction circuit configured to receive the m-bit quantity A, to extract the plurality of sections of the quantity A, and to supply the plurality of sections to the second input (X) in successive clock cycles respectively. Various embodiments of the extraction circuit are contemplated. In one embodiment, the extraction circuit may include a multiplexer, a register and a shift unit, e.g., as suggested in Figure 1C. The multiplexer 51 may be configured to select between a first input port U and a second input port V, where the first input port U is coupled to receive the m-bit quantity A, where the second input port V is coupled to receive an output of the shift unit 53. The register 52 may be coupled to an output of the multiplexer. The shift unit may be coupled to an output of the register. The lowest n significant bits of the register output may be provided as output to the adder circuit 900.

[0088] The quantity A may be partitioned into sections, each having at most n bits, in a wide variety of ways. For example, if m is a multiple of n. it may be advantageous for each of the sections to be of length n bits. If m is not a multiple of n, it may be desirable to partition the quantity A into k=fioor(m/n) sections of length n and one section of length (m-kn).

[0089] In some embodiments, the system also includes a mapping circuit configured to receive the n-bit output from the adder circuit 900, to operate on the adder circuit output to map a state 2ⁿ-l to zero and to pass all other states of the adder circuit output. See for example, the mapping circuit 709 of Figure 7. The output of the mapping circuit after a last of the plurality of cycles is equal to A mod (2ⁿ-l). As suggested above, the value A mod (2¹M) may be used in a variety of ways. For example, the value A mod (2^a-l) may be used to perform data interleaving or deinterleaving. Alternatively, the value A mod (2ⁿ-l) may be used to perform data encryption or decryption.

[0090] In alternative embodiments, the adder circuit 900 may itself include a mapping circuit, e.g., as illustrated by the mapping circuit 503 in the adder circuit V_n of Figure

5. The mapping circuit may be configured to receive an n-bit result R generated by the second n-bit adder, to operate on the n-bit result R in order to obtain the n-bit output Z. The process of operating on the n-bit result may include mapping a state 2ⁿ-

1 to zero and passing all other states of the result R. Thus, for this set of alternative embodiments, the output of the adder circuit 900 is equal to A mod (2ⁿ-l).

[0091] In one set of embodiments, a method (e.g., a computer-implemented method) for computing A mod (2ⁿ-l). where A is an m-bit quantity, m is an integer greater than or equal to two, and n is a positive integer less than or equal to m, may involve the following actions, as illustrated in Figure JOA.

[0092] At 1010, the m-bit quantity A may be received (or generated by computation),

[0093] At 1012, a section of the quantity A may be extracted, where the section includes up to n consecutive bits of the quantity A.

[0094] At 1014, the section may be added to the value of a register, where the register is more than n bits in length.

[0095] At 1016, the register value may be incremented in response to a determination that the register value is greater than 2^-1 , where the increment operation is performed modulo 2ⁿ.

[0096] At 1018, a test may be performed to determine if all m bits of the quantity A have been consumed. If not, the method returns to 1012 for another repetition of the loop (including 1012, 1014 and 1016) on a next section of the quantity A. Thus, actions 1012, 1014 and 1016 may be repeated until the quantity A is exhausted.

[0097] If the test determines that all m bits of the quantity A have been consumed, the method proceeds with 1020.

[0098] At 1020, the register value may be set equal to zero if the register value equals

2ⁿ-l. After 1020, the register value equals A mod (2ⁿ-l),

[0099] The value A mod (2ⁿ-l) may be used in any of a wide variety of ways. In one embodiment, the value A mod (2°- J ) may be used to compute a read address. The read address may used to read data from a memory medium (e.g., a data buffer) as part of an interleaving (or deinterleaving) operation. For example, in order to interleave a block of N data symbols, the data symbols may be written into an input buffer in sequential order and then read out from the input buffer in an interleaved order. Iu one embodiment, the read addresses for the interleaved order may be computed according to the following algorithm:

For (A=O, A<N, A++) RdAddr=f(A), where f is a bijection (i.e., one-to-one function) on the set {0, 1, 2, ..., (N- 2), (N-l)}. The compulation of f(A) may involve the computation of A mod (2ⁿ-l). (See, e.g., section 3.1.3.1.8.1.1 of the following standard: "Physical Layer Standard for cdma2000 Spread Spectrum Systems", 3GPP2 C.S0002-D, Version 1.0, February 13, 2004.) The interleaved block of data may be transmitted through a channel. A receiver may then receive the interleaved block of data (possibly corrupted with noise) from the channel and perform a deinterleaving operation on the received data. The deinterleaving operation may similarly involve repeated computation of A mod (2ⁿ- 1) for different values of A.

[00100] Thus, the operations indicated in the method embodiment of Figure 1OA may be performed for each value in a sequence {AjJ of m-bit values in order to generate read addresses for a data interleaving (or deinterleaving) operation. [00101] In another embodiment, the value A mod (2ⁿ-l) may be used as part of a data encryption (or decryption) operation on a block of data. Methods for performing encryption (or decryption) using the value A mod (2ⁿ-l) are known in the field of encryption. A transmitter may transmit the encrypted data block through a channel (or store the encrypted data on a storage medium). A receiver may then receive the encrypted data block, possibly corrupted by noise, from the channel (or from the storage medium) and apply a decryption operation on the received block. The decryption operation may similarly involve the computation of A mod (2"-I). Note that the value (or values) of A used in the encryption operation is (are) not necessarily the same as the value (or values) of A used in the decryption operation. [00102] The quantity A may be partitioned into sections, each having at most n bits, in a wide variety of ways. For example, if m is a multiple of n, it may be advantageous for each of the sections to be of length n bits. Tf m is not a multiple of n, it may be desirable to partition the quantity A into k=floor(m/n) sections of length n and one section of length (m-kn).

[00103] In some embodiments, n is a positive integer in the range [2,32].

[00104] In some embodiments, n is a power of two. For example, n may equal 2, 4,

8, 16, 32, 64, 128, etc.

[00105] In various embodiments, the method may be enacted by a processor in response to the execution of program instructions stored in a memory. Tn one embodiment, the processor and memory are incorporated in a mobile phone.

[00106] In yet another set of embodiments, a method for computing A mod (2ⁿ-l), where A is an m-bit quantity, where m is an integer greater than or equal to two, where n is a positive integer less than or equal to m. may involve the following actions, as illustrated in Figure 1OB.

[00107] As illustrated at 1050, a number of addition operations may be performed in a sequence of stages. Each of the stages may include performing a corresponding subset of the number of addition operations in a parallel fashion. The subset of addition operations of each stage may receive corresponding input data and generate corresponding output data. The input data of each stage, except for a first of the stages, may include at least a portion of the output data of a previous one of the stages. (See Figures 2A-B, 3A-C, 4 and 7 for various examples of how the input data of a given stage may be supplied from one or more previous stages.)

[00108] The input data of the first stage may include a plurality of sections of the quantity A. Each of the sections may include at most n consecutive bits of the quantity A. (If a section is n bits long, the section may be directly provided as an input operand to one of the first stage addition operations. If a section is less than n bits long, the section may be padded with zeros in order to form an input operand.)

[00109] Each addition operation of said number of addition operations may include performing a first n-bit addition and a second n-bit addition. The first n-bit addition operates on two portions of the input data (of the stage to which the addition operation belongs). The second n-bit addition operates on an intermediate result and a carryout produced by the first n-bit addition. [00110] As illustrated at ] 055, either the value zero or the output data from a last of the stages is selected depending on a comparison of the value (2ⁿ-l) and the output data from the last stage. The selected value equals A mod (2ⁿ-] ).

[00111] In some embodiments, the last stage includes only one addition operation, and thus, the output data of the last stage comprises the output operand of that one addition operation.

[00112] In some embodiments, the method may include additional actions after performing actions 1050 and 1055, e.g., as illustrated in Figure H)C.

[00113] At 1057, a read address may be generated using the selected value.

[00114] At 1059, a data symbol may be read (i.e., accessed) from a data buffer using the read address.

[00115] Furthermore, in one embodiment, the m-bit quantity A may be varied through a range of values, and actions 1050 through 1059 may be performed for each value of the m-bit quantity A (in the range of values) in order to implement an interleaving operation (or a deinterleaving operation) on data symbols stored in the data buffer.

[00116] In alternative embodiments, the actions 1050 and 1055 may be performed as part of an encryption operation or a decryption operation on a block of data.

[00117] Figure 1 1 is a block diagram representing one set of embodiments of a computer system 1082. The computer system 1082 may include at least one cental processing unit CPU 1160 (i.e., processor) which is coupled to a host bus 1162. The

CPU 1160 may be any of various types, including, but not limited to, an x86 processor, a PowerPC processor, a CPU from the SPARC family of RISC processors, as well as others. A memory medium, typically including semiconductor RAM, and referred to herein as main memory 1166, may be coupled to the host bus 1162 by means of memory controller 1 164. The main memory 1166 may store programs operable to implement any or all or any portion of the various method embodiments described herein. The main memory may also store operating system software, as well as other software for operation of the computer system.

[00118] The host bus 1162 may couple to an expansion or input/output bus 1170 through a bus controller 1168 or bus bridge logic. In some embodiments, the expansion bus 1 170 may include slots for various devices such as a video card 1180, a hard drive 1182, storage devices 1190 (such as a CD-ROM drive, a tape drive, a floppy drive, etc.) and a network interface 1122. The video card 1 ] 80 may couple to a display device such as a monitor, a projector, or a head mounted display. The network interface 1122 (e.g., an Ethernet device) may be used to communicate with other computers through a network.

[00119] The computer system 1082 may also include one or more FQ devices 1 192 such as a mouse, a keyboard, one or more microphones, and one or more speakers, a touch sensitive pad, etc.

[00120] Embodiments of computer system 1082 targeted for use as a server computer may be more richly endowed with processor capacity (e.g., having multiple processors), memory capacity and network access bandwidth than embodiments targeted for use as a client computer. The client computer may include the mouse, keyboard, speakers and video card (or graphics accelerator), whereas a server computer does not necessarily include these items.

[00121] Various embodiments are described above for computing A mod (2ⁿ-l) in a sequential fashion using a single adder circuit or in a parallel fashion using an adder tree. The present invention contemplates combinations of these embodiments where the value A mod (2^Λ-1) is computed partially in a sequential fashion and partially in a parallel fashion. For example, if the number c of sections of the quantity A is greater llian number ri_f of inputs to an adder tree, the c sections may be divided in groups, e.g.. groups of size at most (ni-1). The groups may be supplied to the adder tree in successive cycles. The output of the adder tree may be coupled to one of the nr adder tree inputs. The remaining (n[- 1 ) inputs may be configured to recei ve the (ni- 1 ) sections of each group. [00122] Any of various logic implementations may be used in the adder circuits and/or the tree structures of the embodiments described above.

[00123] Any of the various method embodiments disclosed herein (or any combinations thereof or portions thereof) may be implemented in terms of program instructions. The program instructions may be stored in (or on) any of various memory media. A memory medium is a medium configured for the storage of information. Examples of memory media include various kinds of magnetic media (e.g., magnetic tape or magnetic disk); various kinds of optical media (e.g., CD- ROM); various kinds of semiconductor RAM and ROM; various media based on the storage of electrical charge or other physical quantities; etc.

[00124] Furthermore, various embodiments of a system including a memory and a processor are contemplated, where the memory is configured to store program instructions and the processor is configured to read and execute the program instructions from the memory. In various embodiments, the program instructions encode corresponding ones of the method embodiments described herein (or combinations thereof or portions thereof).

[00125] Various embodiments may further include receiving, sending or storing program instructions and/or data implemented in accordance with the foregoing description upon a computer-accessible medium. Generally speaking, a computer- accessible medium may include storage media or memory media such as magnetic or optical media, e.g., disk or CD-ROM, volatile or non-volatile media such as RAM (e.g. SDRAM, DDR SDRAM, RDRAM, SRAM, etc.), ROM, etc. as well as transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as network and/or a wireless link. [00126] The various methods as illustrated in the Figures and descπbed herein represent exemplary embodiments of methods. The methods may be implemented in software, hardware, or a combination thereof. The order of method actions may be changed, and various actions may be added, reordered, combined, omitted, modified, etc.

[00127] Various modifications and changes may be made as would be obvious to a person skilled in the art having the benefit of this disclosure. It is intended that the invention embrace all such modifications and changes and, accordingly, the above description to be regarded in an illustrative rather than a restrictive sense.

Claims

L A system for computing A mod (2ⁿ-l), wherein A is an m-bit quantity, wherein m is an integer greater than or equal to two, wherein n is a positive integer less than or equal to m, the system comprising: a plurality of adder circuits, wherein each of the adder circuits is configured to operate on two n-bit operands in order to produce an n-bit output, wherein the plurality of adder circuits are coupled to form a tree structure, wherein the quantity A is partitioned into a plurality of sections, wherein each of the sections includes up to n consecutive bits of the quantity A. wherein each of the sections is supplied to exactly one of the adder circuits in order to determine one of the two n-bit operands of that adder circuit, wherein each of the adder circuits includes: a first n-bit adder configured to operate on the two n-bit operands in order to produce an intermediate n-bit result; and a second n-bit adder configured, to operate on the intermediate n-bit result and on a carryout signal from the first n-bit adder in order to produce the n-bit output.

2. The system of claim 1 further comprising: a mapping circuit configured to receive the output from a first of the adder circuits, wherein the first adder circuit corresponds to a root of the tree structure, wherein the mapping circuit is configured to operate on the first adder output to map a state 2ⁿ- 1 to zero and to pass all other states of the first adder output.

3. The system of claim 2, wherein the mapping circuit includes a comparison unit and a multiplexer, wherein the comparison unit is configured to determine if said first adder output is equal to 2ⁿ-l and to assert a control signal in response to determining that the first adder output is equal to 2 '-1 , wherein the multiplexer is configured to select between the value zero and the first adder output based on the control signal.

4. The system of claim 1, wherein either: fa) m is a multiple of n, and each of the sections is n bits in length; or fb) m is not a multiple of n, each of the sections except for one is n bits in length, and the exceptional section has length equal to (m-zn) with z being a positive integer.

5. The system of claim 1, wherein the tree structure has a number of levels equal to the ceiling of the base-2 logarithm of the ceiling of m/n.

6. A system for computing A mod (2ⁿ-l), wherein A is an m-bit quantity, wherein m is an integer greater than or equal to two. wherein n is a positive integer less than or equal to m, the system comprising: an adder circuit, wherein the adder circuit is configured to operate on two n-bit inputs and to produce an n-bit output, wherein the output of the adder circuit is coupled to a first of the two inputs, wherein the adder circuit includes: a first n-bit adder configured to operate on the two n-bit operands in order to produce an intermediate n-bit result; and a second n-bit adder configured to operate on the intermediate n-bit result and on a carryout signal from the first n-bit adder in order to produce the n-bit output; wherein a plurality of sections of the quantity A are presented to a second, of the two inputs in a plurality of cycles respectively of a clock signal, wherein each of the sections includes up to n consecutive bits of the quantity A.

7. The system of claim 6 further comprising: an extraction circuit configured to receive the m-bit quantity A, to extract the plurality of sections of the quantity A, and to supply the plurality of sections to the second input of the adder circuit in successive clock cycles respectively.

8. The system of claim 7, wherein the extraction circuit includes a multiplexer, a register and a shift unit, wherein multiplexer is configured to select between a first input port and a second input port, wherein the first input port is coupled to receive the m-bit quantity A, wherein the second input port is coupled to receive an output of the shift unit, wherein the register to coupled to an output of the multiplexer, wherein the shift unit is coupled to an output of the register.

9. The system of claim 6, wherein cither:

(a) m is a multiple of n and each of the sections is n bits in length; or

(b) m is not a multiple of n, each of the sections except for one is n bits in length, and the exceptional section has length equal to (m-zn) with z being a positive integer.

10. The system of claim 6, wherein the number c of sections in said plurality of sections is equal to the ceiling of m/n.

11. The system of claim 10, wherein the system is configured to complete computation of A mod (2ⁿ- 1) in c of said cycles.

12. The system of claim 6 further comprising: a mapping circuit configured to receive the n-bit output from the adder circuit, to operate on the adder circuit output to map a state 2ⁿ-l to zero and to pass all other states of the adder circuit output.

13. The system of claim 6, wherein the adder circuit also includes: a mapping circuit configured to receive an n-bit result generated by the second n-bit adder, to operate on the n-bit result in order to obtain the n-bit output, wherein said operating includes mapping a state 2ⁿ-l to zero and passing all other states of the n-bit result.

wherein a plurality of sections of the quantity A are presented to a second of the two inputs in a plurality of cycles respectively of a clock signal, wherein each of the sections includes up to n consecutive bits of the quantity A.

14. A method for computing A mod (2ⁿ-l), wherein A is an m-bit quantity, wherein m is an integer greater than or equal to two, wherein n is a positive integer less than or equal to m, the method comprising:

(a) receiving the m-bit quantity A;

(b) extracting a section of the quantity A, wherein the section includes up to n consecutive bits of the quantity A;

(c) adding the section to a value of a register; (d) adding one to the register value if the register value is greater than 2M, wherein said adding of one is performed modulo 2";

(e) repeating (b), (c) and (d) until the quantity A is exhausted;

(f) setting the register value equal to zero if the register value equals 2ⁿ-l .

15. The method of claim 14 further comprising:

(g) generating a read address using the register value; and

(h) reading a data symbol from a data buffer using the read address.

16. The method of claim 15 further comprising: varying the no-bit quantity A through a range of values; and performing (a) through (h) for each value of the m-bit quantity A in order to implement an interleaving operation or a deinterleaving operation on data symbols stored in the data buffer.

17. The method of claim 14, wherein (a) through (f) are performed as part of an encryption operation or a decryption operation on a block of data.

18. The method of claim 14, wherein m is a multiple of n, wherein the section extracted in (b) is n bits in length.

19. A method for computing A mod (2ⁿ-l), wherein A is an m-bit quantity, wherein m is an integer greater than or equal to two, wherein n is a positive integer less than or equal to in, the method comprising: (a) performing a number of addition operations in a sequence of stages, wherein each of the stages includes performing a corresponding subset of the number of addition operations in a parallel fashion, wherein the subset of addition operations of each stage receives corresponding input data and generates corresponding output data, wherein the input data of each stage, except for a first of the stages, comprises at least a portion of the output data of a previous one of the stages, wherein the input data of the first stage includes a plurality of sections of the quantity A, wherein each of the sections includes at most n consecutive bits of the quantity A, wherein each of said number of addition operations includes performing a first n-bit addition and a second n-bit addition, wherein the second n-bit addition operates on an intermediate result and a carryout produced by the first n-bit addition;

(b) selecting either the value zero or the output data from a last of the stages depending on a comparison of the value (2ⁿ-l) and said output data from the last stage, wherein the selected value equals A mod (2ⁿ-l).

20. The method of claim 19, wherein the input data of one of the stages, other than the first stage, includes an additional section of the quantity A, wherein said additional section is not included in said plurality of sections.

21. The method of claim 19 further comprising: distributing the plurality of sections of the quantity A to the subset of addition operations of the first stage.

22. The method of claim 19 further comprising:

(c) generating a read address using the selected value; and

(d) reading a data symbol from a data buffer using the read address.

23. The method of claim 22 further comprising: varying the m-bit quantity A through a range of values; and performing (a) through (d) for each value of the m-bit quantity A in order to implement an interleaving operation or a deinterleaving operation on data symbols stored in the data buffer.

24. The method of claim 19, wherein (a) and (b) are performed as part of an encryption operation or a decryption operation on a block of data.