WO2008027694A3 - Stackable packages for three-dimensional packaging of semiconductor dice - Google Patents

Stackable packages for three-dimensional packaging of semiconductor dice Download PDF

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Publication number
WO2008027694A3
WO2008027694A3 PCT/US2007/075191 US2007075191W WO2008027694A3 WO 2008027694 A3 WO2008027694 A3 WO 2008027694A3 US 2007075191 W US2007075191 W US 2007075191W WO 2008027694 A3 WO2008027694 A3 WO 2008027694A3
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WO
WIPO (PCT)
Prior art keywords
strip
substrate
sidewall
integrated circuit
circuit die
Prior art date
Application number
PCT/US2007/075191
Other languages
French (fr)
Other versions
WO2008027694A2 (en
Inventor
Ken M Lam
Original Assignee
Atmel Corp
Ken M Lam
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp, Ken M Lam filed Critical Atmel Corp
Priority to CN2007800320099A priority Critical patent/CN101512762B/en
Publication of WO2008027694A2 publication Critical patent/WO2008027694A2/en
Publication of WO2008027694A3 publication Critical patent/WO2008027694A3/en

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component (201A-201E) of a leadless three-dimensional stackable semiconductor package (300) having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die 209) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated (215) into individual package strip for leadless packages. Three-dimensional stacking (350) is achieved by a bonding area (301) on an uppermost portion of the sidewall (203). The sidewall of the strip is high enough to enclose an encapsulant (213) covering a later mounted integrated circuit die and associated bonding wires (211).
PCT/US2007/075191 2006-08-28 2007-08-03 Stackable packages for three-dimensional packaging of semiconductor dice WO2008027694A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2007800320099A CN101512762B (en) 2006-08-28 2007-08-03 Stackable packages for three-dimensional packaging of semiconductor dice

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/467,786 2006-08-28
US11/467,786 US7816769B2 (en) 2006-08-28 2006-08-28 Stackable packages for three-dimensional packaging of semiconductor dice

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WO2008027694A2 WO2008027694A2 (en) 2008-03-06
WO2008027694A3 true WO2008027694A3 (en) 2008-08-21

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CN (1) CN101512762B (en)
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WO2008027694A2 (en) 2008-03-06
US7816769B2 (en) 2010-10-19
US20080048308A1 (en) 2008-02-28
TW200818458A (en) 2008-04-16
CN101512762B (en) 2012-05-23
US8278150B2 (en) 2012-10-02
CN101512762A (en) 2009-08-19
US20110014747A1 (en) 2011-01-20

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