WO2008030641A3 - Integrated circuit with graduated on-die termination - Google Patents

Integrated circuit with graduated on-die termination Download PDF

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Publication number
WO2008030641A3
WO2008030641A3 PCT/US2007/069471 US2007069471W WO2008030641A3 WO 2008030641 A3 WO2008030641 A3 WO 2008030641A3 US 2007069471 W US2007069471 W US 2007069471W WO 2008030641 A3 WO2008030641 A3 WO 2008030641A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
graduated
die termination
termination
data signal
Prior art date
Application number
PCT/US2007/069471
Other languages
French (fr)
Other versions
WO2008030641A2 (en
Inventor
Kyung Suk Oh
Original Assignee
Rambus Inc
Shaeffer Ian P
Kyung Suk Oh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc, Shaeffer Ian P, Kyung Suk Oh filed Critical Rambus Inc
Priority to EP07853485A priority Critical patent/EP1999602B1/en
Priority to JP2009513379A priority patent/JP5113159B2/en
Priority to DE202007018730U priority patent/DE202007018730U1/en
Priority to EP14195760.5A priority patent/EP2860641B1/en
Priority to CN2007800201333A priority patent/CN101460936B/en
Priority to EP20186614.2A priority patent/EP3761184B1/en
Priority to EP23175747.7A priority patent/EP4235446A3/en
Publication of WO2008030641A2 publication Critical patent/WO2008030641A2/en
Publication of WO2008030641A3 publication Critical patent/WO2008030641A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0605—Improving or facilitating administration, e.g. storage management by facilitating the interaction with a user or administrator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits

Abstract

An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.
PCT/US2007/069471 2006-06-02 2007-05-22 Integrated circuit with graduated on-die termination WO2008030641A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP07853485A EP1999602B1 (en) 2006-06-02 2007-05-22 Integrated circuit with graduated on-die termination
JP2009513379A JP5113159B2 (en) 2006-06-02 2007-05-22 Integrated circuit with gradual on-die termination
DE202007018730U DE202007018730U1 (en) 2006-06-02 2007-05-22 Inegrated circuit with graduated termination on the chip
EP14195760.5A EP2860641B1 (en) 2006-06-02 2007-05-22 Integrated circuit with graduated on-die termination
CN2007800201333A CN101460936B (en) 2006-06-02 2007-05-22 Integrated circuit with graduated on-die termination
EP20186614.2A EP3761184B1 (en) 2006-06-02 2007-05-22 Integrated circuit with graduated on-die termination
EP23175747.7A EP4235446A3 (en) 2006-06-02 2007-05-22 Integrated circuit with graduated on-die termination

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/422,022 2006-06-02
US11/422,022 US7486104B2 (en) 2006-06-02 2006-06-02 Integrated circuit with graduated on-die termination

Publications (2)

Publication Number Publication Date
WO2008030641A2 WO2008030641A2 (en) 2008-03-13
WO2008030641A3 true WO2008030641A3 (en) 2008-05-29

Family

ID=38789378

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/069471 WO2008030641A2 (en) 2006-06-02 2007-05-22 Integrated circuit with graduated on-die termination

Country Status (6)

Country Link
US (25) US7486104B2 (en)
EP (7) EP2133799B1 (en)
JP (1) JP5113159B2 (en)
CN (2) CN102279833B (en)
DE (1) DE202007018730U1 (en)
WO (1) WO2008030641A2 (en)

Families Citing this family (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8335894B1 (en) * 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
DE112006002300B4 (en) 2005-09-02 2013-12-19 Google, Inc. Device for stacking DRAMs
US7439760B2 (en) 2005-12-19 2008-10-21 Rambus Inc. Configurable on-die termination
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7486104B2 (en) * 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
KR100844932B1 (en) * 2006-09-27 2008-07-10 주식회사 하이닉스반도체 Semiconductor memory device with on-die-termination circuit
JP5019573B2 (en) * 2006-10-18 2012-09-05 キヤノン株式会社 Memory control circuit, memory system, memory control method thereof, and integrated circuit
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US7864604B2 (en) * 2007-09-27 2011-01-04 Intel Corporation Multiple address outputs for programming the memory register set differently for different DRAM devices
JP5603535B2 (en) * 2007-11-29 2014-10-08 ピーエスフォー ルクスコ エスエイアールエル Signal transmission circuit, characteristic adjustment method thereof, memory module, and circuit board manufacturing method
US8516185B2 (en) * 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8041865B2 (en) * 2008-08-04 2011-10-18 Qimonda Ag Bus termination system and method
KR100974225B1 (en) * 2008-12-23 2010-08-06 주식회사 하이닉스반도체 Impedance calibration period setting circuit and semiconductor integrated circuit
KR100980425B1 (en) * 2008-12-30 2010-09-07 주식회사 하이닉스반도체 Termination Control Circuit for Global Input/Output Line
JP2010219751A (en) 2009-03-16 2010-09-30 Elpida Memory Inc Semiconductor device
US9608630B2 (en) * 2009-05-06 2017-03-28 Micron Technology, Inc. Reference voltage circuits and on-die termination circuits, methods for updating the same, and methods for tracking supply, temperature, and/or process variation
US7843213B1 (en) * 2009-05-21 2010-11-30 Nanya Technology Corp. Signal termination scheme for high speed memory modules
WO2010144624A1 (en) * 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US7868651B1 (en) * 2009-12-08 2011-01-11 International Business Machines Corporation Off-die termination of memory module signal lines
KR101789077B1 (en) * 2010-02-23 2017-11-20 삼성전자주식회사 On-die termination circuit, data output buffer, semiconductor memory device, memory module, method of operating an on-die termination circuit, method of operating a data output buffer and method of training on-die termination
US8588012B2 (en) * 2010-06-17 2013-11-19 Rambus, Inc. Balanced on-die termination
US8688955B2 (en) * 2010-08-13 2014-04-01 Micron Technology, Inc. Line termination methods and apparatus
US8988102B2 (en) 2011-02-02 2015-03-24 Rambus Inc. On-die termination
KR20130003551A (en) * 2011-06-30 2013-01-09 삼성전자주식회사 Semiconductor memory device, memory controller and memory system having on die termination and method for controlling on die termination thereof
JP5653856B2 (en) 2011-07-21 2015-01-14 ルネサスエレクトロニクス株式会社 Semiconductor device
CN103050147B (en) * 2011-10-13 2016-03-02 澜起科技（上海）有限公司 Terminating device system
WO2014015071A2 (en) * 2012-07-20 2014-01-23 Rambus Inc. Reducing unwanted reflections in source-terminated channels
US9286129B2 (en) * 2013-05-08 2016-03-15 International Business Machines Corporation Termination of requests in a distributed coprocessor system
US20150006826A1 (en) * 2013-06-28 2015-01-01 Yean Kee Yong Strap-based multiplexing scheme for memory control module
US9779039B2 (en) 2013-08-29 2017-10-03 Micron Technology, Inc. Impedance adjustment in a memory device
CN104063183A (en) * 2013-10-30 2014-09-24 苏州天鸣信息科技有限公司 Switching type storage device
US9292391B2 (en) * 2014-02-12 2016-03-22 Apple Inc. Interface calibration using configurable on-die terminations
TWI561077B (en) 2014-05-08 2016-12-01 Novatek Microelectronics Corp Video transmission system
US9780782B2 (en) 2014-07-23 2017-10-03 Intel Corporation On-die termination control without a dedicated pin in a multi-rank system
US9571098B2 (en) 2014-08-11 2017-02-14 Samsung Electronics Co., Ltd. Signal receiving circuits including termination resistance having adjustable resistance value, operating methods thereof, and storage devices therewith
US10255220B2 (en) 2015-03-30 2019-04-09 Rambus Inc. Dynamic termination scheme for memory communication
US10114788B2 (en) 2015-07-08 2018-10-30 International Business Machines Corporation Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus
US10241937B2 (en) 2015-07-08 2019-03-26 International Business Machines Corporation Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus
US10423545B2 (en) * 2015-07-08 2019-09-24 International Business Machines Corporation Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus
KR102275812B1 (en) 2015-09-04 2021-07-14 삼성전자주식회사 Semiconductor memory device for improving signal integrity issue in center pad type of stacked chip structure
US10141935B2 (en) 2015-09-25 2018-11-27 Intel Corporation Programmable on-die termination timing in a multi-rank system
KR20170064777A (en) 2015-12-02 2017-06-12 삼성전자주식회사 Memory device for performing calibration operation without ZQ pin
KR20170112289A (en) 2016-03-31 2017-10-12 삼성전자주식회사 Nonvolatile memory device, memory system including the same and method of operating nonvolatile memory device
RU2632956C1 (en) * 2016-05-06 2017-10-11 Владимир Глебович Венгерцев Device and method for disposal of mercury-containing wastes
EP4145447A1 (en) 2016-06-27 2023-03-08 Apple Inc. Memory system having combined high density, low bandwidth and low density, high bandwidth memories
KR102554496B1 (en) * 2016-07-14 2023-07-13 에스케이하이닉스 주식회사 Data Processing System including a plurality of memory modules
US10679722B2 (en) 2016-08-26 2020-06-09 Sandisk Technologies Llc Storage system with several integrated components and method for use therewith
JP6753746B2 (en) * 2016-09-15 2020-09-09 キオクシア株式会社 Semiconductor memory device
US20180246643A1 (en) * 2017-02-28 2018-08-30 Dell Products, Lp System and Method to Perform Runtime Saves on Dual Data Rate NVDIMMs
US20180322914A1 (en) * 2017-05-03 2018-11-08 Mediatek Inc. Multi-rank topology of memory module and associated control method
US10496584B2 (en) 2017-05-11 2019-12-03 Samsung Electronics Co., Ltd. Memory system for supporting internal DQ termination of data buffer
KR102553266B1 (en) 2017-11-03 2023-07-07 삼성전자 주식회사 Memory device including on-die-termination circuit
CN108682441B (en) * 2018-04-25 2021-04-30 深圳市国微电子有限公司 Reading and writing circuit and integrated circuit of static SRAM
US11276443B2 (en) * 2018-10-16 2022-03-15 Micron Technology, Inc. Offset cancellation
JP2020102286A (en) * 2018-12-21 2020-07-02 キオクシア株式会社 Semiconductor storage device
KR20200078994A (en) 2018-12-24 2020-07-02 에스케이하이닉스 주식회사 Semiconductor apparatus performing termination and semiconductor system including the semiconductor apparatus
KR20210057859A (en) 2019-11-12 2021-05-24 삼성전자주식회사 Memory device performinbg self-calibration by identifying location information and memory module including thereof
US10998904B1 (en) * 2019-11-15 2021-05-04 Xilinx, Inc. Programmable termination circuits for programmable devices
US11210429B2 (en) * 2020-03-10 2021-12-28 Micron Technology, Inc. Memory access gate
DE102020108101A1 (en) * 2020-03-24 2021-09-30 Pilz Gmbh & Co. Kg Device for storing data in a non-volatile memory
US11200190B2 (en) * 2020-04-21 2021-12-14 Innogrit Technologies Co., Ltd. Command based on-die termination for high-speed NAND interface
US20220043135A1 (en) * 2020-08-05 2022-02-10 Rockwell Automation Technologies, Inc. Automatic device ordering
KR20220126364A (en) * 2021-03-09 2022-09-16 에스케이하이닉스 주식회사 Computer System and Interface Circuit Therefor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424200B1 (en) * 2000-06-12 2002-07-23 Lsi Logic Corporation Termination impedance trimming circuit
US20030012046A1 (en) * 2001-07-13 2003-01-16 Samsung Electronics, Co., Ltd. Apparatus for controlling input termination of semiconductor memory device and method for the same
US20030039151A1 (en) * 2001-08-24 2003-02-27 Yoshinori Matsui Memory device and memory system
US20050226080A1 (en) * 2004-04-13 2005-10-13 Samsung Electronics Co., Ltd. Memory module and impedance calibration method of semiconductor memory device
DE102005036528A1 (en) * 2005-07-29 2007-02-01 Infineon Technologies Ag Memory module for use in memory system, has control circuit connected with scheduling circuit to adjust resistance value depending on received control command signal and to schedule connection

Family Cites Families (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131942A (en) 1977-01-10 1978-12-26 Xerox Corporation Non-volatile storage module for a controller
GB2254227B (en) 1990-12-20 1995-08-16 Murata Manufacturing Co Bus terminating circuit
US5272396B2 (en) * 1991-09-05 1996-11-26 Unitrode Corp Controllable bus terminator with voltage regulation
JPH0784863A (en) 1993-09-20 1995-03-31 Hitachi Ltd Information processor and semiconductor storage device suitable to the same
US5467455A (en) 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
US5570037A (en) * 1994-07-20 1996-10-29 Methode Electronics Switchable differential terminator
US5541534A (en) 1995-02-13 1996-07-30 International Business Machines Corporation Mixed voltage interface converter
US5578940A (en) 1995-04-04 1996-11-26 Rambus, Inc. Modular bus with single or double parallel termination
US5546016A (en) 1995-07-03 1996-08-13 Intel Corporation MOS termination for low power signaling
US5666078A (en) 1996-02-07 1997-09-09 International Business Machines Corporation Programmable impedance output driver
US5726583A (en) 1996-07-19 1998-03-10 Kaplinsky; Cecil H. Programmable dynamic line-termination circuit
JP3439096B2 (en) * 1996-11-18 2003-08-25 株式会社日立製作所 Terminating resistance controlled bus system
US5995894A (en) 1997-05-27 1999-11-30 Case Corporation System for analyzing spatially-variable harvest data by pass
US5982191A (en) * 1997-06-25 1999-11-09 Sun Microsystems, Inc. Broadly distributed termination for buses using switched terminator logic
US6060907A (en) 1997-06-25 2000-05-09 Sun Microsystems, Inc. Impedance control circuit
US6232792B1 (en) * 1997-06-25 2001-05-15 Sun Microsystems, Inc. Terminating transmission lines using on-chip terminator circuitry
US6323672B1 (en) 1997-06-25 2001-11-27 Sun Microsystems, Inc. Apparatus for reducing reflections when using dynamic termination logic signaling
US6087847A (en) * 1997-07-29 2000-07-11 Intel Corporation Impedance control circuit
JPH11154852A (en) * 1997-11-20 1999-06-08 Mitsubishi Electric Corp Reflection suppressing device
US6198307B1 (en) 1998-10-26 2001-03-06 Rambus Inc. Output driver circuit with well-controlled output impedance
US6157206A (en) 1998-12-31 2000-12-05 Intel Corporation On-chip termination
US6069539A (en) * 1999-05-27 2000-05-30 Cisco Technology, Inc. VTT power distribution system
US6463543B1 (en) * 1999-08-03 2002-10-08 Btech, Inc. Serial bus communications system
US6308232B1 (en) 1999-09-01 2001-10-23 Rambus Inc. Electronically moveable terminator and method for using same in a memory system
US7572238B2 (en) * 1999-10-04 2009-08-11 Dermanew, Inc. Handheld sonic microdermabrasion porous applicator
US6560666B1 (en) * 1999-11-23 2003-05-06 Intel Corporation Hub link mechanism for impedance compensation update
US6356105B1 (en) 2000-06-28 2002-03-12 Intel Corporation Impedance control system for a center tapped termination bus
US6356106B1 (en) * 2000-09-12 2002-03-12 Micron Technology, Inc. Active termination in a multidrop memory system
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6675272B2 (en) * 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
DE10124176B4 (en) * 2001-05-17 2005-10-06 Infineon Technologies Ag Apparatus and method for reducing reflections in a memory bus system
US7102958B2 (en) * 2001-07-20 2006-09-05 Samsung Electronics Co., Ltd. Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods
KR100389928B1 (en) * 2001-07-20 2003-07-04 삼성전자주식회사 Semiconductor memory system for controlling active termination
US7102200B2 (en) * 2001-09-04 2006-09-05 Intel Corporation On-die termination resistor with analog compensation
EP1306849B1 (en) * 2001-10-19 2008-02-27 Samsung Electronics Co., Ltd. Devices and methods for controlling active termination resistors in a memory system
US6981089B2 (en) * 2001-12-31 2005-12-27 Intel Corporation Memory bus termination with memory unit having termination control
KR100454126B1 (en) * 2002-01-15 2004-10-26 삼성전자주식회사 Information processing system with separated clock line structure
US6683472B2 (en) * 2002-02-19 2004-01-27 Rambus Inc. Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time
US6639423B2 (en) 2002-03-12 2003-10-28 Intel Corporation Current mode driver with variable termination
JP2003283322A (en) * 2002-03-27 2003-10-03 Mitsubishi Electric Corp Interface circuit and semiconductor device
US6781405B2 (en) 2002-04-29 2004-08-24 Rambus Inc. Adaptive signal termination
US6894691B2 (en) 2002-05-01 2005-05-17 Dell Products L.P. Dynamic switching of parallel termination for power management with DDR memory
KR100422451B1 (en) * 2002-05-24 2004-03-11 삼성전자주식회사 method for controlling on-die termination and control circuit therefore
JP2004021916A (en) * 2002-06-20 2004-01-22 Renesas Technology Corp Data bus
US6965529B2 (en) 2002-06-21 2005-11-15 Intel Coproration Memory bus termination
KR100448901B1 (en) * 2002-08-23 2004-09-16 삼성전자주식회사 Layout for semiconductor integrated circuit having on-chip determination
KR100860523B1 (en) * 2002-10-11 2008-09-26 엘지디스플레이 주식회사 In plane switching mode liquid crystal display device and fabrication method thereof
JP3808026B2 (en) * 2002-10-23 2006-08-09 株式会社ルネサステクノロジ Semiconductor device
US7142461B2 (en) * 2002-11-20 2006-11-28 Micron Technology, Inc. Active termination control though on module register
KR100464437B1 (en) * 2002-11-20 2004-12-31 삼성전자주식회사 On-Die Termination circuit and method for reducing on-chip DC current and memory system including memory device having the same
US6842035B2 (en) 2002-12-31 2005-01-11 Intel Corporation Apparatus and method for bus signal termination compensation during detected quiet cycle
US6856169B2 (en) 2003-05-09 2005-02-15 Rambus, Inc. Method and apparatus for signal reception using ground termination and/or non-ground termination
KR100541045B1 (en) * 2003-05-13 2006-01-10 삼성전자주식회사 Dual bank system, memory for use in this system, and on die termination control method thereof
KR100583636B1 (en) 2003-08-19 2006-05-26 삼성전자주식회사 Device of controlling impedance of termination circuit and off-chip driver circuit using one reference resistor
US7042859B2 (en) * 2003-09-02 2006-05-09 Santera Systems, Inc. Methods and systems for performing call handover in a media gateway
US6924660B2 (en) 2003-09-08 2005-08-02 Rambus Inc. Calibration methods and circuits for optimized on-die termination
JP2005119471A (en) 2003-10-16 2005-05-12 Calsonic Kansei Corp Vehicular display device
US6980020B2 (en) 2003-12-19 2005-12-27 Rambus Inc. Calibration methods and circuits for optimized on-die termination
US7532537B2 (en) * 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
KR100539252B1 (en) * 2004-03-08 2005-12-27 삼성전자주식회사 Memory module capable of improving the integrity of signal transferred through data bus and command/address bus, and memory system including the same
KR100604843B1 (en) * 2004-03-26 2006-07-31 삼성전자주식회사 Memory module having on-die termination circuit and control method thereof
US20050228912A1 (en) * 2004-03-30 2005-10-13 Walker Clinton F Memory address bus termination control
US7516281B2 (en) 2004-05-25 2009-04-07 Micron Technology, Inc. On-die termination snooping for 2T applications in a memory system implementing non-self-terminating ODT schemes
US7173450B2 (en) 2004-06-01 2007-02-06 Hewlett-Packard Development Company, L.P. Bus controller
CN100584654C (en) * 2004-07-12 2010-01-27 天津大学 Purely electrical automobile host controller based on CAN bus and control method therefor
US7092312B2 (en) * 2004-08-03 2006-08-15 Micron Technology, Inc. Pre-emphasis for strobe signals in memory device
US7123047B2 (en) 2004-08-18 2006-10-17 Intel Corporation Dynamic on-die termination management
KR100555571B1 (en) * 2004-09-07 2006-03-03 삼성전자주식회사 Transmitter of semiconductor device
US7433992B2 (en) * 2004-11-18 2008-10-07 Intel Corporation Command controlling different operations in different chips
US7996590B2 (en) * 2004-12-30 2011-08-09 Samsung Electronics Co., Ltd. Semiconductor memory module and semiconductor memory system having termination resistor units
US8335115B2 (en) * 2004-12-30 2012-12-18 Samsung Electronics Co., Ltd. Semiconductor memory module and semiconductor memory system having termination resistor units
US7138823B2 (en) 2005-01-20 2006-11-21 Micron Technology, Inc. Apparatus and method for independent control of on-die termination for output buffers of a memory device
JP2005310153A (en) * 2005-04-19 2005-11-04 Elpida Memory Inc Memory device
CN101189682B (en) * 2005-05-30 2010-10-13 精工爱普生株式会社 Semiconductor memory device
US20060277355A1 (en) 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
TWI264881B (en) 2005-06-13 2006-10-21 Airoha Technology Inc Method and apparatus for RF signal demodulation
US7432731B2 (en) 2005-06-30 2008-10-07 Intel Corporation Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations
KR100640158B1 (en) 2005-09-27 2006-11-01 주식회사 하이닉스반도체 Semiconductor memory device with ability to mediate impedance of data output-driver
US7342411B2 (en) 2005-12-07 2008-03-11 Intel Corporation Dynamic on-die termination launch latency reduction
US7372293B2 (en) 2005-12-07 2008-05-13 Intel Corporation Polarity driven dynamic on-die termination
US7414426B2 (en) * 2005-12-07 2008-08-19 Intel Corporation Time multiplexed dynamic on-die termination
US7439760B2 (en) 2005-12-19 2008-10-21 Rambus Inc. Configurable on-die termination
US20070247185A1 (en) * 2006-03-30 2007-10-25 Hideo Oie Memory system with dynamic termination
US7486104B2 (en) * 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
JP5019573B2 (en) * 2006-10-18 2012-09-05 キヤノン株式会社 Memory control circuit, memory system, memory control method thereof, and integrated circuit
US8599631B2 (en) * 2006-12-21 2013-12-03 Rambus Inc. On-die termination of address and command signals
KR100943861B1 (en) 2008-06-12 2010-02-24 주식회사 하이닉스반도체 Impedance matched bi-directional multi drop bus system, memory system using the same and memory module
JP5346259B2 (en) * 2009-09-08 2013-11-20 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
KR20110050923A (en) * 2009-11-09 2011-05-17 삼성전자주식회사 Semiconductor memory device, semiconductor memory module and semicondoctor memory system comprising the same
US8531898B2 (en) * 2010-04-02 2013-09-10 Samsung Electronics Co., Ltd. On-die termination circuit, data output buffer and semiconductor memory device
US8588012B2 (en) * 2010-06-17 2013-11-19 Rambus, Inc. Balanced on-die termination
US8988102B2 (en) * 2011-02-02 2015-03-24 Rambus Inc. On-die termination
KR101858578B1 (en) * 2011-12-21 2018-05-18 에스케이하이닉스 주식회사 Semiconductor package including multiple chips and memory system including the same
KR102098243B1 (en) * 2013-07-19 2020-05-26 삼성전자주식회사 Integrated circuit and data inputting method
US9780782B2 (en) * 2014-07-23 2017-10-03 Intel Corporation On-die termination control without a dedicated pin in a multi-rank system
US10192599B2 (en) * 2016-12-08 2019-01-29 SK Hynix Inc. Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424200B1 (en) * 2000-06-12 2002-07-23 Lsi Logic Corporation Termination impedance trimming circuit
US20030012046A1 (en) * 2001-07-13 2003-01-16 Samsung Electronics, Co., Ltd. Apparatus for controlling input termination of semiconductor memory device and method for the same
US20030039151A1 (en) * 2001-08-24 2003-02-27 Yoshinori Matsui Memory device and memory system
US20050226080A1 (en) * 2004-04-13 2005-10-13 Samsung Electronics Co., Ltd. Memory module and impedance calibration method of semiconductor memory device
DE102005036528A1 (en) * 2005-07-29 2007-02-01 Infineon Technologies Ag Memory module for use in memory system, has control circuit connected with scheduling circuit to adjust resistance value depending on received control command signal and to schedule connection

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION: "DDR2 SDRAM Specification", January 2005, ELECTRONIC INDUSTRIES ALLIANCE, XP002473555 *

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