WO2008060733A3 - Bi-processor architecture for secure systems - Google Patents

Bi-processor architecture for secure systems Download PDF

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Publication number
WO2008060733A3
WO2008060733A3 PCT/US2007/075933 US2007075933W WO2008060733A3 WO 2008060733 A3 WO2008060733 A3 WO 2008060733A3 US 2007075933 W US2007075933 W US 2007075933W WO 2008060733 A3 WO2008060733 A3 WO 2008060733A3
Authority
WO
WIPO (PCT)
Prior art keywords
cpu
processor architecture
secure systems
sensitive information
systems
Prior art date
Application number
PCT/US2007/075933
Other languages
French (fr)
Other versions
WO2008060733A2 (en
Inventor
Majid Kaabouch
Cocquen Eric Le
Original Assignee
Atmel Corp
Majid Kaabouch
Cocquen Eric Le
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp, Majid Kaabouch, Cocquen Eric Le filed Critical Atmel Corp
Priority to CN2007800305614A priority Critical patent/CN101506815B/en
Priority to EP07868330.7A priority patent/EP2052344B1/en
Priority to KR1020097005441A priority patent/KR101460811B1/en
Publication of WO2008060733A2 publication Critical patent/WO2008060733A2/en
Publication of WO2008060733A3 publication Critical patent/WO2008060733A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/14—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms

Abstract

Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first CPU and the second CPU can communicate through a secure interface. The first CPU cannot access the sensitive information within the second CPU.
PCT/US2007/075933 2006-08-17 2007-08-14 Bi-processor architecture for secure systems WO2008060733A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800305614A CN101506815B (en) 2006-08-17 2007-08-14 Bi-processor architecture for secure systems
EP07868330.7A EP2052344B1 (en) 2006-08-17 2007-08-14 Bi-processor architecture for secure systems
KR1020097005441A KR101460811B1 (en) 2006-08-17 2007-08-14 Bi-processor architecture for secure systems

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US82273506P 2006-08-17 2006-08-17
US60/822,735 2006-08-17
US11/558,367 US7984301B2 (en) 2006-08-17 2006-11-09 Bi-processor architecture for secure systems
US11/558,367 2006-11-09

Publications (2)

Publication Number Publication Date
WO2008060733A2 WO2008060733A2 (en) 2008-05-22
WO2008060733A3 true WO2008060733A3 (en) 2008-08-14

Family

ID=39190070

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/075933 WO2008060733A2 (en) 2006-08-17 2007-08-14 Bi-processor architecture for secure systems

Country Status (6)

Country Link
US (1) US7984301B2 (en)
EP (1) EP2052344B1 (en)
KR (1) KR101460811B1 (en)
CN (1) CN101506815B (en)
TW (1) TWI431502B (en)
WO (1) WO2008060733A2 (en)

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Also Published As

Publication number Publication date
US7984301B2 (en) 2011-07-19
KR101460811B1 (en) 2014-11-11
WO2008060733A2 (en) 2008-05-22
CN101506815A (en) 2009-08-12
TWI431502B (en) 2014-03-21
EP2052344B1 (en) 2017-09-27
TW200817968A (en) 2008-04-16
US20080072051A1 (en) 2008-03-20
CN101506815B (en) 2012-05-09
KR20090041438A (en) 2009-04-28
EP2052344A2 (en) 2009-04-29

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