WO2008060816A2 - Stackable micropackages and stacked modules - Google Patents
Stackable micropackages and stacked modules Download PDFInfo
- Publication number
- WO2008060816A2 WO2008060816A2 PCT/US2007/081931 US2007081931W WO2008060816A2 WO 2008060816 A2 WO2008060816 A2 WO 2008060816A2 US 2007081931 W US2007081931 W US 2007081931W WO 2008060816 A2 WO2008060816 A2 WO 2008060816A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- die
- redistribution substrate
- pads
- redistribution
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the present invention relates to aggregating integrated circuits and, in particular, to stacks and stacking integrated circuits.
- a variety of techniques are used to stack integrated circuits into a module. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. Both leaded and BGA type packaged integrated circuits (ICs) have been stacked. Although BGA packaging has become widely adopted, leaded packages are still employed in large volumes in low cost applications such as, for example, flash memory, which, when packaged, is typically found in thin small outline packages otherwise known as TSOPs. [0004] Other technologies have been devised to stack bare die or flip-chip configured integrated circuits. In a typical example, flex circuitry upon which such integrated circuits have been affixed has been employed to supplant the role of encapsulating packaging.
- flex circuitry bearing bare or flip- chip die is folded over itself to yield a multi-level module in which the constituent die are disposed vertically one above the other with module contacts being provided along one or more surfaces of the flex circuitry.
- a substrate bears an integrated circuit die that is encapsulated by a seal material having a height less than protruding electrodes connected to pads on the redistribution substrate which are connected to the die.
- seal material having a height less than protruding electrodes connected to pads on the redistribution substrate which are connected to the die.
- Other previous systems have purportedly disposed flip-chip devices active face down on substrates that are connected one to another through conductive members as described in U.S. Pat. No. 6,781,241 to Nishimura et al.
- the present invention provides a system and method for stacked circuit modules and stackable assemblies that may be stacked to create a stacked circuit module.
- One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry.
- the die and redistribution substrate are bonded together and wire-bond connected.
- Two or more stackable assemblies are interconnected through frame members to create low profile, high density stacked circuit modules.
- Fig. 1 depicts an exemplar IC die as may be employed in embodiments.
- Fig. 2 depicts an exemplar redistribution substrate as may be employed in embodiments.
- Fig. 3 depicts a frame member that may be employed in embodiments of the present stacked module.
- Fig. 4 is an enlarged depiction of a pad and via construction in an exemplar frame member as seen along line A - A in Fig. 3.
- FIG. 5 is a perspective depiction of an exemplar stacked module in accordance with an embodiment.
- Fig. 6 is a cross-sectional depiction of an exemplar stacked IC module devised in accord with an embodiment as seen along line B - B of Fig. 5.
- FIG. 7 is an enlarged depiction of a portion of the cross-sectional view of a stacked module identified in Fig. 6 by "C".
- Fig. 8 depicts an enlarged cross-sectional view of an exemplar stacked IC module devised in accord with an embodiment as seen along line D - D of Fig. 5.
- FIG. 9 depicts an enlarged cross-sectional view of an exemplar stacked IC module devised in accord with an embodiment.
- Fig. 1 depicts an exemplar IC die 12 as may be employed in embodiments of a stacked module.
- IC die 12 has a first side 11 and second side (indicated by reference 9) and edge 8 proximal to which are found plural die pads 13.
- the present invention may be employed to advantage with die of a variety of functions and sizes, it is particularly advantageous for use with memory IC die including but not limited to flash memory.
- IC die may be aggregated in a vertical stacked module that provides high density and helps ameliorate the steep next-generation cost slope typically encountered when higher memory density demands are satisfied with higher cost next generation monolithic devices. Depicted die 12 shown in Fig.
- Fig. 2 depicts an exemplar redistribution substrate 20 as may be employed in embodiments. Although it can be devised from a variety of conductive substrates capable of bearing a network of conductive traces and connectors, substrate 20 is preferably a flexible circuit devised with a thin profile and has upper surface 21 and indicated lower surface 25 which those of skill will understand is present but not visible in the view of Fig. 2.
- substrate 20 exhibits connective sites 22 along edges 23 and 27 of substrate 20 which sites are, in a preferred embodiment, typically pads which are well known in the art in a variety of configurations.
- connective sites 22 are on each of sides 21 and 25 of substrate 20.
- the disclosed stackable assemblies can be interconnected through the respective connection sites 22 to form a stacked circuit module.
- Wire bond pads 24 are shown adjacent to edges 26 and 28 of surface 21 of substrate 20.
- a lower die 12B (as shown in later Figs.) is attached to lower surface 25 of substrate 20, it is preferably disposed so that it is emergent beyond one of the perimeter edges of substrate 20 to expose its own die pads 13 for wire bond connection to substrate 20. This allows the wire bonding operation to be done without repositioning of the substrate assembly. Typically, this will require rotation of lower die 12B 180 degrees relative to the orientation of upper die 12T. Die 12 and substrate 20 are, typically but not always, close to the same size so that the advantages provided by the use of stackable assemblies disclosed herein are not outweighed by the minor increase in size.
- Fig. 3 depicts a frame member 30 that may be employed in some embodiments of the present stacked module.
- frame member 30 exhibits frame pads 32 having vias 34 that provide connection between upper and lower frame pads along upper and lower sides 35 and 37 respectively of frame member 30.
- the distance between upper and lower sides 35 and 37 of frame member 30 is less than twice the thickness of IC die 12.
- Frame member 30 provides structure or stiffness for stacked module embodiments and is disposed at least in part between substrates 20 in a stacked module embodiment as will be shown in more detail.
- frame member 30 is preferably disposed along the row of connective sites 22 adjacent to selected sides of substrate 20 and thus provides connection and structure between stackable assemblies.
- Frame member 30 can be devised from a variety of materials such as, for example, circuit board material such as FR4 or other epoxy or fiber structural material appropriate for support of a network of conductive pad structures and vias. Frame member 30 can be devised in accordance with low profile objectives and those of skill will appreciate that die thickness is one of the determinants of minimum thickness for frame member 30.
- Fig. 4 is an enlarged depiction of a pad and via construction in an exemplar frame member 30 as seen along line A - A in Fig. 3.
- frame pads 32 can be formed on each of sides 35 and 37 of frame member 30 with a hole that is preferably plated to create via 34 that passes between the frame pad 32 on side 35 to the corresponding frame pad 32 on side 37.
- Fig. 5 is a perspective depiction of an exemplar stacked module 50 in accordance with an embodiment.
- die 12T is disposed on upper surface 21 of substrate 20 and wire-bonded to wire bond pads 24 along side 26 of substrate 20 through exemplar wire bonds 33. Shown emergent from beneath substrate 20, lower die 12B is also wire-bonded to wire bond pads 24 along upper surface 21 near edge 28 of substrate 20 as shown by the exemplar wire bonds 33.
- the depiction of Fig. 5 includes four (4) die 12 and two substrates 20 in a high density stacked circuit module 50 in accordance with an embodiment.
- Stacked module 50 is preferably encapsulated with any of the variety of encapsulants known in the industry. The encapsulant is represented by arcing dotted line E across module 50.
- FIG. 6 is a cross-sectional depiction of an exemplar stacked IC module
- stacked module 50 devised in accord with an embodiment as seen along line B - B of Fig. 5.
- application contact 60 provides the capability to connect stacked module 50 to an application environment.
- application contacts 60 can be configured in a variety of different dimensions and shapes to correspond to the constraints of the particular application where stacked module 50 is employed.
- the depicted example of a ball contact serving as application contact 60 should be understood to merely be an example and not limiting of the many different configurations available for application contact 60 such as, for example, pads.
- Fig. 7 is an enlarged depiction of a portion of the cross-sectional view of stacked module 50 identified in Fig. 6 by "C".
- frame member 30 is disposed (at least in part) between corresponding inner connective sites 22 of two different stackable assemblies 70 that are bonded together. If adhesives are used, a thermally conductive adhesive is preferred.
- space is shown between frame pad 32 and the corresponding inner connective site 22 of the upper one of the constituent stacked assemblies 70 of the depicted exemplar stacked module 50. The depicted space is provided for clarity of the exposition and those of skill will understand that frame pads 32 and connective sites 22 are connected.
- solder 74 is shown as an exemplar connective material between frame pads 32 and connective sites 22 of the exemplar stacked module 50.
- Fig. 8 depicts an enlarged cross-sectional view of an exemplar stacked IC module 50 devised in accord with an embodiment as seen along line D - D of Fig. 5.
- the application contacts are not shown but the wire bonds 33 between IC die 2 IB and substrates 20 of stackable assemblies are shown.
- upper die 12T is disposed on substrate 20 while lower die 12B is seen emergent from beneath substrate 20 exposing die pads 13 that are to be wire-bonded to wire bond pads 24 of substrate 20.
- both die 12T and 12B connected to the same side of substrate 20 even though the two die are attached to different sides of that substrate.
- the wire bond pads 24 of upper die 12T are not visible in the depiction of Fig. 8.
- Frame member 30 is shown along lateral edge 27 of substrates 20 and, in practice, those of skill will recognize that typically, two frame members 30 are typically employed when, for example, two stackable assemblies 70 are stacked to create a stacked module 50 and those frame members will typically be disposed along edges 27 and 23 of first and second redistribution substrates 20.
- the example shown illustrates die with bond-pads along one edge, it can be seen that the same techniques illustrated would work with pads along two adjacent edges. In such instances, the lower and upper die are displaced along both axes to expose the bond out pads of the lower die for wire bonding to two edges of the substrate. In such instances, the substrate would be extended along one or both axes to allow for contacts and positioning of the frame members.
- Fig. 9 illustrates the wire bond connection between upper die 12T and substrate 20 in a stacked module 50 comprised from four (4) stackable assemblies.
- the embodiment depicted in Fig. 9 illustrates how wire bonds 33 nest into the space between substrates as indicated by dimension "X" that is, at a minimum, the thickness of a selected upper die 12T and an adjacent selected lower die 12B.
- dimension "X" that is, at a minimum, the thickness of a selected upper die 12T and an adjacent selected lower die 12B.
- the thickness of upper die 12T has been indicated in Fig. 8 rather than Fig. 9 and is indicated with reference 12TT while the thickness of lower die 12B is indicated with reference 12BT.
- an adhesive or other bond 51 is used between adjacent upper and lower die 12T and 12B, respectively. Consequently, where adhesive or bonding layer 51 is present, "X" will also include the thickness of layer 51 between the respective die. Thus, because the wire bond does not extend above the surface of the redistribution substrate a distance greater than "X", the wire bond does not contribute to the overall height of stacked module 50 except as to the top-most one of the multiple assemblies.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
The present invention provides a system and method for devising stackable assemblies (70) that may be then stacked to create a stacked circuit module (50). One or more integrated circuit (IC) die (12) are disposed on one or more sides of a redistribution substrate (20) that is preferably flexible circuitry. In some preferred embodiments, the die (12) and redistribution substrate (20) are bonded together and wire-bond (33) connected. Two or more stackable assemblies (70) are interconnected through frame members (30) to create low profile high density stacked circuit modules (50).
Description
STACKABLE MICROPACKAGES AND STACKED MODULES
CROSS REFERENCE TO RELATED APPLICATIONS:
[0001] This application claims priority to provisional application
No. 60/862,431 filed October 20, 2006, pending, which is hereby incorporated by reference.
TECHNICAL FIELD
[0002] The present invention relates to aggregating integrated circuits and, in particular, to stacks and stacking integrated circuits.
BACKGROUND
[0003] A variety of techniques are used to stack integrated circuits into a module. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. Both leaded and BGA type packaged integrated circuits (ICs) have been stacked. Although BGA packaging has become widely adopted, leaded packages are still employed in large volumes in low cost applications such as, for example, flash memory, which, when packaged, is typically found in thin small outline packages otherwise known as TSOPs. [0004] Other technologies have been devised to stack bare die or flip-chip configured integrated circuits. In a typical example, flex circuitry upon which such integrated circuits have been affixed has been employed to supplant the role of encapsulating packaging. In some strategies, flex circuitry bearing bare or flip- chip die is folded over itself to yield a multi-level module in which the constituent die are disposed vertically one above the other with module contacts being provided along one or more surfaces of the flex circuitry. In other strategies, such as purportedly disclosed in U.S. Pat. No. 6,388,333 to Taniguchi, et al, a substrate bears an integrated circuit die that is encapsulated by a seal material having a
height less than protruding electrodes connected to pads on the redistribution substrate which are connected to the die. Other previous systems have purportedly disposed flip-chip devices active face down on substrates that are connected one to another through conductive members as described in U.S. Pat. No. 6,781,241 to Nishimura et al.
[0005] Most previous systems that employ unpackaged die have provided complex structures with attendant scalability and construction technique complexities. Consequently, what is needed is a system and method for stacks and stacking die that is readily adaptable to scalability, while using well understood materials with facility for known good die management.
SUMMARY
[0006] The present invention provides a system and method for stacked circuit modules and stackable assemblies that may be stacked to create a stacked circuit module. One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry. In some preferred embodiments, the die and redistribution substrate are bonded together and wire-bond connected. Two or more stackable assemblies are interconnected through frame members to create low profile, high density stacked circuit modules.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Fig. 1 depicts an exemplar IC die as may be employed in embodiments.
[0008] Fig. 2 depicts an exemplar redistribution substrate as may be employed in embodiments.
[0009] Fig. 3 depicts a frame member that may be employed in embodiments of the present stacked module.
[00010] Fig. 4 is an enlarged depiction of a pad and via construction in an exemplar frame member as seen along line A - A in Fig. 3.
[00011] Fig. 5 is a perspective depiction of an exemplar stacked module in accordance with an embodiment.
[00012] Fig. 6 is a cross-sectional depiction of an exemplar stacked IC module devised in accord with an embodiment as seen along line B - B of Fig. 5.
[00013] Fig. 7 is an enlarged depiction of a portion of the cross-sectional view of a stacked module identified in Fig. 6 by "C".
[00014] Fig. 8 depicts an enlarged cross-sectional view of an exemplar stacked IC module devised in accord with an embodiment as seen along line D - D of Fig. 5.
[00015] Fig. 9 depicts an enlarged cross-sectional view of an exemplar stacked IC module devised in accord with an embodiment.
DETAILED DESCRIPTION
[00016] Fig. 1 depicts an exemplar IC die 12 as may be employed in embodiments of a stacked module. IC die 12 has a first side 11 and second side (indicated by reference 9) and edge 8 proximal to which are found plural die pads 13. Although the present invention may be employed to advantage with die of a variety of functions and sizes, it is particularly advantageous for use with memory IC die including but not limited to flash memory. Through the present invention, IC die may be aggregated in a vertical stacked module that provides high density and helps ameliorate the steep next-generation cost slope typically encountered when higher memory density demands are satisfied with higher cost next generation monolithic devices. Depicted die 12 shown in Fig. l should be considered a proxy for any of a variety of die that can be stacked to advantage and, in particular, memory IC die. As shown, die 12 exhibits die pads 13 which, as
those of skill will recognize, can be located in a variety of locations, but are often found along one or more edges of the die such as the identified edge 8. [00017] Fig. 2 depicts an exemplar redistribution substrate 20 as may be employed in embodiments. Although it can be devised from a variety of conductive substrates capable of bearing a network of conductive traces and connectors, substrate 20 is preferably a flexible circuit devised with a thin profile and has upper surface 21 and indicated lower surface 25 which those of skill will understand is present but not visible in the view of Fig. 2. Many techniques can be employed to reduce the thickness of substrate 20 including, for example, devising the substrate without a covercoat. As shown in FIG. 2, substrate 20 exhibits connective sites 22 along edges 23 and 27 of substrate 20 which sites are, in a preferred embodiment, typically pads which are well known in the art in a variety of configurations. Typically, connective sites 22 are on each of sides 21 and 25 of substrate 20.
[00018] The disclosed stackable assemblies can be interconnected through the respective connection sites 22 to form a stacked circuit module. Wire bond pads 24 are shown adjacent to edges 26 and 28 of surface 21 of substrate 20. When a lower die 12B (as shown in later Figs.) is attached to lower surface 25 of substrate 20, it is preferably disposed so that it is emergent beyond one of the perimeter edges of substrate 20 to expose its own die pads 13 for wire bond connection to substrate 20. This allows the wire bonding operation to be done without repositioning of the substrate assembly. Typically, this will require rotation of lower die 12B 180 degrees relative to the orientation of upper die 12T. Die 12 and substrate 20 are, typically but not always, close to the same size so that the advantages provided by the use of stackable assemblies disclosed herein are not outweighed by the minor increase in size.
[00019] Fig. 3 depicts a frame member 30 that may be employed in some embodiments of the present stacked module. As shown, frame member 30
exhibits frame pads 32 having vias 34 that provide connection between upper and lower frame pads along upper and lower sides 35 and 37 respectively of frame member 30. Preferably, the distance between upper and lower sides 35 and 37 of frame member 30 is less than twice the thickness of IC die 12. Frame member 30 provides structure or stiffness for stacked module embodiments and is disposed at least in part between substrates 20 in a stacked module embodiment as will be shown in more detail. As those of skill will appreciate, frame member 30 is preferably disposed along the row of connective sites 22 adjacent to selected sides of substrate 20 and thus provides connection and structure between stackable assemblies. Frame member 30 can be devised from a variety of materials such as, for example, circuit board material such as FR4 or other epoxy or fiber structural material appropriate for support of a network of conductive pad structures and vias. Frame member 30 can be devised in accordance with low profile objectives and those of skill will appreciate that die thickness is one of the determinants of minimum thickness for frame member 30.
[00020] Fig. 4 is an enlarged depiction of a pad and via construction in an exemplar frame member 30 as seen along line A - A in Fig. 3. As shown, frame pads 32 can be formed on each of sides 35 and 37 of frame member 30 with a hole that is preferably plated to create via 34 that passes between the frame pad 32 on side 35 to the corresponding frame pad 32 on side 37.
[00021] Fig. 5 is a perspective depiction of an exemplar stacked module 50 in accordance with an embodiment. As shown in Fig. 5, die 12T is disposed on upper surface 21 of substrate 20 and wire-bonded to wire bond pads 24 along side 26 of substrate 20 through exemplar wire bonds 33. Shown emergent from beneath substrate 20, lower die 12B is also wire-bonded to wire bond pads 24 along upper surface 21 near edge 28 of substrate 20 as shown by the exemplar wire bonds 33.
[00022] The depiction of Fig. 5 includes four (4) die 12 and two substrates 20 in a high density stacked circuit module 50 in accordance with an embodiment. Stacked module 50 is preferably encapsulated with any of the variety of encapsulants known in the industry. The encapsulant is represented by arcing dotted line E across module 50.
[00023] Fig. 6 is a cross-sectional depiction of an exemplar stacked IC module
50 devised in accord with an embodiment as seen along line B - B of Fig. 5. In the view of Fig. 6, two stacked packages are stacked together to create stacked module 50. Also shown in Fig. 6, application contact 60 provides the capability to connect stacked module 50 to an application environment. As those of skill will recognize, application contacts 60 can be configured in a variety of different dimensions and shapes to correspond to the constraints of the particular application where stacked module 50 is employed. The depicted example of a ball contact serving as application contact 60 should be understood to merely be an example and not limiting of the many different configurations available for application contact 60 such as, for example, pads. For example, it is also possible to use an additional frame member 30 in place of contacts 60 to connect a stacked module to a transposer substrate or system board.
[00024] Fig. 7 is an enlarged depiction of a portion of the cross-sectional view of stacked module 50 identified in Fig. 6 by "C". As shown in Fig. 7, frame member 30 is disposed (at least in part) between corresponding inner connective sites 22 of two different stackable assemblies 70 that are bonded together. If adhesives are used, a thermally conductive adhesive is preferred. In the depiction of Fig. 7, space is shown between frame pad 32 and the corresponding inner connective site 22 of the upper one of the constituent stacked assemblies 70 of the depicted exemplar stacked module 50. The depicted space is provided for clarity of the exposition and those of skill will understand that frame pads 32 and connective sites 22 are connected. Between lower frame pad 32 and the inner
connective site 22 of stackable assembly 7OB (lower in Fig. 7) solder 74 is shown as an exemplar connective material between frame pads 32 and connective sites 22 of the exemplar stacked module 50.
[00025] Fig. 8 depicts an enlarged cross-sectional view of an exemplar stacked IC module 50 devised in accord with an embodiment as seen along line D - D of Fig. 5. For clarity of the exposition, the application contacts are not shown but the wire bonds 33 between IC die 2 IB and substrates 20 of stackable assemblies are shown. As shown in Fig. 8, upper die 12T is disposed on substrate 20 while lower die 12B is seen emergent from beneath substrate 20 exposing die pads 13 that are to be wire-bonded to wire bond pads 24 of substrate 20. Thus, both die 12T and 12B connected to the same side of substrate 20 even though the two die are attached to different sides of that substrate. The wire bond pads 24 of upper die 12T are not visible in the depiction of Fig. 8. Frame member 30 is shown along lateral edge 27 of substrates 20 and, in practice, those of skill will recognize that typically, two frame members 30 are typically employed when, for example, two stackable assemblies 70 are stacked to create a stacked module 50 and those frame members will typically be disposed along edges 27 and 23 of first and second redistribution substrates 20. Although the example shown illustrates die with bond-pads along one edge, it can be seen that the same techniques illustrated would work with pads along two adjacent edges. In such instances, the lower and upper die are displaced along both axes to expose the bond out pads of the lower die for wire bonding to two edges of the substrate. In such instances, the substrate would be extended along one or both axes to allow for contacts and positioning of the frame members.
[00026] Fig. 9 illustrates the wire bond connection between upper die 12T and substrate 20 in a stacked module 50 comprised from four (4) stackable assemblies. The embodiment depicted in Fig. 9 illustrates how wire bonds 33 nest into the space between substrates as indicated by dimension "X" that is, at a minimum, the
thickness of a selected upper die 12T and an adjacent selected lower die 12B. For purposes of clarity of view, the thickness of upper die 12T has been indicated in Fig. 8 rather than Fig. 9 and is indicated with reference 12TT while the thickness of lower die 12B is indicated with reference 12BT.
[00027] Typically an adhesive or other bond 51 is used between adjacent upper and lower die 12T and 12B, respectively. Consequently, where adhesive or bonding layer 51 is present, "X" will also include the thickness of layer 51 between the respective die. Thus, because the wire bond does not extend above the surface of the redistribution substrate a distance greater than "X", the wire bond does not contribute to the overall height of stacked module 50 except as to the top-most one of the multiple assemblies.
[00028] Although the present invention has been described in detail, it will be apparent that those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.
Claims
1. A stacked circuit module comprised of: a first IC die having first and second surfaces with die pads disposed along the first surface; a second IC die having first and second surfaces with die pads disposed along the first surface and proximal to a die edge; a first redistribution substrate having a first side and a second side and first, second, third and fourth perimeter edges and plural connective sites and wire bond pads, the plural connective sites being disposed along each of the first and second sides and located proximal to at least the first and third perimeter edges of the first redistribution substrate while the wire bond pads are disposed on the first side of the first redistribution substrate proximal to the second and fourth perimeter edges, the first IC die being attached on its second surface to the first side of the first redistribution substrate and the die pads of the first IC die being wire-bonded to the wire bond pads of the first redistribution substrate proximal to the second perimeter edge and the second IC die being attached on its first surface to the second side of the first redistribution substrate and disposed to extend beyond the fourth perimeter edge of the first redistribution substrate and the die pads of the second IC die are wire-bonded to the wire bond pads of the first redistribution substrate proximal to the fourth perimeter edge; a third IC die having first and second surfaces with die pads disposed along the first surface; a fourth IC die having first and second surfaces with die pads disposed along the first surface and proximal to a die edge of the fourth IC die; a second redistribution substrate having a first side and a second side and first, second, third and fourth perimeter edges and plural connective sites and wire bond pads, the plural connective sites being disposed along each of the first and second sides and located proximal to at least the first and third perimeter edges of the second redistribution substrate while the wire bond pads are disposed on the first side of the second redistribution substrate proximal to the second and fourth perimeter edges, the third IC die being attached on its second surface to the first side of the second redistribution substrate and the die pads of the third IC die being wire-bonded to the wire bond pads of the second redistribution substrate proximal to the second perimeter edge and the fourth IC die being attached on its first surface to the second side of the second redistribution substrate and disposed to extend beyond the fourth perimeter edge of the second redistribution substrate and the die pads of the fourth IC die are wire-bonded to the wire bond pads of the second redistribution substrate proximal to the fourth perimeter edge; and first and second frame members each having first and second frame member sides with plural frame pads on each of the first and second frame member sides, the first and second frame members being disposed at least in part between the first and second redistribution substrates to provide connection between the first and second redistribution substrates.
2. The circuit module of claim 1 further comprising application contacts.
3. The circuit module of claim 1 in which the third IC die is wired bonded to the second redistribution substrate with wire bonds and at least some of which wire bonds lie at least in part between the first and second redistribution substrates and rise no further above the first side of the second redistribution substrate than the sum of the thickness of the second IC die and the third IC die.
4. The circuit module of claim 1 in which the first and second redistribution substrates are comprised of flexible circuitry.
5. The circuit module of claim 1 in which the frame members are comprised of circuit board material.
6. The circuit module of claim 1 in which the frame members are disposed proximal to the first and third perimeter edges of the first and second redistribution substrates to provide connection between the plural connective sites of the first and second redistribution substrates.
7. The circuit module of claim 6 in which the frame members are thinner than the second IC die or the third IC die.
8. The circuit module of claim 6 further comprising an encapsulant disposed about at least the first IC die.
9. A stackable assembly comprising: a first IC memory circuit die having die pads along a first die surface of the first IC memory die; a second IC memory circuit die having die pads along a first die surface of the second IC memory die; a first redistribution substrate comprised of flexible circuitry, the first redistribution substrate having a first side and a second side and first, second, third and fourth perimeter edges and plural connective sites and wire bond pads, the plural connective sites being disposed along each of the first and second sides and located proximal to at least the first and third perimeter edges of the first redistribution substrate while the wire bond pads are disposed on the first side of the first redistribution substrate proximal to the second and fourth perimeter edges, the first IC memory circuit die being attached on its second surface to the first side of the first redistribution substrate and the die pads of the first IC memory circuit die being wire-bonded to the wire bond pads of the first redistribution substrate proximal to the second perimeter edge and the second IC memory circuit die being attached on its first surface to the second side of the first redistribution substrate and disposed to extend beyond the fourth perimeter edge of the first redistribution substrate and the die pads of the second IC memory circuit die are wire-bonded to the wire bond pads of the first redistribution substrate proximal to the fourth perimeter edge.
10. A stacked circuit module comprised from two iterations of the stackable assembly of claim 9.
11. A stacked circuit module comprised from three iterations of the stackable assembly of claim 9.
12. A stackable assembly comprising: a first IC die having first and second faces and die pads on the first face of the first IC die which are disposed along an edge of the first IC die; a second IC die having first and second faces and die pads on the first face of the second IC die which are disposed along an edge of the second IC die; a redistribution substrate comprised of flexible circuitry, the redistribution substrate having four perimeter sides, and a first side and a second side with the first side having wire bond pads, the first IC die being attached on its second face to the first side of the redistribution substrate and the second IC die being attached on its first face to the second side of the redistribution substrate with the second IC die rotated 180 degrees relative to the disposition of the first IC die and the second IC die extending beyond at least one of the four perimeter edges of the redistribution substrate to expose the die pads of the second IC die, the first and second IC die each being wire- bond connected to the wire bond pads of the first side of redistribution substrate.
13. A stacked circuit module comprised from two iterations of the stackable assembly of claim 12 and further comprising frame members disposed at least in part between the redistribution substrates of the two respective stackable assemblies to provide connection between said redistribution substrates.
14. The stacked circuit module of claim 13 in which the frame members are disposed proximal to at least two of the four perimeter sides of the redistribution substrates.
15. The stacked circuit module of claim 14 in which the frame members are comprised of circuit board material.
16. The stacked circuit module of claim 14 in which the frame members are comprised of frame pads connected through a via.
17. The stacked circuit module of claim 14 in which the frame members are comprised of epoxy or resin.
18. The stacked circuit module of claim 14 in which the first and second IC die are each flash memory circuits.
19. The stackable assembly of claim 12 in which the first and second IC die are flash memory circuits.
20. A stacked module comprising multiple iterations of the stackable assembly of claim 12.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86243106P | 2006-10-20 | 2006-10-20 | |
US60/862,431 | 2006-10-20 | ||
US11/682,643 | 2007-03-06 | ||
US11/682,643 US7468553B2 (en) | 2006-10-20 | 2007-03-06 | Stackable micropackages and stacked modules |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008060816A2 true WO2008060816A2 (en) | 2008-05-22 |
WO2008060816A3 WO2008060816A3 (en) | 2008-07-24 |
Family
ID=39317135
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/081931 WO2008060816A2 (en) | 2006-10-20 | 2007-10-19 | Stackable micropackages and stacked modules |
Country Status (2)
Country | Link |
---|---|
US (1) | US7468553B2 (en) |
WO (1) | WO2008060816A2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7888185B2 (en) * | 2006-08-17 | 2011-02-15 | Micron Technology, Inc. | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
US20110051385A1 (en) * | 2009-08-31 | 2011-03-03 | Gainteam Holdings Limited | High-density memory assembly |
US8415808B2 (en) | 2010-07-28 | 2013-04-09 | Sandisk Technologies Inc. | Semiconductor device with die stack arrangement including staggered die and efficient wire bonding |
KR20140109134A (en) * | 2013-03-05 | 2014-09-15 | 삼성전자주식회사 | Semiconductor package having multi-channel and related electronic system |
US10483237B2 (en) | 2016-11-11 | 2019-11-19 | Semiconductor Components Industries, Llc | Vertically stacked multichip modules |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376904B1 (en) * | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
US20040201087A1 (en) * | 2003-01-03 | 2004-10-14 | Dong-Ho Lee | Stack package made of chip scale packages |
US6878571B2 (en) * | 2000-06-21 | 2005-04-12 | Staktek Group L.P. | Panel stacking of BGA devices to form three-dimensional modules |
Family Cites Families (167)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3436604A (en) | 1966-04-25 | 1969-04-01 | Texas Instruments Inc | Complex integrated circuit array and method for fabricating same |
US3654394A (en) | 1969-07-08 | 1972-04-04 | Gordon Eng Co | Field effect transistor switch, particularly for multiplexing |
US3772776A (en) | 1969-12-03 | 1973-11-20 | Thomas & Betts Corp | Method of interconnecting memory plane boards |
US3704455A (en) | 1971-02-01 | 1972-11-28 | Alfred D Scarbrough | 3d-coaxial memory construction and method of making |
US3746934A (en) | 1971-05-06 | 1973-07-17 | Siemens Ag | Stack arrangement of semiconductor chips |
US3766439A (en) | 1972-01-12 | 1973-10-16 | Gen Electric | Electronic module using flexible printed circuit board with heat sink means |
US3983547A (en) | 1974-06-27 | 1976-09-28 | International Business Machines - Ibm | Three-dimensional bubble device |
US4288841A (en) | 1979-09-20 | 1981-09-08 | Bell Telephone Laboratories, Incorporated | Double cavity semiconductor chip carrier |
US4398235A (en) | 1980-09-11 | 1983-08-09 | General Motors Corporation | Vertical integrated circuit package integration |
US4437235A (en) * | 1980-12-29 | 1984-03-20 | Honeywell Information Systems Inc. | Integrated circuit package |
JPS57181146A (en) | 1981-04-30 | 1982-11-08 | Hitachi Ltd | Resin-sealed semiconductor device |
US4513368A (en) | 1981-05-22 | 1985-04-23 | Data General Corporation | Digital data processing system having object-based logical memory addressing and self-structuring modular memory |
US4406508A (en) | 1981-07-02 | 1983-09-27 | Thomas & Betts Corporation | Dual-in-line package assembly |
JPS58159360A (en) | 1982-03-17 | 1983-09-21 | Fujitsu Ltd | Semiconductor device |
US4466183A (en) | 1982-05-03 | 1984-08-21 | National Semiconductor Corporation | Integrated circuit packaging process |
US4567543A (en) * | 1983-02-15 | 1986-01-28 | Motorola, Inc. | Double-sided flexible electronic circuit module |
US4656605A (en) | 1983-09-02 | 1987-04-07 | Wang Laboratories, Inc. | Single in-line memory module |
JPS6055458A (en) * | 1983-09-05 | 1985-03-30 | Matsushita Electric Ind Co Ltd | Cmos transistor circuit |
KR890004820B1 (en) | 1984-03-28 | 1989-11-27 | 인터내셔널 비지네스 머신즈 코포레이션 | Stacked double density memory module using industry standard memory chips |
US4587596A (en) | 1984-04-09 | 1986-05-06 | Amp Incorporated | High density mother/daughter circuit board connector |
EP0213205B1 (en) * | 1984-12-28 | 1992-12-09 | Micro Co., Ltd. | Method of stacking printed circuit boards |
WO1993013557A1 (en) * | 1985-02-14 | 1993-07-08 | Yoshiyuki Sato | Structure for mounting the semiconductor chips in a three-dimensional manner |
DE3675321D1 (en) | 1985-08-16 | 1990-12-06 | Dai Ichi Seiko Co Ltd | SEMICONDUCTOR ARRANGEMENT WITH PACK OF PIN PLUG TYPE. |
US4696525A (en) | 1985-12-13 | 1987-09-29 | Amp Incorporated | Socket for stacking integrated circuit packages |
US4850892A (en) | 1985-12-16 | 1989-07-25 | Wang Laboratories, Inc. | Connecting apparatus for electrically connecting memory modules to a printed circuit board |
US4709300A (en) | 1986-05-05 | 1987-11-24 | Itt Gallium Arsenide Technology Center, A Division Of Itt Corporation | Jumper for a semiconductor assembly |
US4763188A (en) | 1986-08-08 | 1988-08-09 | Thomas Johnson | Packaging system for multiple semiconductor devices |
US4821007A (en) | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
US5159535A (en) | 1987-03-11 | 1992-10-27 | International Business Machines Corporation | Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate |
US4862249A (en) | 1987-04-17 | 1989-08-29 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
KR970003915B1 (en) * | 1987-06-24 | 1997-03-22 | 미다 가쓰시게 | Semiconductor device and the use memory module |
IT1214254B (en) | 1987-09-23 | 1990-01-10 | Sgs Microelettonica S P A | SEMICONDUCTOR DEVICE IN PLASTIC OR CERAMIC CONTAINER WITH "CHIPS" FIXED ON BOTH SIDES OF THE CENTRAL ISLAND OF THE "FRAME". |
US5016138A (en) | 1987-10-27 | 1991-05-14 | Woodman John K | Three dimensional integrated circuit package |
US4983533A (en) * | 1987-10-28 | 1991-01-08 | Irvine Sensors Corporation | High-density electronic modules - process and product |
US5198888A (en) * | 1987-12-28 | 1993-03-30 | Hitachi, Ltd. | Semiconductor stacked device |
US4833568A (en) | 1988-01-29 | 1989-05-23 | Berhold G Mark | Three-dimensional circuit component assembly and method corresponding thereto |
JP2600753B2 (en) * | 1988-02-03 | 1997-04-16 | 日本電気株式会社 | Input circuit |
US4891789A (en) * | 1988-03-03 | 1990-01-02 | Bull Hn Information Systems, Inc. | Surface mounted multilayer memory printed circuit board |
US5253010A (en) | 1988-05-13 | 1993-10-12 | Minolta Camera Kabushiki Kaisha | Printed circuit board |
JPH025375A (en) | 1988-06-24 | 1990-01-10 | Toshiba Corp | Actual fitting of electronic component |
US5025306A (en) | 1988-08-09 | 1991-06-18 | Texas Instruments Incorporated | Assembly of semiconductor chips |
US4911643A (en) * | 1988-10-11 | 1990-03-27 | Beta Phase, Inc. | High density and high signal integrity connector |
US4956694A (en) | 1988-11-04 | 1990-09-11 | Dense-Pac Microsystems, Inc. | Integrated circuit chip stacking |
WO1990006609A1 (en) * | 1988-11-16 | 1990-06-14 | Motorola, Inc. | Flexible substrate electronic assembly |
EP0382203B1 (en) * | 1989-02-10 | 1995-04-26 | Fujitsu Limited | Ceramic package type semiconductor device and method of assembling the same |
DE69006609T2 (en) | 1989-03-15 | 1994-06-30 | Ngk Insulators Ltd | Ceramic lid for closing a semiconductor element and method for closing a semiconductor element in a ceramic package. |
US4953060A (en) | 1989-05-05 | 1990-08-28 | Ncr Corporation | Stackable integrated circuit chip package with improved heat removal |
US5104820A (en) | 1989-07-07 | 1992-04-14 | Irvine Sensors Corporation | Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting |
US5200362A (en) | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5012323A (en) | 1989-11-20 | 1991-04-30 | Micron Technology, Inc. | Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe |
US5191404A (en) * | 1989-12-20 | 1993-03-02 | Digital Equipment Corporation | High density memory array packaging |
JPH03227541A (en) | 1990-02-01 | 1991-10-08 | Hitachi Ltd | Semiconductor device |
US5041015A (en) | 1990-03-30 | 1991-08-20 | Cal Flex, Inc. | Electrical jumper assembly |
US5345205A (en) | 1990-04-05 | 1994-09-06 | General Electric Company | Compact high density interconnected microwave system |
US5053853A (en) | 1990-05-08 | 1991-10-01 | International Business Machines Corporation | Modular electronic packaging system |
US5261068A (en) | 1990-05-25 | 1993-11-09 | Dell Usa L.P. | Dual path memory retrieval system for an interleaved dynamic RAM memory unit |
US5050039A (en) | 1990-06-26 | 1991-09-17 | Digital Equipment Corporation | Multiple circuit chip mounting and cooling arrangement |
US5241456A (en) | 1990-07-02 | 1993-08-31 | General Electric Company | Compact high density interconnect structure |
US5065277A (en) | 1990-07-13 | 1991-11-12 | Sun Microsystems, Inc. | Three dimensional packaging arrangement for computer systems and the like |
US5377077A (en) | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
WO1992003035A1 (en) | 1990-08-01 | 1992-02-20 | Staktek Corporation | Ultra high density integrated circuit packages, method and apparatus |
US5499160A (en) * | 1990-08-01 | 1996-03-12 | Staktek Corporation | High density integrated circuit module with snap-on rail assemblies |
US5140405A (en) | 1990-08-30 | 1992-08-18 | Micron Technology, Inc. | Semiconductor assembly utilizing elastomeric single axis conductive interconnect |
US5117282A (en) | 1990-10-29 | 1992-05-26 | Harris Corporation | Stacked configuration for integrated circuit devices |
US5289346A (en) * | 1991-02-26 | 1994-02-22 | Microelectronics And Computer Technology Corporation | Peripheral to area adapter with protective bumper for an integrated circuit chip |
JPH04284661A (en) * | 1991-03-13 | 1992-10-09 | Toshiba Corp | Semiconductor device |
US5219794A (en) | 1991-03-14 | 1993-06-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of fabricating same |
US5289062A (en) * | 1991-03-18 | 1994-02-22 | Quality Semiconductor, Inc. | Fast transmission gate switch |
US5099393A (en) * | 1991-03-25 | 1992-03-24 | International Business Machines Corporation | Electronic package for high density applications |
US5138430A (en) | 1991-06-06 | 1992-08-11 | International Business Machines Corporation | High performance versatile thermally enhanced IC chip mounting |
US5714802A (en) * | 1991-06-18 | 1998-02-03 | Micron Technology, Inc. | High-density electronic module |
JPH0513666A (en) | 1991-06-29 | 1993-01-22 | Sony Corp | Complex semiconductor device |
US5311401A (en) | 1991-07-09 | 1994-05-10 | Hughes Aircraft Company | Stacked chip assembly and manufacturing method therefor |
US5252857A (en) | 1991-08-05 | 1993-10-12 | International Business Machines Corporation | Stacked DCA memory chips |
US5281852A (en) * | 1991-12-10 | 1994-01-25 | Normington Peter J C | Semiconductor device including stacked die |
US5397916A (en) * | 1991-12-10 | 1995-03-14 | Normington; Peter J. C. | Semiconductor device including stacked die |
US5198965A (en) * | 1991-12-18 | 1993-03-30 | International Business Machines Corporation | Free form packaging of specific functions within a computer system |
US5241454A (en) | 1992-01-22 | 1993-08-31 | International Business Machines Corporation | Mutlilayered flexible circuit package |
US5262927A (en) | 1992-02-07 | 1993-11-16 | Lsi Logic Corporation | Partially-molded, PCB chip carrier package |
US5224023A (en) | 1992-02-10 | 1993-06-29 | Smith Gary W | Foldable electronic assembly module |
US5208729A (en) | 1992-02-14 | 1993-05-04 | International Business Machines Corporation | Multi-chip module |
US5268815A (en) | 1992-02-14 | 1993-12-07 | International Business Machines Corporation | High density, high performance memory circuit package |
US5243133A (en) | 1992-02-18 | 1993-09-07 | International Business Machines, Inc. | Ceramic chip carrier with lead frame or edge clip |
US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5229916A (en) | 1992-03-04 | 1993-07-20 | International Business Machines Corporation | Chip edge interconnect overlay element |
US5313096A (en) | 1992-03-16 | 1994-05-17 | Dense-Pac Microsystems, Inc. | IC chip package having chip attached to and wire bonded within an overlying substrate |
US5259770A (en) | 1992-03-19 | 1993-11-09 | Amp Incorporated | Impedance controlled elastomeric connector |
US5361228A (en) | 1992-04-30 | 1994-11-01 | Fuji Photo Film Co., Ltd. | IC memory card system having a common data and address bus |
US5422435A (en) | 1992-05-22 | 1995-06-06 | National Semiconductor Corporation | Stacked multi-chip modules and method of manufacturing |
US5247423A (en) | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
US5729894A (en) * | 1992-07-21 | 1998-03-24 | Lsi Logic Corporation | Method of assembling ball bump grid array semiconductor packages |
US5229917A (en) | 1992-07-24 | 1993-07-20 | The United States Of America As Represented By The Secretary Of The Air Force | VLSI integration into a 3-D WSI dual composite module |
US5266912A (en) * | 1992-08-19 | 1993-11-30 | Micron Technology, Inc. | Inherently impedance matched multiple integrated circuit module |
JPH0679990A (en) * | 1992-09-04 | 1994-03-22 | Mitsubishi Electric Corp | Ic memory card |
JP3105089B2 (en) * | 1992-09-11 | 2000-10-30 | 株式会社東芝 | Semiconductor device |
US5402006A (en) * | 1992-11-10 | 1995-03-28 | Texas Instruments Incorporated | Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound |
US5313097A (en) | 1992-11-16 | 1994-05-17 | International Business Machines, Corp. | High density memory module |
US5375041A (en) | 1992-12-02 | 1994-12-20 | Intel Corporation | Ra-tab array bump tab tape based I.C. package |
US5347428A (en) | 1992-12-03 | 1994-09-13 | Irvine Sensors Corporation | Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip |
US6205654B1 (en) * | 1992-12-11 | 2001-03-27 | Staktek Group L.P. | Method of manufacturing a surface mount package |
US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
US5390844A (en) * | 1993-07-23 | 1995-02-21 | Tessera, Inc. | Semiconductor inner lead bonding tool |
US5386341A (en) * | 1993-11-01 | 1995-01-31 | Motorola, Inc. | Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape |
KR970000214B1 (en) * | 1993-11-18 | 1997-01-06 | 삼성전자 주식회사 | Semiconductor device and method of producing the same |
EP0658937A1 (en) * | 1993-12-08 | 1995-06-21 | Hughes Aircraft Company | Vertical IC chip stack with discrete chip carriers formed from dielectric tape |
US5502333A (en) * | 1994-03-30 | 1996-03-26 | International Business Machines Corporation | Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit |
US5715144A (en) * | 1994-12-30 | 1998-02-03 | International Business Machines Corporation | Multi-layer, multi-chip pyramid and circuit board structure |
US5592364A (en) * | 1995-01-24 | 1997-01-07 | Staktek Corporation | High density integrated circuit module with complex electrical interconnect rails |
US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
US5612570A (en) * | 1995-04-13 | 1997-03-18 | Dense-Pac Microsystems, Inc. | Chip stack and method of making same |
US6025642A (en) * | 1995-08-17 | 2000-02-15 | Staktek Corporation | Ultra high density integrated circuit packages |
US5861666A (en) * | 1995-08-30 | 1999-01-19 | Tessera, Inc. | Stacked chip assembly |
US6013948A (en) * | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US6784023B2 (en) * | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
JP2755252B2 (en) * | 1996-05-30 | 1998-05-20 | 日本電気株式会社 | Semiconductor device package and semiconductor device |
US6030856A (en) * | 1996-06-10 | 2000-02-29 | Tessera, Inc. | Bondable compliant pads for packaging of a semiconductor chip and method therefor |
US6008538A (en) * | 1996-10-08 | 1999-12-28 | Micron Technology, Inc. | Method and apparatus providing redundancy for fabricating highly reliable memory modules |
US6336262B1 (en) * | 1996-10-31 | 2002-01-08 | International Business Machines Corporation | Process of forming a capacitor with multi-level interconnection technology |
JP3695893B2 (en) * | 1996-12-03 | 2005-09-14 | 沖電気工業株式会社 | Semiconductor device, manufacturing method and mounting method thereof |
US6225688B1 (en) * | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
JP3455040B2 (en) * | 1996-12-16 | 2003-10-06 | 株式会社日立製作所 | Source clock synchronous memory system and memory unit |
US6208521B1 (en) * | 1997-05-19 | 2001-03-27 | Nitto Denko Corporation | Film carrier and laminate type mounting structure using same |
US6014316A (en) * | 1997-06-13 | 2000-01-11 | Irvine Sensors Corporation | IC stack utilizing BGA contacts |
US6028352A (en) * | 1997-06-13 | 2000-02-22 | Irvine Sensors Corporation | IC stack utilizing secondary leadframes |
US6040624A (en) * | 1997-10-02 | 2000-03-21 | Motorola, Inc. | Semiconductor device package and method |
US5869353A (en) * | 1997-11-17 | 1999-02-09 | Dense-Pac Microsystems, Inc. | Modular panel stacking process |
DE19754874A1 (en) * | 1997-12-10 | 1999-06-24 | Siemens Ag | Converting substrate with edge contacts into ball grid array |
US6021048A (en) * | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6028365A (en) * | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US6172874B1 (en) * | 1998-04-06 | 2001-01-09 | Silicon Graphics, Inc. | System for stacking of integrated circuit packages |
US6180881B1 (en) * | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
JP3186700B2 (en) * | 1998-06-24 | 2001-07-11 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
SG75873A1 (en) * | 1998-09-01 | 2000-10-24 | Texas Instr Singapore Pte Ltd | Stacked flip-chip integrated circuit assemblage |
US6187652B1 (en) * | 1998-09-14 | 2001-02-13 | Fujitsu Limited | Method of fabrication of multiple-layer high density substrate |
US6239485B1 (en) * | 1998-11-13 | 2001-05-29 | Fujitsu Limited | Reduced cross-talk noise high density signal interposer with power and ground wrap |
US6222737B1 (en) * | 1999-04-23 | 2001-04-24 | Dense-Pac Microsystems, Inc. | Universal package and method of forming the same |
US6323060B1 (en) * | 1999-05-05 | 2001-11-27 | Dense-Pac Microsystems, Inc. | Stackable flex circuit IC package and method of making same |
US6351029B1 (en) * | 1999-05-05 | 2002-02-26 | Harlan R. Isaak | Stackable flex circuit chip package and method of making same |
JP3526788B2 (en) * | 1999-07-01 | 2004-05-17 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
US6370668B1 (en) * | 1999-07-23 | 2002-04-09 | Rambus Inc | High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes |
KR100344927B1 (en) * | 1999-09-27 | 2002-07-19 | 삼성전자 주식회사 | Stack package and method for manufacturing the same |
US6489178B2 (en) * | 2000-01-26 | 2002-12-03 | Texas Instruments Incorporated | Method of fabricating a molded package for micromechanical devices |
US6528870B2 (en) * | 2000-01-28 | 2003-03-04 | Kabushiki Kaisha Toshiba | Semiconductor device having a plurality of stacked wiring boards |
JP3855594B2 (en) * | 2000-04-25 | 2006-12-13 | セイコーエプソン株式会社 | Semiconductor device |
US6522018B1 (en) * | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
US20020006032A1 (en) * | 2000-05-23 | 2002-01-17 | Chris Karabatsos | Low-profile registered DIMM |
US6683377B1 (en) * | 2000-05-30 | 2004-01-27 | Amkor Technology, Inc. | Multi-stacked memory package |
US6525413B1 (en) * | 2000-07-12 | 2003-02-25 | Micron Technology, Inc. | Die to die connection method and assemblies and packages including dice so connected |
JP4397109B2 (en) * | 2000-08-14 | 2010-01-13 | 富士通株式会社 | Information processing apparatus and crossbar board unit / back panel assembly manufacturing method |
KR100400765B1 (en) * | 2000-11-13 | 2003-10-08 | 엘지.필립스 엘시디 주식회사 | Method for forming thin-film and liquid crystal display device fabricated by the same method |
JP2002184937A (en) * | 2000-12-18 | 2002-06-28 | Shinko Electric Ind Co Ltd | Mounting structure of semiconductor device |
US6712226B1 (en) * | 2001-03-13 | 2004-03-30 | James E. Williams, Jr. | Wall or ceiling mountable brackets for storing and displaying board-based recreational equipment |
US6707684B1 (en) * | 2001-04-02 | 2004-03-16 | Advanced Micro Devices, Inc. | Method and apparatus for direct connection between two integrated circuits via a connector |
US6532162B2 (en) * | 2001-05-26 | 2003-03-11 | Intel Corporation | Reference plane of integrated circuit packages |
DE10131939B4 (en) * | 2001-07-02 | 2014-12-11 | Qimonda Ag | Electronic circuit board with a plurality of housing-type housing semiconductor memories |
US6451626B1 (en) * | 2001-07-27 | 2002-09-17 | Charles W.C. Lin | Three-dimensional stacked semiconductor package |
WO2003019654A1 (en) * | 2001-08-22 | 2003-03-06 | Tessera, Inc. | Stacked chip assembly with stiffening layer |
US6674644B2 (en) * | 2001-11-01 | 2004-01-06 | Sun Microsystems, Inc. | Module and connector having multiple contact rows |
SG115459A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
US6873039B2 (en) * | 2002-06-27 | 2005-03-29 | Tessera, Inc. | Methods of making microelectronic packages including electrically and/or thermally conductive element |
US6838761B2 (en) * | 2002-09-17 | 2005-01-04 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US6869825B2 (en) * | 2002-12-31 | 2005-03-22 | Intel Corporation | Folded BGA package design with shortened communication paths and more electrical routing flexibility |
US6686656B1 (en) * | 2003-01-13 | 2004-02-03 | Kingston Technology Corporation | Integrated multi-chip chip scale package |
US6853064B2 (en) * | 2003-05-12 | 2005-02-08 | Micron Technology, Inc. | Semiconductor component having stacked, encapsulated dice |
KR100592786B1 (en) * | 2003-08-22 | 2006-06-26 | 삼성전자주식회사 | Stack package made of area array type packages, and manufacturing method thereof |
US20050018495A1 (en) * | 2004-01-29 | 2005-01-27 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
-
2007
- 2007-03-06 US US11/682,643 patent/US7468553B2/en active Active
- 2007-10-19 WO PCT/US2007/081931 patent/WO2008060816A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376904B1 (en) * | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
US6878571B2 (en) * | 2000-06-21 | 2005-04-12 | Staktek Group L.P. | Panel stacking of BGA devices to form three-dimensional modules |
US20040201087A1 (en) * | 2003-01-03 | 2004-10-14 | Dong-Ho Lee | Stack package made of chip scale packages |
Also Published As
Publication number | Publication date |
---|---|
US20080093724A1 (en) | 2008-04-24 |
US7468553B2 (en) | 2008-12-23 |
WO2008060816A3 (en) | 2008-07-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10468380B2 (en) | Stackable microelectronic package structures | |
US7723839B2 (en) | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device | |
KR20050001159A (en) | Multi-chip package having a plurality of flip chips and fabrication method thereof | |
US20130147060A1 (en) | Semiconductor package | |
JP4970610B2 (en) | Semiconductor device manufacturing method and lead frame | |
US7468553B2 (en) | Stackable micropackages and stacked modules | |
CN100524736C (en) | A stacking type wafer packaging structure | |
US20120286398A1 (en) | Semiconductor chip module and planar stack package having the same | |
US20030015803A1 (en) | High-density multichip module and method for manufacturing the same | |
US20050035467A1 (en) | Semiconductor package using flexible film and method of manufacturing the same | |
KR20040069392A (en) | Stacked type semiconductor multichip package | |
KR100947146B1 (en) | Semiconductor package | |
US7304382B2 (en) | Managed memory component | |
CN1652334A (en) | Chip stage package for integrated multi-chip | |
KR100826976B1 (en) | Planar stack package | |
JP2003037244A (en) | Tape carrier for semiconductor device and semiconductor device using the same | |
KR100681686B1 (en) | Semiconductor package | |
CN1441493A (en) | Semiconductor element in stacked structure | |
KR100639203B1 (en) | Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package | |
KR101195460B1 (en) | Stacked semiconductor package | |
KR20090011966A (en) | Stack package and method for fabricating of the same | |
KR20060074714A (en) | Chip stack package | |
KR20030045949A (en) | A stack package and a manufacturing method thereof | |
KR20060133802A (en) | Semiconductor package | |
KR20050012591A (en) | Semiconductor package and package module stacking it |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07868514 Country of ref document: EP Kind code of ref document: A2 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 07868514 Country of ref document: EP Kind code of ref document: A2 |