WO2008065822A1 - Encoding device and encoding method - Google Patents
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- WO2008065822A1 WO2008065822A1 PCT/JP2007/070156 JP2007070156W WO2008065822A1 WO 2008065822 A1 WO2008065822 A1 WO 2008065822A1 JP 2007070156 W JP2007070156 W JP 2007070156W WO 2008065822 A1 WO2008065822 A1 WO 2008065822A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
- H03M7/4006—Conversion to or from arithmetic code
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/124—Quantisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/136—Incoming video signal characteristics or properties
- H04N19/14—Coding unit complexity, e.g. amount of activity or edge presence estimation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/146—Data rate or code amount at the encoder output
- H04N19/15—Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/189—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding
- H04N19/192—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding the adaptation method, adaptation tool or adaptation type being iterative or recursive
- H04N19/194—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding the adaptation method, adaptation tool or adaptation type being iterative or recursive involving only two passes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
Definitions
- the present invention relates to an encoding apparatus and method, and more particularly to an encoding apparatus and method to which arithmetic encoding is applied.
- Arithmetic coding is a technique that can reversibly compress the amount of information to a theoretical limit in accordance with the occurrence probability of the information source symbol. Arithmetic coding is adopted in the field of image coding in the JPEG2000 standard (ISO / lEC15444), the H.264 / MPEG4-AVC standard (see Non-Patent Document 1), and the like.
- CABAC Context Adaptive Binary Arithmetic Coding
- a binarization circuit 130 binarizes multi-value input data that is encoded information power such as transform coefficient data and flags.
- binarization distinguishes the syntax element (syntax element) which is the type of input data from the control information, and the probability characteristics of the data, unary binarization or unary binarization.
- the binary symbol (binary) sequence binarized by the binarization circuit 130 is sent to the (binary) arithmetic coding circuit 140. This is done using different methods such as fixed-length binarization. Entered.
- the context calculation circuit 520 Based on the control information indicating the syntax element, the context calculation circuit 520 converts the value of the context index (ctxldx) used to encode the current 1 bit in the binary symbol sequence to the H.264 standard. It is determined uniquely with reference to the table defined in.
- the context calculation circuit 520 initializes and stores occurrence probability information for each value of ctxldx. Occurrence probability information is the symbol of the higher occurrence probability of “0” or “1” of the binary symbol. It is a set of MPS indicating Bol and occurrence probability pState. Occurrence probability information corresponding to the calculated value of ctxldx is called “context information”.
- the context calculation circuit 520 generates context information 504 and outputs it to the arithmetic coding circuit 140.
- the occurrence probability of a symbol input to the arithmetic encoding circuit 140 that is, the context information 504 is adaptively switched by a syntax element that performs arithmetic encoding, so that the occurrence probability of a binary symbol dynamically changes.
- Optimal arithmetic coding can be performed on the value symbol string 503.
- the total bit length (symbol length) of the binary symbol sequence is called “symbol amount”, and the total bit length of the output code after arithmetic coding is called “code amount”.
- the total bit length of a binary symbol sequence that is generated when multi-value input data in a certain interval is processed is called “generated binary symbol amount”, and the total bit length of output code is called “generated code amount”.
- the occurrence probability of symbol “0” is 0.75 (binary 0.11) and symbol “1” occurrence probability is 0.25 from the source of ⁇ 0, 0, 0, 1 ⁇ .
- the occurrence probability pState is expressed as a normalized integer value, but here it is a binary value for simplicity.
- the context information 504 is updated by the current binary arithmetic coding and returned to the context calculation circuit 520.
- the context calculation circuit 520 updates the occurrence probability information of the corresponding ctxldx. This value is reused when the same context is encoded next time.
- the value “011” after the decimal point becomes the output binary string, and the 4-bit input value is compressed to 3 bits. That's it. Actually, when the output bit (0 or 1) is determined, a process called renormalization is performed to shift the left bit of the probability value.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2004-135251
- Non-Patent Document 1 I ⁇ > ⁇ IEC14496— 10 Advanced video coding for generic audiovisual services
- an upper limit value (BinCountsInNALunits) of a binary symbol amount is specified for the purpose of specifying the maximum processing amount in the decoder (see Non-Patent Document 1). .
- this upper limit value it is necessary to control the code amount and binary symbol amount.
- By defining this upper limit value it is possible to define the upper limit value of the circuit operating time. For example, in Patent Document 1, a limit monitor for the amount of binary symbols to be input to the arithmetic encoder is prepared, and when the threshold value is exceeded, the encoder is re-encoded or a plurality of encoding parameters are applied in parallel. The amount of binary symbols is controlled by encoding.
- the present invention has been made in consideration of the above-described problems, and an object of the present invention is an encoding apparatus to which arithmetic encoding is applied, which can reduce the amount of binary symbols with a simple circuit configuration.
- An object of the present invention is to provide an encoding device that performs encoding with guaranteed decoding operation while controlling the following, and at the same time, accurately realizes code amount control.
- an apparatus for quantizing and encoding an input signal wherein an upper limit value of a symbol amount of binary symbols generated by quantization is determined.
- the encoding device includes a signal processing circuit that performs predetermined signal processing on an input signal, a quantization parameter generation circuit that generates a first quantization parameter, and an input signal that has undergone predetermined signal processing.
- a first quantization circuit that generates the first quantized data by quantizing based on the first quantization parameter, binarizes the first quantized data, and outputs the first binary
- a first binarization circuit that outputs symbol data
- a first binarization unit that performs arithmetic coding on the first binary symbol data based on a predetermined target code amount to generate first encoded data Based on the arithmetic coding circuit, the symbol amount of the first binary symbol data, the code amount of the first encoded data, the second quantization parameter, the upper limit value of the symbol amount, and the target code amount.
- the encoding method includes a step of performing predetermined signal processing on an input signal, a step of generating a first quantization parameter, and an input signal having been subjected to predetermined signal processing into a first quantity.
- the amount of generated binary symbols is controlled to be equal to or less than the upper limit value with a simple circuit configuration, and at the same time, the code amount control of the output bitstream is accurately performed. Therefore, it is possible to provide a bit stream in which the code amount is accurately kept within a predetermined amount and the decoding operation is guaranteed.
- FIG. 1 is a configuration diagram of a video encoding device according to an embodiment of the present invention.
- FIG. 4 (a) A diagram illustrating a specific example of the representative quantization parameter, (b) a diagram illustrating an example of applying the representative quantization parameter to a macroblock in the case of the progressive method, and (c) an interlace. Diagram showing an example of applying representative quantization parameters to macroblocks in the case of the method
- FIG. 5 is a diagram showing a specific example of the generated binary symbol amount and the generated code amount for each representative quantization parameter stored in the binary symbol amount ′ code amount integrated value memory.
- FIG. 6 Diagram for explaining how to calculate the optimal quantization parameter based on the amount of generated binary symbols
- FIG. 7 A diagram for explaining a method for calculating an optimal quantization parameter based on a generated code amount.
- FIG. 8 is a block diagram of an encoding device to which the idea of the present invention can be applied.
- FIG. 9 is a diagram showing the configuration of a conventional context adaptive arithmetic coding circuit
- an intra frame that can be decoded within a frame is a target for encoding, and the amount of binary symbols obtained by encoding is controlled to be equal to or less than a predetermined upper limit value, and the amount of code is controlled with high accuracy.
- the encoding device will be described. [0025] 1. Composition of video symbol ⁇ Hh
- FIG. 1 shows the configuration of a video encoding apparatus according to the embodiment of the present invention.
- a video encoding apparatus 100 includes a first encoding circuit 101 that performs provisional encoding, a second encoding circuit 102 that performs regular encoding, a frame memory 151, and a prediction mode memory 152.
- the first encoding circuit 101 includes a blocking circuit 161 for blocking the input digital video signal, a prediction mode detection circuit 173, an intra prediction generation circuit 171, and a DCT as an orthogonal transformation circuit.
- the circuit 181, the quantization circuit 121, the quantization parameter generation circuit 111, the binarization circuit 131, and the arithmetic coding circuit 141 are configured.
- the second encoding circuit 102 includes a blocking circuit 162 for blocking the input digital video signal, an intra prediction generation circuit 172, a DCT circuit 182, a quantization circuit 122, The quantization parameter calculation circuit 112, the binarization circuit 132, the arithmetic coding circuit 142, the inverse quantization circuit 124, and the inverse DCT circuit 184 are configured.
- the first encoding circuit 101 When the video encoding device 100 receives a digital video signal of one frame, the first encoding circuit 101 performs a temporary encoding process of the video signal for one frame.
- the digital video signal input to the video encoding device 100 is also stored in the frame memory 151, delayed by a predetermined time within one frame, and output to the second encoding circuit 102.
- the second encoding circuit 102 reads data from the frame memory 151, performs normal encoding processing on the read data, and outputs a bit stream as a result of encoding.
- the prediction mode detection circuit 173 detects a prediction mode for intra prediction, and stores the value in the prediction mode memory 152. Also, the binary symbol amount and code amount output from the binarization circuit 131 and arithmetic coding circuit 141 are stored in the binary symbol / code amount integrated value memory 153. The second encoding circuit 102 multiplies the prediction mode value stored in the prediction mode memory 152 and the binary symbol amount / binary symbol amount stored in the code amount integrated value memory 153 and the code amount. The optimal quantization parameter is determined in response to the value, and normal encoding processing is performed on the video signal of the same frame as the frame processed by the first encoding circuit 101.
- the processing of the first encoding circuit 101 will be described.
- the blocking circuit 161 divides the image indicated by the input digital video signal of one frame into a plurality of macroblocks of 16 ⁇ 16 pixels.
- a macroblock contains multiple blocks that are processing units for DCT and intra prediction.
- the intra prediction generation circuit 171 varies the value of each pixel of the macroblock from the pixel of the input digital video signal and the pixel adjacent to the image of the input digital video signal. Prediction in the prediction mode.
- the prediction modes include field macroblock decoding flag (mb—field—decoding—flag), luminance 4 ⁇ 4 intra prediction mode (Intra4x4PredMode), luminance 8 ⁇ 8 intra prediction mode (Intra8x8PredMode), color difference intra prediction mode (intra —Chroma-pred-mode) is included. Intra prediction may be done in units of 8 x 8 pixel blocks or 4 x 4 pixel blocks! /.
- the prediction mode detection circuit 173 detects an optimum prediction mode from the four prediction modes, and outputs the information as a prediction mode value.
- the prediction mode value is stored in the prediction mode memory 152.
- a difference value between each pixel value of the macroblock to be encoded in the input digital video signal and a predicted value of each pixel of the macroblock to be encoded generated by the intra prediction generation circuit 171 is calculated. Then, a block of difference values of 16 ⁇ 16 pixels is generated and output to the DCT circuit 181.
- the DCT circuit 181 performs DCT processing on the block of difference values. DCT processing is usually
- the quantization parameter generation circuit 111 generates a quantization parameter that defines a quantization rate at the time of quantization. In this embodiment, the possible values of the quantization parameter are 0 to 51, and the smaller the value, the higher the quantization rate.
- the quantization parameter generation circuit 111 has a plurality of quantization parameters (hereinafter referred to as “representative quantization parameters”) qp as candidates for quantization parameters to be generated.
- the quantization parameter generation circuit 11 1 selects one of a plurality of representative quantization parameters qp for each macroblock and outputs it as a quantization parameter QP for the quantization of the macroblock. Details of the quantization parameter determination processing of the quantization parameter generation circuit 111 will be described later.
- the coefficient data quantized by the quantizing circuit 121 is binarized by the binarizing circuit 131, and thereafter arithmetic coded by the arithmetic coding circuit 141.
- the binary symbol amount 'code amount product circuit 154 converts the symbol amount of the binary symbol output from the binarization circuit 131 and the code amount of the code output from the arithmetic encoding circuit 141 into the same quantum. Integration is performed for each macroblock group to which the conversion parameter is applied, and the integrated value is stored in the binary symbol amount / code amount integrated value memory 153.
- prediction pixels for intra prediction are obtained from a digital video signal for provisional encoding. Predicted pixels for intra prediction specified by the H.264 standard should not be used for the following reasons.
- a quantization parameter is changed by the quantization parameter generation circuit 111 and a code amount and a binary symbol amount are output. Therefore, when a decoded pixel is used, the value of the quantization parameter is changed. When it is large, the accuracy of the decoded pixel is deteriorated, and the accuracy of the predicted pixel of the subsequent macroblock is lowered.
- the inverse quantization circuit and the inverse DCT circuit in provisional encoding can be omitted, and the circuit scale can be reduced.
- the video signal of one frame stored in the frame memory 151 is input to the blocking circuit 162 of the second encoding circuit 102.
- the blocking circuit 162 divides an image of one frame of video signal into a plurality of macro blocks each having 16 ⁇ 16 pixels.
- the intra prediction generation circuit 172 reads the prediction mode value from the prediction mode memory 152, and obtains a pixel prediction value for each pixel of the macroblock to be encoded using the prediction mode indicated by the prediction mode value. At this time, the values of adjacent pixels used by the intra prediction generation circuit 172 for intra prediction are generated by the inverse quantization circuit 124 and the inverse DCT circuit 184.
- the intra prediction generation circuit 172 calculates a difference value between the pixel prediction value and the pixel value of the macroblock to be encoded for each pixel to obtain a block of difference values.
- the DCT circuit 182 performs DCT processing on the block of difference values obtained in this way, and outputs coefficient data of frequency components.
- the coefficient data is input to the quantization circuit 122.
- the quantization circuit 121 quantizes the coefficient data according to the quantization parameter.
- the quantization parameter is calculated by the quantization parameter calculation circuit 112.
- the quantization circuit 121 outputs the quantized coefficient data to the binarization circuit 132 and the inverse quantization circuit 124.
- the quantization parameter calculation circuit 112 acquires the binary symbol amount and encoding amount obtained by the first encoding hunting 101 from the binary symbol amount / code amount integrated value memory 153, and these values are obtained. Quantization parameters are determined based on The detailed operation of the quantization parameter generation circuit 112 will be described later.
- the binarization circuit 132 converts the quantized coefficient data into a binary symbol.
- the arithmetic encoding circuit 142 arithmetically encodes the binary symbol from the binarizing circuit 132 and outputs the result as a bit stream.
- a target code amount indicating an upper limit value of the generated code amount is defined!
- the coefficient data quantized by the quantization circuit 122 is inversely quantized by the inverse quantization circuit 124 and then subjected to inverse DCT processing by the inverse DCT circuit 184.
- the value of the adjacent pixel of the encoding target macroblock used for intra prediction is obtained.
- the quantization parameter generation operation by the quantization parameter generation circuit 111 of the first encoding circuit 101 will be described.
- a description will be given of a case where the optimum quantization parameter is calculated for each slice in provisional encoding of one frame of 1920 ⁇ 1080 pixels.
- a slice into which a frame is divided is an arbitrary set of consecutive macroblocks. Defined.
- a 1920X1080 pixel frame consists of 16X16 macroblocks.
- provisional quantization parameter QP (n) used in quantization circuit 121 of first encoding circuit 101 is determined.
- the temporary quantization parameter QP (n) is the macroblock
- Each parameter is set to one parameter selected from multiple parameter candidates (representative quantization parameters). That is, the temporary quantization parameter QP (n).
- the quantization parameter is determined to include the maximum and minimum values of the specified quantization parameter
- the data is selected from two types of representative quantization parameters so that the frequency of appearance of each representative quantization parameter is equal.
- the quantization parameter “0” is given to half of the macroblocks
- the quantization parameter “20” is given to the other half of the macroblocks.
- temporary quantization parameters are arranged alternately or randomly in the slice. For example, in progressive scan, as shown in Fig. 3 (a), representative quantization parameters are alternately given in the order of normal raster scan, and in interlace scan, macroblock pairs are set as shown in Fig. 3 (b).
- the representative quantization parameter can be given alternately every time.
- the number Q of representative quantization parameters used in the quantization circuit 121 can be set to a divisor of the number of macroblocks included in one slice. By setting the number Q of representative quantization parameters in this way, the number of times each representative quantization parameter appears in the slice can be kept constant. it can. At that time, if the scanning method is the progressive method, the number of representative quantization parameters
- Q can be a divisor of the number of macroblocks. Also, when pairing macroblocks for interlace coding, it can be set to a divisor that is half the number of macroblocks included in one slice. For example, if the number of macroblocks included in one slice is 2040, 5, 10, and 20 can be selected as the number Q of representative quantization parameters. For each Q, the number of appearances of each representative quantization parameter in one slice is 408, 204, and 102, respectively.
- the representative quantization parameter qp (X) is a quantization parameter that can be selected by the encoder.
- Q different values are selected from the range. In this case, it is preferable to appropriately distribute these values so that code amount prediction for optimal encoding can be easily performed.
- Fig. 4 (a) you can select the representative quantization parameter of ⁇ 0, 4, 8, 12, 16, 22, 28, 34, 42, 51 ⁇ .
- the representative quantization parameter is applied as shown in FIG. 4 (b)
- the representative quantization parameter is applied as shown in FIG. 4 (c).
- the binary symbol amount / code amount integration circuit 154 integrates the binary symbol amount and the code amount obtained as a result of the temporary encoding in the first encoding circuit 101 for each macroblock using the same representative quantization parameter. Each accumulated value is stored in the accumulated value memory 153. Hereinafter, this operation will be specifically described.
- the amount of code generated by QP r (x), which is the sum of the quantity R ( ⁇ ), is the binary symbol quantity 'code quantity integrated value me
- the target code amount T and the upper limit binary symbol amount B of the slice allocated using information such as bit rate, frame rate, frame complexity, and slice coding type are set as follows.
- the second encoding circuit 102 generates a generated symbol amount b (X) and a generated code amount r (X) for each representative quantization parameter obtained as a result of provisional encoding in the first encoding circuit 101. ) And upper limit of 2 values
- the optimal quantization parameter QP is determined based on the symbol amount and the target code amount.
- the quantization parameter calculation circuit 112 calculates the optimum quantization parameter based on the binary symbol amount and the optimum quantization parameter based on the code amount, compares the calculation results, and compares them.
- the left and right quantization parameters are used as the optimal quantization parameters. Details will be described below.
- Figure 6 shows the representative quantization parameter qp (X) and each quantization parameter.
- FIG. 6 is a diagram showing a relationship between binary symbol amounts predicted in units of slices.
- the generated binary symbol quantity b (X) for each QP is the value of the macro to which the same quantization parameter QP is applied.
- CEIL [x] is a function that returns the smallest integer greater than or equal to x.
- q is an integer of 0 ⁇ q ⁇ Q— 1 and satisfies QXb (q + 1) ⁇ B ⁇ QXb (q).
- Figure 7 shows the representative quantization parameter qp (X) and the quantization parameter QP.
- FIG. 1 A first figure.
- the generated code amount r (x) for each QP is a macroblock to which the same quantization parameter QP is applied.
- code I can power S.
- QP The calculation of QP is obtained by the following equation by linear interpolation.
- Equation (2) When the optimal quantization parameter candidate QP is calculated using Equation (2), it is about 16.84.
- the quantization parameter must be an integer, so round off the decimal point to 17
- the quantization parameter calculation circuit 112 calculates the larger one of the optimal quantization parameter candidate QP based on the binary symbol amount obtained as described above and the optimal quantization parameter candidate QP bin cod based on the code amount. Is selected as the optimal quantization parameter QP and output to the quantization circuit 122 e opt
- encoding can be performed according to the statistical properties of the input data, and the amount of generated code can be kept low.
- the code amount is somewhat smaller than the target code amount, but binary.
- the upper limit of the symbol amount is satisfied. Conversely, when the amount of binary symbols is relatively small and the amount of codes is large, QP is selected, and the amount of binary symbols is kept to a certain extent below the upper limit. Since it is close to the target code amount, it can be encoded into a value.
- the generated binary symbol amount and the generated code amount are set for each of the plurality of representative quantization parameters. Ask. Thereafter, in the second encoding circuit 102, an optimum quantization parameter is obtained in consideration of the upper limit binary symbol amount and the target code amount based on the value obtained by provisional coding.
- the optimum quantization parameter can be determined in the one-way processing flow, so that a complicated circuit configuration for restoring the occurrence probability information of the updated arithmetic coding as in the past is used. This eliminates the need for an arithmetic coding circuit in parallel! /, Thus simplifying the circuit configuration.
- the video encoding apparatus is particularly effective when the code amount per frame is constant.
- the video encoding apparatus has a decoder buffer state that is critical even when encoding with a limit value for the code amount in frame units or for encoding with no limit value for the code amount in frame units. This is effective when the code amount of the current frame is limited. The reason will be described below.
- Non-Patent Document 1 it is necessary to comply with the definition of the upper limit value of the binary symbol amount by increasing the code amount using stuffing called cabac_zero_word. However, if the code amount is increased, the code amount may exceed the limit value and the coding may be broken. As exemplary type condition, because it can control the binary symbol amount below an upper limit value of the binary symbol amount calculated relative to the limiting value, stuffing of cabac_ Ze r 0 _ WO rd is needed However, the amount of code will always be below the limit value and will not fail. Therefore, the idea of this embodiment is particularly effective in the case described above.
- Subsequent quantization parameters can control the binary symbol amount and code amount by feedback control, and can dynamically change the optimal quantization parameter QP (n).
- the optimal quantization parameter QP QP (n)
- the accumulated code amount R (n) at the time of encoding is added in the range of 0 ⁇ n ⁇ m in the macroblock of macroblock number m.
- the remaining code amount (T—B) which is the difference between the generated code amount B and the target code amount T until a certain point in time (for example, the macroblock number N—1), is expressed as the remaining macroblock n (m ⁇ n ⁇ This can be implemented by setting the target code amount S to N—1).
- provisional encoding and normal encoding are performed in units of slices, but the generated code amount R (n) is obtained by performing provisional encoding and normal encoding in smaller units. May be.
- the processing unit for provisional encoding and regular encoding is fixed, the unit for provisional encoding and regular encoding can be dynamically changed in units of frames or other units.
- the slice prediction code amount was obtained by linear interpolation, advanced numerical interpolation such as spline interpolation can also be used.
- the QP-specific generated binary symbol quantity b (X) and the QP-generated generated code quantity r (x) are
- Binary symbol amount ⁇ Code amount integrated value memory 153 The power S explained in the example of accumulation, the generated binary symbol amount B (n) and the generated code amount R (n) for each macroblock before calculating the sum Accumulate
- the total sum may be calculated after reading from the binary symbol amount / code amount integrated value memory 153.
- provisional encoding processing may be performed a plurality of times.
- context adaptive computation in the H.264 standard for video coding is used.
- the description has been given by taking the example of the technical coding.
- the idea of the present invention can be applied when arithmetic coding is performed on quantized coefficient data, and can be applied to an encoding device that can adaptively change the quantization parameter.
- an encoding device 200 includes a first encoding circuit 201 that performs provisional encoding processing on an input signal, a second encoding circuit 202 that performs normal encoding, and an input signal.
- the first encoding circuit 201 includes a signal processing circuit 261 that performs predetermined signal processing on the input signal, a quantization circuit 221, a quantization parameter generation circuit 211, and a binarization circuit 231. And an arithmetic coding circuit 241.
- the second encoding circuit 202 includes a signal processing circuit 262 that performs predetermined signal processing on the input signal, a quantization circuit 222, a quantization parameter calculation circuit 212, and a binarization circuit 232. And an arithmetic coding circuit 242.
- the encoding apparatus 200 configured as described above performs the following operation during the provisional encoding process.
- the signal processing circuit 261 performs predetermined signal processing on the input signal, and the quantization circuit 221 quantizes the signal output from the signal processing circuit 261 based on the temporary quantization parameter from the quantization parameter generation circuit 211. To do.
- the quantized signal is binarized by the binarization circuit 231 and then arithmetically encoded by the arithmetic encoding circuit 241.
- the binary symbol amount-code amount integrating circuit 254 calculates the symbol amount of the binary symbol output from the binarizing circuit 231 and the code amount of the code output from the arithmetic encoding circuit 241 for each predetermined unit. Accumulate and store the accumulated value in the binary symbol amount.code amount integrated value memory 253. The processing of the binary symbol amount. Code amount integrating circuit 254 is as described above.
- the signal processing circuit 262 performs predetermined signal processing on the input signal delayed for a predetermined time by the delay memory 251.
- the quantization circuit 222 quantizes the input signal that has undergone predetermined signal processing using the quantization parameter from the quantization parameter calculation circuit 212.
- the method for determining the quantization parameter in the quantization parameter calculation circuit 212 is as described above. So Thereafter, processing is performed by the binarization circuit 232 and the arithmetic coding circuit 242 and a bit stream is output.
- the bit stream encoded using the present embodiment can be recorded on a recording medium such as a tape, an optical disk, a magnetic disk, a semiconductor memory, and the like so as to be redistributable.
- a recording medium such as a tape, an optical disk, a magnetic disk, a semiconductor memory, and the like so as to be redistributable.
- the functions of the respective circuits in the encoding device of Figs. 1 and 8 are realized by software, and the software is executed by a microprocessor, so that the same functions as those of the encoding device of Figs. 1 and 8 are achieved. It can also be realized.
- the present invention is effective for a data recording apparatus that requires real-time operation with a small circuit scale, such as a digital camera recorder or a recording apparatus.
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EP07829890.8A EP2088784B1 (en) | 2006-11-28 | 2007-10-16 | Encoding device and encoding method |
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JP5257215B2 (ja) * | 2009-04-16 | 2013-08-07 | ソニー株式会社 | 画像符号化装置と画像符号化方法 |
WO2011080851A1 (ja) * | 2009-12-28 | 2011-07-07 | パナソニック株式会社 | 画像符号化装置および集積回路 |
BR112012031160B1 (pt) * | 2010-06-10 | 2022-04-19 | Interdigital Vc Holdings, Inc. | Método em um decodificador de vídeo, decodificador de vídeo e mídia de armazenamento legível por computador para determinação de preditores de parâmetros de quantização a partir de uma pluralidade de parâmetros de quantização vizinhos |
EP2830054A1 (en) | 2013-07-22 | 2015-01-28 | Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V. | Audio encoder, audio decoder and related methods using two-channel processing within an intelligent gap filling framework |
WO2018074291A1 (ja) * | 2016-10-18 | 2018-04-26 | パナソニックIpマネジメント株式会社 | 画像符号化方法、伝送方法および画像符号化装置 |
CN111052742A (zh) * | 2017-09-30 | 2020-04-21 | 深圳市大疆创新科技有限公司 | 图像处理 |
JPWO2021084679A1 (ja) * | 2019-10-31 | 2021-05-06 |
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CN101502122B (zh) | 2011-06-01 |
US20090263036A1 (en) | 2009-10-22 |
CN101502122A (zh) | 2009-08-05 |
EP2088784A4 (en) | 2011-09-07 |
US8170359B2 (en) | 2012-05-01 |
EP2088784A1 (en) | 2009-08-12 |
JP5231243B2 (ja) | 2013-07-10 |
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