WO2008077244A1 - Independent link and bank selection - Google Patents

Independent link and bank selection Download PDF

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Publication number
WO2008077244A1
WO2008077244A1 PCT/CA2007/002320 CA2007002320W WO2008077244A1 WO 2008077244 A1 WO2008077244 A1 WO 2008077244A1 CA 2007002320 W CA2007002320 W CA 2007002320W WO 2008077244 A1 WO2008077244 A1 WO 2008077244A1
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WO
WIPO (PCT)
Prior art keywords
link
bank
memory
output
logic
Prior art date
Application number
PCT/CA2007/002320
Other languages
French (fr)
Inventor
Hong Beom Pyeon
Hakjune Oh
Jin-Ki Kim
Original Assignee
Mosaid Technologies Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Incorporated filed Critical Mosaid Technologies Incorporated
Priority to KR1020097015434A priority Critical patent/KR101370711B1/en
Priority to CN2007800515754A priority patent/CN101611453B/en
Priority to KR1020137018555A priority patent/KR101392593B1/en
Priority to JP2009541717A priority patent/JP5467573B2/en
Priority to EP07855602A priority patent/EP2126918A4/en
Publication of WO2008077244A1 publication Critical patent/WO2008077244A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Definitions

  • the Invention relates to memory systems with multiple links and multiple memory banks.
  • the memory communicates with other components using a set of parallel input/output (I/O) pins, the number of which is implementation specific.
  • the I/O pins receive command instructions and input data and provide output data. This is commonly known as a parallel interface.
  • High speed operation may cause communication degrading effects such as cross-talk, signal skew and signal attenuation, for example, which degrades signal quality.
  • serial interconnection configurations In order to incorporate higher density and faster operation on system boards, there are two design techniques: serial interconnection configurations and parallel interconnection configurations such as multi-drops. These design techniques may be used to overcome the density issue that determines the cost and operating efficiency of memory swapping between a hard disk and a memory system.
  • multi-drop configurations have a shortcoming relative to the serial interconnection configurations. For example, if the number of drops in a multi-drop memory system increases, then as a result of loading effect of each pin, delay time also increases so that the total performance of the multi-drop memory system is degraded. This is due to the wire resistor-capacitor loading and the pin capacitance of the memory device.
  • a serial link in a device such as a memory device may utilize a single pin input that receives all address, command, and data serially.
  • the serial link may provide a serial interconnection configuration to control command bits, address bits, and data bits effectively through the configuration.
  • the devices in the configuration may be memory devices, for example, dynamic random access memories (DRAMs), static random access memories (SRAMs) and Flash memories.
  • Methods and systems are provided for use in a memory system with multiple memory banks and multiple links.
  • the systems allow read and write access from any of the links to any of the banks, but circuitry is provided to prevent invalid access attempts. There is an invalid access attempt when there is simultaneous or 76181-35
  • Some implementations feature a common circuitry that is used to perform switching for every link, thereby simplifying manufacture. With such implementations, each instance of the switching circuitry is configured to function in a particular manner that reflects its position within the overall system.
  • the invention provides a memory system comprising: a plurality of memory banks; a plurality of link controllers each link controller having at least one input for receiving control and data and having at least one output for outputting the data; for each memory bank, first switching logic for receiving the at least one output for each link controller, and for passing on the at least one output of only one of the link controllers to the memory bank; for each link controller, second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller; and switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
  • the first switching logic comprises a plurality of switching elements for a corresponding plurality of outputs of each of the link controllers.
  • the second switching logic comprises a single switching element for receiving a serial output from each of the memory banks.
  • the plurality of memory banks consist of two memory banks and the plurality of link controllers consist of two link controllers. 76181-35
  • the switch controller logic comprises: a respective switch controller for each memory bank.
  • the switch controllers have substantially identical circuit implementations, wherein each switch controller comprises: link recognition logic for receiving an instruction that the switch controller is to operate according to a selected one of a plurality of possible positions for the switch controller in the system.
  • the plurality of memory banks consist of a first memory bank and a second memory bank and the switch controller logic consists of a first link controller and a second link controller, and wherein the plurality of possible positions for the switch controller in the system comprises: a first position in which the switch controller controls the first switching logic for the first bank and controls the second switching logic for the first link controller; and a second position in which the switch controller controls the first switching logic for the second bank and controls the second switching logic for the second link controller.
  • the memory system further comprises: an input for selecting single link operation; wherein upon assertion a single link operation through said input, the memory system operates as if there is only one link controller.
  • the memory system further comprises: invalid check logic for receiving bank selection outputs from each of the link controUers and for determining if there is simultaneous or overlapping access to multiple banks by the same link controller, and if so generating an invalidity signal.
  • each switch controller further comprises: a hold circuit for holding previous control outputs in the event of simultaneous or overlapping access to multiple banks by the same link controller and in the event of simultaneous or overlapping access by multiple links to the same bank.
  • each switch controller is operable to generate outputs comprising: link bank select signals for selecting which link outputs that are to be passed on to the bank; and bank select signals for selecting which bank outputs are to be passed on to the link controller.
  • each link controller comprises: an input buffer for receiving incoming command and data; serial to parallel register for converting incoming command and data to parallel form; and command interpreter control logic for interpreting incoming commands.
  • each link controller is operable to output bank select signals for the switch controller logic.
  • the invention provides a method comprising: receiving a plurality of inputs; outputting a plurality of outputs; selectably passing signals received on the plurality of inputs to memory bank inputs of a plurality of memory banks; selectably passing signals received from memory bank outputs to the plurality of outputs; and controlling the selectably passing signals received on the plurality of inputs to memory bank inputs and the selectably passing signals received from memory bank outputs to the plurality of outputs to prevent simultaneous or overlapping access from multiple inputs to the same memory bank, and to prevent simultaneous or overlapping output from multiple banks to the same output.
  • selectably passing signals received on the plurality of inputs to memory bank inputs of a plurality of memory banks comprises: for a given access from a given input of the plurality of inputs to a given memory bank of the plurality of memory banks, connecting the given memory bank to receive signals from the given input.
  • the method selectably passing signals received from memory bank outputs to the plurality of outputs comprises: for a given memory 76181-35
  • the controlling is performed by a plurality of identical switch controllers, the method further comprising: configuring each of the plurality of identical switch controllers to behave in a manner specific to their position within an overall memory system.
  • the method further comprises: upon occurrence of an invalid access attempt, either simultaneous or overlapping access from multiple inputs to the same memory bank or simultaneous or overlapping output from multiple banks to the same output comprises, maintaining a previous access state.
  • the method further comprises: detecting invalid access attempts by examining bank select signals forming part of each of the plurality of inputs.
  • the plurality of inputs and the plurality of outputs comprise a respective at least one input and a respective at least one output for each of a plurality of link controllers.
  • Figure 1 is a block diagram of a multiple independent serial link memory system
  • FIG. 2 is a detailed block diagram showing control and data signalling for a multiple independent serial link memory system
  • FIGS 3 through 6 show various valid memory access configurations for the system of Figure 2;
  • FIG. 7 is a block diagram showing details of the link controllers of Figure 2;
  • Figure 8 shows a set of simultaneous link accesses with different banks that are valid
  • Figure 9 shows two examples of linked bank accesses that are not valid
  • Figure 10 shows switching elements for control and data, and for read data
  • Figure 11 A is a block diagram showing the use of a linkJD to configure switch controllers
  • Figure 11 B is a block diagram showing the interconnection of bank select signals between link controllers and switch controllers;
  • FIG. 12 is a detailed block diagram of a switch controller
  • Figure 13 is a truth table of part of the logic of Figure 12 while operating in a two link mode.
  • Figure 14 is a truth table of part of the logic of Figure 12 while operating in a single link mode.
  • An MISL (Multiple Independent Serial Link) memory system has a set of links and a set of memory banks, and has a feature that enables accessing any bank from any link port.
  • FIG 1 shown is a conceptual block diagram of two MISL memory systems. A first example is generally indicated at 30 and depicts a dual 76181-35
  • LinkO 10 LinkO 10
  • linki 12 there are two banks, BankO 18 and Banki 20.
  • switching logic 16 interconnecting the links 10,12 and the banks 18,20. Control logic is indicated at 14.
  • the switching logic 16 can interconnect LinkO 10 to either of BankO 18 or Banki 20 as indicated at 24.
  • the switching logic 16 can interconnect Linki 12 to either of BankO 18 or Banki 20 as indicated at 26.
  • a single port configuration is indicated at 32. This is generally the same as the dual port configuration 30 except the second link Linki 12 is not used.
  • circuits that ensure that the two link ports can access the two banks for read and write operations so as to prevent invalid access conditions, such as simultaneous access to one bank from both links.
  • Control signals and data use a path determined by a bank address and the accessed link port for the accessed bank.
  • implementations might support only a subset of these features. More generally, implementations may support any number of these features.
  • Figure 2 shows an example of the connections between links and banks with several switches that corresponds with the two link, two bank example of Figure 1.
  • two banks 18,20 are connected to two independent links LinkO 10 and Linki 12 through switches 40,42,44,46 under control of switch controllers 48,50.
  • control input Bnk0 ⁇ 1 :0> 49 connected as an input to switch controllers 48,50 from LinkO 10 for functioning as a bank select control;
  • control input Bnk1 ⁇ 1 :0> 51 connected as an input to switch controllers 48,50 from Linki 12 for functioning as a bank select control; 76181-35
  • each bank has an "inside" link and an "inside" link
  • the inside link of a given bank is the link having a corresponding position to the bank, and the outside link is the remaining link.
  • the inside link for BankO is LinkO
  • the outside link for BankO is Linki
  • the inside link for Banki is Link1
  • the outside link for Banki is LinkO.
  • “Lnk_is” refers to a so-called “inside link”
  • “Lnk_os” refers to the so-called "outside link”.
  • the switch controllers 48,50 receive the control inputs 49,51 , and produce the control outputs Lnk_is_BnkO_ctrl_enable 53, Lnk_os_BnkO_ctrl_enable 60, Lnk0_Bnk_s!ct ⁇ 1 :0> 64, Lnkjs_Bnk1_ctrl_enable 63, Lnk_os_Bnk1_ctrl_enable 65, Lnk1_Bnk_slct ⁇ 1 :0> 66 in such a manner as to prevent prohibited combinations of link/bank accesses. Specifically, the two links are not permitted to access the same bank during overlapping time intervals, and the switch controllers 48, 50 operate to prevent this.
  • a BankO output 60 shown connected to each of switches 42,46; this output may be a parallel output, for example 4,8 or 16 bits depending on a particular design, with parallel to conversion being performed in the Link blocks; alternatively, if there is a 76181-35
  • this output may be a serial output; the remainder of this description assumes it is a 8-bit parallel output;
  • connection 68 interconnecting switch 46 and Linki 12.
  • commands are received at LinkO 10 and Linki 12 , and each command will be associated with one of the banks.
  • the selected bank is indicated at Bnk0 ⁇ 1 :0> 49 and this is propagated to switch controllers 48,50 while for Linki 12, the selected bank is indicated at Bnk1 ⁇ 1 :0> 51 and this also is propagated to switch controllers 48,50.
  • the switch controllers 48,50 operate to prevent contention for the same bank by multiple links. An access attempt that is does not result in contention 76181-35
  • data transferring is carried out after serial data to parallel conversion through designated registers in each link 10,12 to produce the sets of outputs 70,72.
  • serial to parallel conversion An example of a detailed implementation showing the serial to parallel conversion will be described later with reference to Figure 7.
  • the access scenarios described below include LinkO to BankO access, LinkO to Banki access, Linki to Banki access, and Linki to BankO access.
  • switch controller 48 will control switches 40 such that outputs 70 of LinkO are propagated to BankO 18 thereby establishing write data path and control path.
  • Switch controller 48 will control switch 42 such that the output 60 from BankO 18 is propagated along output 67 to LinkO 10 thereby establishing read data path.
  • switch controller 50 will control switches 44 such that outputs 70 of LinkO 10 are propagated to Banki thereby establishing write data path and control path.
  • Switch controller 50 will control switch 42 such that the output 62 from Banki 20 is propagated along output 67 to LinkO 10 thereby establishing read data path.
  • switch controller 50 will control switches 44 such that outputs 72 of Linki 12 are propagated to Banki 20 thereby establishing write data path and control path.
  • Switch controller 50 will control switch 46 such that the output 62 from Banki 20 is propagated along output 68 to Linki 12 thereby establishing read data path.
  • switch controller 48 will control switches 40 such that outputs 72 of Linki 12 are propagated to BankO thereby establishing write data path and control path.
  • Switch controller 50 will control switch 46 such that the output 60 from BankO 18 is propagated along output 68 to Linki 12 thereby establishing read data path.
  • the various access scenarios described below include LinkO to BankO access, LinkO to Banki access, Linki to Banki access, and Linki to BankO access.
  • LinkO access to BankO access is an inside operation that does not need any signals from outside.
  • the link select Lnkjs_BnkO_ctrl_enable is enabled to allow data and control inputs from LinkO to be passed on to BankO and LnkO_Bnk_slct ⁇ O> transitions to a high state thereby selecting BankO for read operations until a new command is asserted.
  • Linki to Banki access shown is another example of Linki to Banki access.
  • the case of Linki and Banki is similar to the LinkO and BankO example described with reference to Figure 3.
  • All switches placed in the middle of Banki and Linki pass data and control them to Banki .
  • Lnk_is_Bnk1_ctrl_enable transitions to high enable data and control inputs from Linki to be passed to Banki
  • Lnk1_Bnk_slct ⁇ 1> transitions to high to select Banki for read access.
  • FIG. 6 shown is another example of Linki to BankO access.
  • Linki control signals are transferred to BankO via the switches placed between BankO and LinkO.
  • Lnk_os_Bnk_ctrl_enable transitions to high to enable data and control inputs from Linki to be passed to BankO
  • global data lines ⁇ 7:0> are used to send data from the Page buffer to Link! Lnk_os_BnkO_ctrl_enable transitions to high to enable data and control inputs from Linki to be passed on to BankO, and Lnk_bnk_slct ⁇ 0> transitions to high to select BankO for read access.
  • LinkO 10, Linki 12, BankO 18 and Banki 20 are shown .
  • Switches 40,44 (individual switching elements are shown in Figure 2) interconnect the links 10,12 to the banks 18,20 and are controlled by switch controllers 48,50.
  • the outputs 70 of LinkO 10 are connected to both switches 40,44, and the outputs 72 of Link1 are connected to both switches 40,44.
  • a control output 92 from LinkO 10 is input to switch controller 48, and a control output 94 from Linki 12 is input to switch controller 50.
  • LinkO 10 has input buffers 80, serial data capture registers 82 that allows serial to parallel conversion, and command interpreter control logic 84.
  • Linki 12 has input buffers 86, serial data capture registers 88, and command interpreter control logic 90.
  • a bank address is input first with a DN (device Number) to select which device (assuming a serial interconnected memory system). Based on the bank address, each link transfers data bits to a selected bank address bit. Switch logic delay is not negligible in the 2 banks and 2 links system. However, due to the timing margin between serial to parallel conversion at registers 82, the delay is hidden while input data is being latched consecutively.
  • the command decoding in the command interpreter control logic 84 is performed after latching a bank address and making relevant control signals of switch logic so that any race timing issue between switch control signals and input data of switches does not occur.
  • the switch logic can be varied according to the logic implementation. In the specific circuits described herein, 2-input NANDs are used to perform a multiplexing function. 76181-35
  • the different links should have valid different bank access when two links are used without timing difference. This is shown by way of example in Figure 8 where there is no timing difference between accesses to two banks.
  • a first example is generally indicated at 800. In this example, there is valid simultaneous access by LinkO to BankO and Linki to Banki followed by valid simultaneous access by Linki to BankO and LinkO to Bank!
  • a second example is generally indicated at 802. In this example, there is valid simultaneous access by Linki to BankO and LinkO to Banki followed by valid simultaneous access by Linki to Banki and LinkO to BankO. Another invalid access state occurs when there is simultaneous access to the same bank from two links.
  • Figure 9 shows an example of such an invalid access. In an example generally indicated at 900, both links are simultaneously attempting to access BankO. In an example generally indicated at 901 , both links are simultaneously attempting to access Banki .
  • Banks are physically separated with dedicated logic blocks that activate the word line and bit line paths. Independent operations are achieved with flexible link and bank connections. Valid and invalid determination is made as a function of timing difference at the two links as shown in Figure 9. If there is some difference between the timing of link operations for the same bank (i.e. not simultaneous as was the case with the examples of Figure 8), then the first access is allowed, and the subsequent access is invalid and is ignored.
  • the timing difference may be varied by PVT (Process / Voltage / Temperature). In some implementations, a timing difference of at least 2 cycles is used to ensure the valid operation of the first input streams from any link input port. The timing difference is implementation specific.
  • Figure 9 shows an example of this, generally indicated at 902. There is a first valid access from Linki to BankO followed by a later invalid access from LinkO to BankO. 76181-35
  • FIG 10 generally indicated at 101 is an example of a single switching element in switch 40 or switch 44.
  • FIG 10 generally indicated at 103 is an example of a single switching element in switch 42 or switch 46.
  • the switching element 103 has a first NAND gate 110 that receives an input BankOJn from BankO and also receives the bank select signal Lnk_Br ⁇ k_slct ⁇ 0>.
  • Switching element 103 has a second NAND gate 102 that receives an Bank1_in from Banki and also receives the bank select signal Lnk__Bnk_slct ⁇ 1>.
  • Lnk0_Bnk_slct ⁇ 1 :0> are in respect of LinkO.
  • Lnk1_Bnk_slct ⁇ 1 :0> are in respect of Linki .
  • the outputs of the two NAND gates 110,112 are input to a third NAND gate 114 which combines them to produce switch output out1 115.
  • outO 115 is connected as an input to LinkO.
  • outO 115 is connected as an input to Linki .
  • the switching elements 101 ,103 are shown with specific logic components. In other implementations, the switching elements 101 ,103 have 76181-35
  • the switching elements 101 ,103 need not have any NAND gates. Other implementations are possible.
  • the system has an additional input, for example an extra input pin, that enables identical switch controller circuitry to be implemented for the switch control logic for all of the links.
  • an additional input for example an extra input pin, that enables identical switch controller circuitry to be implemented for the switch control logic for all of the links.
  • Such an input can be used to identify the link the switch control logic is functioning for.
  • FIG. 11A A summary of the logic for the purpose of illustrating link id functionality is indicated at 400 in Figure 11A. Again LinkO 12, Linki 12, BankO 18, Banki 20, and switches 42,44,46,48 are shown. Switch controller 48 is with a link id connected to
  • Switch controller 50 is with a linkjd connected to VDD, thereby selecting it to function as the switch controller for Linki 12.
  • the switch controller 50 produces Lnk1_Bnk_slct ⁇ 1 :0>, and produces Lnk_os BnkO_ctrl_enable and Lnk_is_Bnk1_ctrl enable.
  • the system has an additional input, for example an extra input pin, that allows a selection between single link configuration and multiple link configuration.
  • an additional input for example an extra input pin, that allows a selection between single link configuration and multiple link configuration.
  • an extra input pin for example an extra input pin.
  • a Singlejink input is implemented. If single link configuration is used, this pin is high. For multiple link configuration (dual link in the illustrated example), the pin is set low.
  • FIG. 11 B An example of the logic for the purpose of illustrating bank select interconnections is indicated at 401 in Figure 11 B. Again LinkO 10, Linki 12, BankO 18, Banki 20, and switches 42,44,46,48 are shown. As described previously, LinkO outputs bank select signals Bk0 ⁇ 1 :0> 49 while Linki outputs bank select signals Bk1 ⁇ 1 :0> 51. Each switch controller 48,50 has inputs for receiving Bkb ⁇ 1 :0> and Bka ⁇ 1 :0>. The suffix 'a' and 'b' of 'Bka ⁇ 1 :0>' and 'Bkb ⁇ 1 :0>' have the meaning of two different links, 76181-35
  • FIG. 12 A detailed diagram of an example implementation of the switch controllers is shown in Figure 12. It is to be understood that this implementation is very specific for example purposes only. The particular example illustrated is designed to allow it to function as a switch controller for the switches connected to/from any of the banks.
  • the circuitry generally indicated at 300 generates four control signals Inkjs, lnk_os, bk_slct ⁇ and bk_slct1 , which are used to open and close the switches that connect the links to the banks.
  • These switches may be implemented using any appropriate logic circuitry, for example circuitry having 2-input NAND gates as shown in Figure 10.
  • Link recognition logic 305 receives a linkjd input. For example, if this logic system is included in linkO block, it is 'zero', otherwise, it is 'one'. This logic allows the circuit 300 to recognize which link control block contains itself when switch control operation starts.
  • the link recognition logic has an inverter 402 that is connected to receive the linkjd input. The output of inverter 402 is input to one input of a three input NAND gate 400. The other inputs of NAND gate 400 include the single link output slink_b, and Bkb ⁇ 0>.
  • the other two outputs bk_slct ⁇ and bk_slct1 are the Lnk1_Bnk_slct ⁇ 1 :0> signals switch controller 50.
  • the circuit includes a first Invalid check logic 301. This logic is provided to prevent two bank access through one link at the same time.
  • the circuit has first NAND gate 370 that has inputs Bka ⁇ 0> AND Bka ⁇ 1 >, and a second NAND gate 372 that has inputs Bkb ⁇ 0> AND Bkb ⁇ 1 >.
  • the outputs of the two NAND gates 370,372 are input to a third NAND gate 374 the output of which is inverted with an inverter to produce an invalid_b output.
  • the Invalid check logic 301 produces an lnvalid_b output that is high if both banks are selected by one link. Specifically, if Bka ⁇ 0> AND Bka ⁇ 1 > are both high meaning both banks are selected by the same link, then the InvalidjD output is high indicating an invalid condition; if Bkb ⁇ 0> AND Bkb ⁇ 1> are both high meaning both banks are selected by the same link, then the lnvalid_b output is high indicating an invalid condition.
  • Single Link configuration circuit 302 is provided to allow the previously discussed selection of single link operation. Even though two links are more efficient for a two-bank memory system, single link also is supported as an available configuration of the memory system with the circuit described. If single link configuration is used, 'singlejink' signal becomes high and 'slink_b' will have a low state. When 'slink_b' has a low state, ink_os' becomes low and only 'Inkjs' has a valid state according to the bank address. For the two link configuration, 'singlejink' has a low state such that both outputs 'Inkjs' and 1nk_os' are valid. In the illustrated example, single link configuration circuit 302 is simply an inverter 403. 76181-35
  • the circuit 300 has a second Invalid check logic that includes functionality indicated at 303A and 303B.
  • Circuit 303A has a NAND gate 350 that receives Bka ⁇ 0> and Bkb ⁇ 0>.
  • the output of the NAND gate 350 is connected to an input of another NAND gate 352 that also receives the previously referenced Invalidja.
  • the output hldO of the NAND gate 352 is inverted by inverter 354 to produce output hld ⁇ _b.
  • Circuit 303B has a NAND gate 356 that receives Bka ⁇ 1 > and Bkb ⁇ 1 >.
  • the output of the NAND gate 356 is connected to an input of another NAND gate 358 that also receives the previously referenced InvalidjD.
  • the output hld1 of the NAND gate 358 is inverted by inverter 360 to produced output hld1_b.
  • these circuits 303A,303B provide a data holding function to keep the previous state of lnk_is and lnk_os respectively when two links access the same bank at the same time, accidentally and when a single link attempts to access both banks simultaneously (as signalled by lnvalid_b).
  • lnvalid_b For circuit 303A, if both of the inputs Bka ⁇ 0> and Bkb ⁇ 0> have 'zero' states or one of inputs has 'zero' state, the outputs hldO and hld ⁇ _b have high and low state, respectively.
  • the outputs hldO and hld ⁇ _b have low and high state, respectively. This occurs if both links are trying to access BankO. This is a hold state that also occurs if the same link is attempting to access both banks as indicated by the lnvalid_b input.
  • the hldO and hld ⁇ _b outputs are used by hold logic 306A to hold Inkjs to a previous value as described in further detail below.
  • circuit 303B if Bka ⁇ 1 > and Bkb ⁇ 1 > both have 'zero' states or one of inputs has 'zero' state, the outputs hld1 and hld1_b have high and low state, respectively. Similarly, if both Bka ⁇ 1 > and Bkb ⁇ 1> both have 'one' states, the outputs hld1 and hld1_b have low and high state, respectively. This occurs if both links are trying to access Banki . This is a hold state that also occurs if the same link is attempting to access both banks as indicated by the lnvalid_b input. The hldO and hld ⁇ _b outputs are used by hold logic 306B to hold lnk_os to a previous value as described in further detail below. 76181-35
  • Switch logic 304A, 304B functions to control the logic as a function of the link id.
  • link id is zero so that the output of inverter 402 is high and enables NAND gate 380.
  • Bka ⁇ 0>, actually, BK0 ⁇ 0> becomes the input source of Ink is.
  • link id is high and this enables NAND gate 388 such that Bka ⁇ 1>, actually BK1 ⁇ 1 >, becomes the input source of lnk_is.
  • the operation of switching logic 304A, 304B can be summarized as follows:
  • NAND 388 output affects the result of 'Lnkjs'.
  • NAND 380 logically does not have any influence. The result is bank 1 access from link 1 -> link inside (304A).
  • -> BkO ⁇ 1 > is logically connected to the NAND 392 as one of inputs.
  • the result isbank 1 access from link 0 -> link outside (304B).
  • Switch logic 304A has a first NAND gate 380 that receives Bka ⁇ 0> and the inverted linkjd.
  • the output of NAND gate 380 is connected as an input to NAND gate 382.
  • the second input of NAND gate 382 comes from the output of a NAND gate 388 forming part of switch logic 304B described below.
  • the overall output of switch logic 304A is labelled aaO.
  • Switch logic 304B has a first NAND gate 388 that receives Bka ⁇ 1 > and the linkjd. The output of NAND gate 388 is connected as an input to NAND gate 382 76181-35
  • Logic 304B also includes a second NAND gate 390 that has three inputs: Bkb ⁇ 1 >, slink_b and link_id.
  • the output of NAND gate 390 is input to a third NAND gate 392 having a second input received from the output of NAND gate 400 forming part of link recognition logic 305
  • the overall output of switch logic 304B is labelled aa1.
  • Switch logic 304A,304B functions according to the truth table in Figure 13 for two link operation and according to the truth table in Figure 14 for single link operation.
  • the output of logic 304A is referred to as aaO, while the output of logic 304B is referred to as aa1.
  • the output is either "0" meaning deselect, "1" meaning select, or "Hold” meaning maintain previous output. Note that the logic combinations not shown in Figure 13 relate to invalid cases that are prevented by invalid check logic.
  • Hold circuit 306A functions to receive the output aaO of switch logic 304A and to pass this on to the output Inkj ' s unless the hldO is low and hld ⁇ _b are high in which case lnk is holds its previous state.
  • Hold circuit 306B functions to receive the output aa1 of switch logic 304B and to pass this on to the output lnk_os unless the hldO is low and hld ⁇ _b are high in which case lnk_os holds its previous state.
  • bank selection logic 307A,307B for the read data path.
  • Logic 307A has a NAND gate 404 that receives Bka ⁇ 0> and lnvalid_b as inputs. The output of NAND gate 404 is inverted by inverter 406 to produce bk_slct ⁇ .
  • Logic 307B has a NAND gate 408 that receives Bka ⁇ 1 > and lnvalid_b as inputs. The output of NAND gate 408 is inverted by inverter 410 to produce bk_slct1.
  • the outputs bk_slct ⁇ and bk_slct1 are the Lnk_Bnk_slct ⁇ 1 :0> signals of one of the switch controllers 48,50.
  • the device elements and circuits are connected to each other as shown in the figures, for the sake of simplicity.
  • elements, circuits, etc. may be connected directly to each other.
  • elements, circuits etc. may be connected indirectly to each other through other elements, circuits, etc., necessary for operation of devices and apparatus.
  • the circuit elements and circuits are directly or indirectly coupled with or connected to each other.

Abstract

Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Description

76181-35
INDEPENDENT LINK AND BANK SELECTION
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of US Application No. 11/643,850 filed
December 22, 2006 which is a continuation-in-part of U.S. Patent Application Number 11/324,023 filed December 30, 2005 entitled "Multiple Independent Link Serial Memory", which claims the benefit of U.S. Provisional Application No. 60/722,368 filed September 30, 2005, the content of both of which is entirely incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The Invention relates to memory systems with multiple links and multiple memory banks.
BACKGROUND OF THE INVENTION
[0003] Current consumer electronic devices use memory devices. For example, mobile electronic devices such as digital cameras, portable digital assistants, portable audio/video players and mobile terminals continue to require mass storage memories, preferably non-volatile memory with ever increasing capacities and speed capabilities. Non-volatile memory and hard-disk drives are preferred since data is retained in the absence of power, thus extending battery life.
[0004] While existing memory devices operate at speeds sufficient for many current consumer electronic devices, such memory devices may not be adequate for use in future electronic devices and other devices where high data rates are desired. For example, a mobile multimedia device that records high definition moving pictures is likely to require a memory module with a greater programming throughput than one with current memory technology. Unfortunately, there is a problem with signal quality at such high frequencies, which sets a practical limitation on the operating frequency of the 76181-35
memory. The memory communicates with other components using a set of parallel input/output (I/O) pins, the number of which is implementation specific. The I/O pins receive command instructions and input data and provide output data. This is commonly known as a parallel interface. High speed operation may cause communication degrading effects such as cross-talk, signal skew and signal attenuation, for example, which degrades signal quality.
[0005] In order to incorporate higher density and faster operation on system boards, there are two design techniques: serial interconnection configurations and parallel interconnection configurations such as multi-drops. These design techniques may be used to overcome the density issue that determines the cost and operating efficiency of memory swapping between a hard disk and a memory system. However, multi-drop configurations have a shortcoming relative to the serial interconnection configurations. For example, if the number of drops in a multi-drop memory system increases, then as a result of loading effect of each pin, delay time also increases so that the total performance of the multi-drop memory system is degraded. This is due to the wire resistor-capacitor loading and the pin capacitance of the memory device. A serial link in a device such as a memory device may utilize a single pin input that receives all address, command, and data serially. The serial link may provide a serial interconnection configuration to control command bits, address bits, and data bits effectively through the configuration. The devices in the configuration may be memory devices, for example, dynamic random access memories (DRAMs), static random access memories (SRAMs) and Flash memories.
SUMMARY OF THE INVENTION
[0006] Methods and systems are provided for use in a memory system with multiple memory banks and multiple links. The systems allow read and write access from any of the links to any of the banks, but circuitry is provided to prevent invalid access attempts. There is an invalid access attempt when there is simultaneous or 76181-35
overlapping read or write access to the same bank from multiple links. There is an invalid access attempt when there is simultaneous or overlapping read or write access to multiple banks from the same link. Some implementations feature a common circuitry that is used to perform switching for every link, thereby simplifying manufacture. With such implementations, each instance of the switching circuitry is configured to function in a particular manner that reflects its position within the overall system.
[0007] According to one broad aspect, the invention provides a memory system comprising: a plurality of memory banks; a plurality of link controllers each link controller having at least one input for receiving control and data and having at least one output for outputting the data; for each memory bank, first switching logic for receiving the at least one output for each link controller, and for passing on the at least one output of only one of the link controllers to the memory bank; for each link controller, second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller; and switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
[0008] In some embodiments, the first switching logic comprises a plurality of switching elements for a corresponding plurality of outputs of each of the link controllers.
[0009] In some embodiments, the second switching logic comprises a single switching element for receiving a serial output from each of the memory banks.
[0010] In some embodiments, the plurality of memory banks consist of two memory banks and the plurality of link controllers consist of two link controllers. 76181-35
[0011] in some embodiments, the switch controller logic comprises: a respective switch controller for each memory bank.
[0012] In some embodiments, the switch controllers have substantially identical circuit implementations, wherein each switch controller comprises: link recognition logic for receiving an instruction that the switch controller is to operate according to a selected one of a plurality of possible positions for the switch controller in the system.
[0013] In some embodiments, the plurality of memory banks consist of a first memory bank and a second memory bank and the switch controller logic consists of a first link controller and a second link controller, and wherein the plurality of possible positions for the switch controller in the system comprises: a first position in which the switch controller controls the first switching logic for the first bank and controls the second switching logic for the first link controller; and a second position in which the switch controller controls the first switching logic for the second bank and controls the second switching logic for the second link controller.
[0014] In some embodiments, the memory system further comprises: an input for selecting single link operation; wherein upon assertion a single link operation through said input, the memory system operates as if there is only one link controller.
[0015] In some embodiments, the memory system further comprises: invalid check logic for receiving bank selection outputs from each of the link controUers and for determining if there is simultaneous or overlapping access to multiple banks by the same link controller, and if so generating an invalidity signal.
[0016] In some embodiments, each switch controller further comprises: a hold circuit for holding previous control outputs in the event of simultaneous or overlapping access to multiple banks by the same link controller and in the event of simultaneous or overlapping access by multiple links to the same bank.
- A - 76181-35
[0017] In some embodiments, each switch controller is operable to generate outputs comprising: link bank select signals for selecting which link outputs that are to be passed on to the bank; and bank select signals for selecting which bank outputs are to be passed on to the link controller.
[0018] In some embodiments, each link controller comprises: an input buffer for receiving incoming command and data; serial to parallel register for converting incoming command and data to parallel form; and command interpreter control logic for interpreting incoming commands.
[0019] In some embodiments, each link controller is operable to output bank select signals for the switch controller logic.
[0020] According to another broad aspect, the invention provides a method comprising: receiving a plurality of inputs; outputting a plurality of outputs; selectably passing signals received on the plurality of inputs to memory bank inputs of a plurality of memory banks; selectably passing signals received from memory bank outputs to the plurality of outputs; and controlling the selectably passing signals received on the plurality of inputs to memory bank inputs and the selectably passing signals received from memory bank outputs to the plurality of outputs to prevent simultaneous or overlapping access from multiple inputs to the same memory bank, and to prevent simultaneous or overlapping output from multiple banks to the same output.
[0021] In some embodiments, selectably passing signals received on the plurality of inputs to memory bank inputs of a plurality of memory banks comprises: for a given access from a given input of the plurality of inputs to a given memory bank of the plurality of memory banks, connecting the given memory bank to receive signals from the given input.
[0022] In some embodiments, the method selectably passing signals received from memory bank outputs to the plurality of outputs comprises: for a given memory 76181-35
bank and a given bank, connecting the output of given memory bank to send signals towards the given output.
[0023] In some embodiments, the controlling is performed by a plurality of identical switch controllers, the method further comprising: configuring each of the plurality of identical switch controllers to behave in a manner specific to their position within an overall memory system.
[0024] In some embodiments, the method further comprises: upon occurrence of an invalid access attempt, either simultaneous or overlapping access from multiple inputs to the same memory bank or simultaneous or overlapping output from multiple banks to the same output comprises, maintaining a previous access state.
[0025] In some embodiments, the method further comprises: detecting invalid access attempts by examining bank select signals forming part of each of the plurality of inputs.
[0026] In some embodiments, the plurality of inputs and the plurality of outputs comprise a respective at least one input and a respective at least one output for each of a plurality of link controllers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
Figure 1 is a block diagram of a multiple independent serial link memory system;
Figure 2 is a detailed block diagram showing control and data signalling for a multiple independent serial link memory system; 76181-35
Figures 3 through 6 show various valid memory access configurations for the system of Figure 2;
Figure 7 is a block diagram showing details of the link controllers of Figure 2;
Figure 8 shows a set of simultaneous link accesses with different banks that are valid;
Figure 9 shows two examples of linked bank accesses that are not valid;
Figure 10 shows switching elements for control and data, and for read data;
Figure 11 A is a block diagram showing the use of a linkJD to configure switch controllers;
Figure 11 B is a block diagram showing the interconnection of bank select signals between link controllers and switch controllers;
Figure 12 is a detailed block diagram of a switch controller;
Figure 13 is a truth table of part of the logic of Figure 12 while operating in a two link mode; and
Figure 14 is a truth table of part of the logic of Figure 12 while operating in a single link mode.
DETAILED DESCRIPTION
[0028] An MISL (Multiple Independent Serial Link) memory system has a set of links and a set of memory banks, and has a feature that enables accessing any bank from any link port. Referring to Figure 1 , shown is a conceptual block diagram of two MISL memory systems. A first example is generally indicated at 30 and depicts a dual 76181-35
port configuration. There are two links, LinkO 10, and linki 12, and there are two banks, BankO 18 and Banki 20. There is switching logic 16 interconnecting the links 10,12 and the banks 18,20. Control logic is indicated at 14. The switching logic 16 can interconnect LinkO 10 to either of BankO 18 or Banki 20 as indicated at 24. Similarly, the switching logic 16 can interconnect Linki 12 to either of BankO 18 or Banki 20 as indicated at 26. A single port configuration is indicated at 32. This is generally the same as the dual port configuration 30 except the second link Linki 12 is not used.
[0029] To deal with the case of the dual link configuration of MlSL described above, circuits are provided that ensure that the two link ports can access the two banks for read and write operations so as to prevent invalid access conditions, such as simultaneous access to one bank from both links. Control signals and data use a path determined by a bank address and the accessed link port for the accessed bank.
[0030] In the illustrated example, there are two links 10,12 and two banks 18,20.
Subsequent examples also assume that there are two banks and two links. However, more generally, there may be any plural number of links and any plural number of banks. It is to be appreciated that variations and modifications of the features disclosed herein may be contemplated for implementations employing any appropriate number of links and any appropriate number of banks.
[0031] Embodiments of the invention described below support the following features:
1. prevention of simultaneous access to the same bank from multiple link ports;
2. single link access as an optional feature;
3. short switch path from link control to bank control block;
4. same logic implementation for each link control block; 7618-<-35
5. previous bank access is maintained when the same bank is subsequently accessed from different link port; and
6. separate logic for link to bank access (write and control signals) and bank to link access (read data).
However, it is to be understood that some implementations might support only a subset of these features. More generally, implementations may support any number of these features.
[0032] Figure 2 shows an example of the connections between links and banks with several switches that corresponds with the two link, two bank example of Figure 1. In this example, two banks 18,20 are connected to two independent links LinkO 10 and Linki 12 through switches 40,42,44,46 under control of switch controllers 48,50.
[0033] The connections illustrated in Figure 2 include the following for control:
a control input Bnk0<1 :0> 49 connected as an input to switch controllers 48,50 from LinkO 10 for functioning as a bank select control;
a Lnk_is_BnkO_ctrl_enable 53 from switch controller 48 to switch 40 that enables control, address and data from LinkO to be applied to BankO;
a Lnk_os_BnkO_ctrl_enable 60 from switch controller 48 to switch 40 that enables control, address and data from Linki to be applied to BankO;
a Lnk0_Bnk_slct<1 :0> output 64 from switch controller 48 to switch 42 this is used to select a bank when read related operation is performed from page buffer to link logic block for LinkO;
a control input Bnk1<1 :0> 51 connected as an input to switch controllers 48,50 from Linki 12 for functioning as a bank select control; 76181-35
a Lnk_is_Bnk1_ctrl_enable 63 from switch controller 50 to switches 44 that enables control, address and data from Link1 to be applied to Banki ;
a Lnk_os_Bnk1_ctrl_enable 65 from switch controller 50 to switches 44 that enables control, address and data from LinkO to be applied to Banki ; and
a Lnk1_Bnk_slct<1 :0> output 66 from switch controller 50 to switch 46 used to select a bank when read related operation is performed from page buffer to link logic block for Link1.
[0034] For the purpose of this description, each bank has an "inside" link and an
"outside" link. For this implementation, the inside link of a given bank is the link having a corresponding position to the bank, and the outside link is the remaining link. Thus, the inside link for BankO is LinkO, and the outside link for BankO is Linki . The inside link for Banki is Link1 , and the outside link for Banki is LinkO. In the above labelling scheme, "Lnk_is" refers to a so-called "inside link" , and "Lnk_os" refers to the so-called "outside link".
[0035] The switch controllers 48,50 receive the control inputs 49,51 , and produce the control outputs Lnk_is_BnkO_ctrl_enable 53, Lnk_os_BnkO_ctrl_enable 60, Lnk0_Bnk_s!ct<1 :0> 64, Lnkjs_Bnk1_ctrl_enable 63, Lnk_os_Bnk1_ctrl_enable 65, Lnk1_Bnk_slct<1 :0> 66 in such a manner as to prevent prohibited combinations of link/bank accesses. Specifically, the two links are not permitted to access the same bank during overlapping time intervals, and the switch controllers 48, 50 operate to prevent this.
[0036] The data connections illustrated in Figure 2 include the following data paths for read operation:
a BankO output 60 shown connected to each of switches 42,46; this output may be a parallel output, for example 4,8 or 16 bits depending on a particular design, with parallel to conversion being performed in the Link blocks; alternatively, if there is a 76181-35
buit-in parallel to serial converter in BankO for read access, then this output may be a serial output; the remainder of this description assumes it is a 8-bit parallel output;
a Banki output 62 shown connected to each of switches 42,46; similar comments apply with respect to this output as described above for output 62;
a connection 67 interconnecting switch 42 and LinkO 10; and
a connection 68 interconnecting switch 46 and Linki 12.
[0037] The connections illustrated in Figure 2 include the following for control and write operation:
a plurality of outputs 70 from LinkO 10 that are each connected to a respective switching element of switch 40, and a respective switching element of switch 44;
a plurality of outputs 72 from Linki 12 that are each connected to a respective switching element of switch 40 and a respective switching element of switch 44;
a respective output from each switching element of switch 40 connected to BankO 10, the outputs collectively indicated at 74; and
a respective output from each switching element of switch 44 connected to Banki 12, the outputs collectively indicated at 76.
[0038] In operation, commands are received at LinkO 10 and Linki 12 , and each command will be associated with one of the banks. For LinkO 10, the selected bank is indicated at Bnk0<1 :0> 49 and this is propagated to switch controllers 48,50 while for Linki 12, the selected bank is indicated at Bnk1 <1 :0> 51 and this also is propagated to switch controllers 48,50. The switch controllers 48,50 operate to prevent contention for the same bank by multiple links. An access attempt that is does not result in contention 76181-35
for the same bank by multiple links is referred to as a valid access attempt. A detailed circuit for preventing invalid attempts is described further below.
[0039] In some embodiments, to switch the two links between the two banks effectively without performance degradation due to the additional logic paths, data transferring is carried out after serial data to parallel conversion through designated registers in each link 10,12 to produce the sets of outputs 70,72. An example of a detailed implementation showing the serial to parallel conversion will be described later with reference to Figure 7.
[0040] With reference to Figure 2, various access scenarios will now be described. The access scenarios described below include LinkO to BankO access, LinkO to Banki access, Linki to Banki access, and Linki to BankO access.
[0041] During a valid access attempt by LinkO 10, if BankO 18 is selected, then the switch controller 48 will control switches 40 such that outputs 70 of LinkO are propagated to BankO 18 thereby establishing write data path and control path. Switch controller 48 will control switch 42 such that the output 60 from BankO 18 is propagated along output 67 to LinkO 10 thereby establishing read data path.
[0042] During a valid access attempt by LinkO 10, if Banki 20 is selected, then the switch controller 50 will control switches 44 such that outputs 70 of LinkO 10 are propagated to Banki thereby establishing write data path and control path. Switch controller 50 will control switch 42 such that the output 62 from Banki 20 is propagated along output 67 to LinkO 10 thereby establishing read data path.
[0043] During a valid access attempt by Linki 12, if Banki 20 is selected, then the switch controller 50 will control switches 44 such that outputs 72 of Linki 12 are propagated to Banki 20 thereby establishing write data path and control path. Switch controller 50 will control switch 46 such that the output 62 from Banki 20 is propagated along output 68 to Linki 12 thereby establishing read data path. 76181-35
[0044] During a valid access attempt by Linki 12, if BankO 18 is selected, then the switch controller 48 will control switches 40 such that outputs 72 of Linki 12 are propagated to BankO thereby establishing write data path and control path. Switch controller 50 will control switch 46 such that the output 60 from BankO 18 is propagated along output 68 to Linki 12 thereby establishing read data path.
[0045] The various access scenarios described above are specific to the implementation shown in Figure 2. Note that additional access scenarios might be possible if additional banks and/or links are present. Access scenarios may differ for different implementations. Figures 3 through 6 will be used to describe various access scenarios for an alternative implementation. In each figure, the control signals discussed previously are shown, namely:
Lnk0_Bank_slct<0> for LinkO,
LnkO_Bank_slct<1 > for each LinkO,
Lnk1_Bank_slct<0> for Linki ,
Lnk1_Bank_slct<1 > for each Linki ,
Lnk_is_BnkO_ctrl_enable,
Lnk_os_BnkO_ctrl_enable,
Lnk_is_Bnk1_ctrl_enable, and
Lnk_os_Bnk1_ctrl_enable.
The various access scenarios described below include LinkO to BankO access, LinkO to Banki access, Linki to Banki access, and Linki to BankO access.
[0046] With reference to Figure 3, shown is another example of LinkO to BankO access. Only LinkO control signals are involved in switching multiplexer between LinkO 76181-35
and BankO. For this example, LinkO access to BankO access is an inside operation that does not need any signals from outside. The link select Lnkjs_BnkO_ctrl_enable is enabled to allow data and control inputs from LinkO to be passed on to BankO and LnkO_Bnk_slct<O> transitions to a high state thereby selecting BankO for read operations until a new command is asserted.
[0047] With reference to Figure 4, there is a switch of the connection of Banki from Linki to LinkO so that the high transition of Lnk_os_Bnk1_ctrl_enable occurs after obtaining bank information from SIPO (link 0 port). Instead of Linki connections, LinkO control signals are transferred to Banki via the switches placed between Banki and Link! Lnk_os_BnkO_ctrl_enable transitions to high to enable data and control inputs from LinkO to be passed to Banki , and LnkO_Bnk_slct<1 > transitions to high to select Banki for read access.
[0048] With reference to Figure 5, shown is another example of Linki to Banki access. The case of Linki and Banki is similar to the LinkO and BankO example described with reference to Figure 3. Without control and data path switching between LinkO (or Linki ) and Banki (BankO), all switches placed in the middle of Banki and Linki pass data and control them to Banki . Lnk_is_Bnk1_ctrl_enable transitions to high enable data and control inputs from Linki to be passed to Banki , and Lnk1_Bnk_slct<1> transitions to high to select Banki for read access.
[0049] With reference to Figure 6, shown is another example of Linki to BankO access. For this example, there is a switch of the connection of BankO from LinkO to Linki so that the high transition of Lnk_os_BnkO_ctrl_enable occurs after obtaining bank information from SIPO (link 0 port). Instead of LinkO connections, Linki control signals are transferred to BankO via the switches placed between BankO and LinkO. Lnk_os_Bnk_ctrl_enable transitions to high to enable data and control inputs from Linki to be passed to BankO, and Lnk1_Bnk_slct<1 > transitions to high to select BankO for read access. 76181-35
[0050] For the output result of a read operation, global data lines <7:0> are used to send data from the Page buffer to Link! Lnk_os_BnkO_ctrl_enable transitions to high to enable data and control inputs from Linki to be passed on to BankO, and Lnk_bnk_slct<0> transitions to high to select BankO for read access.
[0051] Referring now to Figure 7, an example of a detailed implementation for some of the functionality of Figure 2 will be described. Again, LinkO 10, Linki 12, BankO 18 and Banki 20 are shown . Switches 40,44 (individual switching elements are shown in Figure 2) interconnect the links 10,12 to the banks 18,20 and are controlled by switch controllers 48,50. The outputs 70 of LinkO 10 are connected to both switches 40,44, and the outputs 72 of Link1 are connected to both switches 40,44. In the example of Figure 7, a control output 92 from LinkO 10 is input to switch controller 48, and a control output 94 from Linki 12 is input to switch controller 50. LinkO 10 has input buffers 80, serial data capture registers 82 that allows serial to parallel conversion, and command interpreter control logic 84. Similarly, Linki 12 has input buffers 86, serial data capture registers 88, and command interpreter control logic 90.
[0052] In order to catch the bank address from a SlP (Serial Input Port) (not shown) and generate the switch control signals described above, prior to the command assertion, a bank address is input first with a DN (device Number) to select which device (assuming a serial interconnected memory system). Based on the bank address, each link transfers data bits to a selected bank address bit. Switch logic delay is not negligible in the 2 banks and 2 links system. However, due to the timing margin between serial to parallel conversion at registers 82, the delay is hidden while input data is being latched consecutively. The command decoding in the command interpreter control logic 84 is performed after latching a bank address and making relevant control signals of switch logic so that any race timing issue between switch control signals and input data of switches does not occur. The switch logic can be varied according to the logic implementation. In the specific circuits described herein, 2-input NANDs are used to perform a multiplexing function. 76181-35
[0053] The different links should have valid different bank access when two links are used without timing difference. This is shown by way of example in Figure 8 where there is no timing difference between accesses to two banks. A first example is generally indicated at 800. In this example, there is valid simultaneous access by LinkO to BankO and Linki to Banki followed by valid simultaneous access by Linki to BankO and LinkO to Bank! A second example is generally indicated at 802. In this example, there is valid simultaneous access by Linki to BankO and LinkO to Banki followed by valid simultaneous access by Linki to Banki and LinkO to BankO. Another invalid access state occurs when there is simultaneous access to the same bank from two links. Figure 9 shows an example of such an invalid access. In an example generally indicated at 900, both links are simultaneously attempting to access BankO. In an example generally indicated at 901 , both links are simultaneously attempting to access Banki .
[0054] Banks are physically separated with dedicated logic blocks that activate the word line and bit line paths. Independent operations are achieved with flexible link and bank connections. Valid and invalid determination is made as a function of timing difference at the two links as shown in Figure 9. If there is some difference between the timing of link operations for the same bank (i.e. not simultaneous as was the case with the examples of Figure 8), then the first access is allowed, and the subsequent access is invalid and is ignored. The timing difference may be varied by PVT (Process / Voltage / Temperature). In some implementations, a timing difference of at least 2 cycles is used to ensure the valid operation of the first input streams from any link input port. The timing difference is implementation specific.
[0055] In summary, when there is a sequential access to the same bank from two links, the first access is valid, and the second is invalid. Figure 9 shows an example of this, generally indicated at 902. There is a first valid access from Linki to BankO followed by a later invalid access from LinkO to BankO. 76181-35
[0056] In Figure 10, generally indicated at 101 is an example of a single switching element in switch 40 or switch 44. The switching element 101 has a first NAND gate 100 that receives an input ln_A and also receives the link select signal lnk_is_Bnki_ctrl_enable (i=0 for switches controlled by switch controller 48 and i = 1 for switching elements controlled by switch controller 50). Switching element 101 has a second NAND gate 102 that receives an input ln_B from Linki also receives the link select signal Lnk_os_Bnki_ctrl_enable (i=0 for switches controlled by switch controller 48 and i = 1 for switching elements controlled by switch controller 50). For switching elements controlled by switch controller 48, i=0, so ln_A is an input from LinkO and ln_B is an input from Linki . For switching elements controlled by switch controller 50, i=1 , so ln_A is an input from Linki and ln_B is an input from LinkO. The outputs of the two NAND gates 100,102 are input to a third NAND gate 104 which combines them to produce switch output outO 105. For switching elements controlled by switch 48, outO 105 is connected as an input to BankO. For switching elements controlled by switch 50, outO 105 is connected as an input to Banki .
[0057] In Figure 10, generally indicated at 103 is an example of a single switching element in switch 42 or switch 46. The switching element 103 has a first NAND gate 110 that receives an input BankOJn from BankO and also receives the bank select signal Lnk_Brιk_slct<0>. Switching element 103 has a second NAND gate 102 that receives an Bank1_in from Banki and also receives the bank select signal Lnk__Bnk_slct<1>. For switching elements controlled by switch controller 48, Lnk0_Bnk_slct<1 :0> are in respect of LinkO. For switching elements controlled by switch controller 50, Lnk1_Bnk_slct<1 :0> are in respect of Linki . The outputs of the two NAND gates 110,112 are input to a third NAND gate 114 which combines them to produce switch output out1 115. For switch 48, outO 115 is connected as an input to LinkO. For switch 50, outO 115 is connected as an input to Linki .
[0058] The switching elements 101 ,103 are shown with specific logic components. In other implementations, the switching elements 101 ,103 have 76181-35
alternative logic components that in combination achieve similar functionality. The switching elements 101 ,103 need not have any NAND gates. Other implementations are possible.
[0059] In some embodiments, the system has an additional input, for example an extra input pin, that enables identical switch controller circuitry to be implemented for the switch control logic for all of the links. Such an input can be used to identify the link the switch control logic is functioning for.
[0060] A summary of the logic for the purpose of illustrating link id functionality is indicated at 400 in Figure 11A. Again LinkO 12, Linki 12, BankO 18, Banki 20, and switches 42,44,46,48 are shown. Switch controller 48 is with a link id connected to
VSS, thereby selecting it to function as the switch controller for LinkO 10. The switch controller 48 produces Lnk0_Bnk_slct<1 :0>, and produces Lnk_is_BnkO_ctrl_enable and Lnk_os_Bnk01_ctrl enable [p24]. Switch controller 50 is with a linkjd connected to VDD, thereby selecting it to function as the switch controller for Linki 12. The switch controller 50 produces Lnk1_Bnk_slct<1 :0>, and produces Lnk_os BnkO_ctrl_enable and Lnk_is_Bnk1_ctrl enable.
[0061] In some embodiments, the system has an additional input, for example an extra input pin, that allows a selection between single link configuration and multiple link configuration. In a specific example included in Figure 12 below, a Singlejink input is implemented. If single link configuration is used, this pin is high. For multiple link configuration (dual link in the illustrated example), the pin is set low.
[0062] An example of the logic for the purpose of illustrating bank select interconnections is indicated at 401 in Figure 11 B. Again LinkO 10, Linki 12, BankO 18, Banki 20, and switches 42,44,46,48 are shown. As described previously, LinkO outputs bank select signals Bk0<1 :0> 49 while Linki outputs bank select signals Bk1<1 :0> 51. Each switch controller 48,50 has inputs for receiving Bkb<1 :0> and Bka<1 :0>. The suffix 'a' and 'b' of 'Bka<1 :0>' and 'Bkb<1 :0>' have the meaning of two different links, 76181-35
and <1 :0> is bank number, with <0> -> BankO and <1 > -> Banki . The connection of these inputs to the bank select outputs of LinkO, Linki is done according to the location of the logic system. Specifically, for switch controller 48 (linkO side), Bka<1 :0>=Bk0<1 :0> and Bkb<1 :0>=Bk1 <1 :0>. For switch controller 50 (linki side), the connections are reversed such that Bka<1:0>=Bk1<1:0> and Bkb<1 :0>=Bk0<1 :0>.
[0063] A detailed diagram of an example implementation of the switch controllers is shown in Figure 12. It is to be understood that this implementation is very specific for example purposes only. The particular example illustrated is designed to allow it to function as a switch controller for the switches connected to/from any of the banks. The circuitry generally indicated at 300 generates four control signals Inkjs, lnk_os, bk_slctθ and bk_slct1 , which are used to open and close the switches that connect the links to the banks. These switches may be implemented using any appropriate logic circuitry, for example circuitry having 2-input NAND gates as shown in Figure 10.
[0064] Link recognition logic 305 receives a linkjd input. For example, if this logic system is included in linkO block, it is 'zero', otherwise, it is 'one'. This logic allows the circuit 300 to recognize which link control block contains itself when switch control operation starts. The link recognition logic has an inverter 402 that is connected to receive the linkjd input. The output of inverter 402 is input to one input of a three input NAND gate 400. The other inputs of NAND gate 400 include the single link output slink_b, and Bkb<0>.
[0065] In operation, when the circuit 300 is configured to operate as switch controller 48 of Figure 2 (link_id= 0), output signals lnk_is and lnk_os function as Lnk_is_BnkO_ctrl_enable and lnk_os_BnkO_ctrl_enable for switch controller 48, and the other two outputs bk_slctθ and bk_slct1 are the Lnk0_Bnk_slct<1 :0> signals of switch controller 48. When the circuit 300 is configured to operate as switch controller 50 of
Figure 2 (link id=1 ), the two output signals Inkjs and lnk_os function as
LnkjsJ3nk1_ctrl_enable and Lnk_os_Bnk1_ctrl_enable for switch controller 50, and 76181 -35
the other two outputs bk_slctθ and bk_slct1 are the Lnk1_Bnk_slct<1 :0> signals switch controller 50.
[0066] The circuit includes a first Invalid check logic 301. This logic is provided to prevent two bank access through one link at the same time. The circuit has first NAND gate 370 that has inputs Bka<0> AND Bka<1 >, and a second NAND gate 372 that has inputs Bkb<0> AND Bkb<1 >. The outputs of the two NAND gates 370,372 are input to a third NAND gate 374 the output of which is inverted with an inverter to produce an invalid_b output.
[0067] In operation, the Invalid check logic 301 produces an lnvalid_b output that is high if both banks are selected by one link. Specifically, if Bka<0> AND Bka<1 > are both high meaning both banks are selected by the same link, then the InvalidjD output is high indicating an invalid condition; if Bkb<0> AND Bkb<1> are both high meaning both banks are selected by the same link, then the lnvalid_b output is high indicating an invalid condition.
[0068] If two inputs (Bka<0> and Bka<1 >) or (Bkb<0> or Bkb<1 >) have zero states, this means there is no operation since there is no selection of banks for the given link.
[0069] Single Link configuration circuit 302 is provided to allow the previously discussed selection of single link operation. Even though two links are more efficient for a two-bank memory system, single link also is supported as an available configuration of the memory system with the circuit described. If single link configuration is used, 'singlejink' signal becomes high and 'slink_b' will have a low state. When 'slink_b' has a low state, ink_os' becomes low and only 'Inkjs' has a valid state according to the bank address. For the two link configuration, 'singlejink' has a low state such that both outputs 'Inkjs' and 1nk_os' are valid. In the illustrated example, single link configuration circuit 302 is simply an inverter 403. 76181-35
[0070] The circuit 300 has a second Invalid check logic that includes functionality indicated at 303A and 303B. Circuit 303A has a NAND gate 350 that receives Bka<0> and Bkb<0>. The output of the NAND gate 350 is connected to an input of another NAND gate 352 that also receives the previously referenced Invalidja. The output hldO of the NAND gate 352 is inverted by inverter 354 to produce output hldθ_b. Circuit 303B has a NAND gate 356 that receives Bka<1 > and Bkb<1 >. The output of the NAND gate 356 is connected to an input of another NAND gate 358 that also receives the previously referenced InvalidjD. The output hld1 of the NAND gate 358 is inverted by inverter 360 to produced output hld1_b.
[0071] In operation, these circuits 303A,303B provide a data holding function to keep the previous state of lnk_is and lnk_os respectively when two links access the same bank at the same time, accidentally and when a single link attempts to access both banks simultaneously (as signalled by lnvalid_b). For circuit 303A, if both of the inputs Bka<0> and Bkb<0> have 'zero' states or one of inputs has 'zero' state, the outputs hldO and hldθ_b have high and low state, respectively. If both of the inputs Bka<0> and Bkb<0> have 'one' states, the outputs hldO and hldθ_b have low and high state, respectively. This occurs if both links are trying to access BankO. This is a hold state that also occurs if the same link is attempting to access both banks as indicated by the lnvalid_b input. The hldO and hldθ_b outputs are used by hold logic 306A to hold Inkjs to a previous value as described in further detail below.
[0072] In circuit 303B, if Bka<1 > and Bkb<1 > both have 'zero' states or one of inputs has 'zero' state, the outputs hld1 and hld1_b have high and low state, respectively. Similarly, if both Bka<1 > and Bkb<1> both have 'one' states, the outputs hld1 and hld1_b have low and high state, respectively. This occurs if both links are trying to access Banki . This is a hold state that also occurs if the same link is attempting to access both banks as indicated by the lnvalid_b input. The hldO and hldθ_b outputs are used by hold logic 306B to hold lnk_os to a previous value as described in further detail below. 76181-35
[0073] Switch logic 304A, 304B functions to control the logic as a function of the link id. In case of LinkO, link id is zero so that the output of inverter 402 is high and enables NAND gate 380. When this is the case, then Bka<0>, actually, BK0<0>, becomes the input source of Ink is. On the other hand, in the case of Linki , link id is high and this enables NAND gate 388 such that Bka<1>, actually BK1 <1 >, becomes the input source of lnk_is. The operation of switching logic 304A, 304B can be summarized as follows:
• LinkO position (linkjd = 0) -> NAND 380 output affects the result of 'Inkjs', NAND 388 logically does not have any influence. The result is bank 0 access from link 0 -» link inside ( 304A).
• Linki position (linkjd - 1 ) -» NAND 388 output affects the result of 'Lnkjs'. NAND 380 logically does not have any influence. The result is bank 1 access from link 1 -> link inside (304A).
• LinkO position (linkjd = 0) -» NAND 400 output affects the result of 'lnk_os'. -> Bk1 <0> is logically connected to the NAND 392 as one of inputs. The result is bank 0 access from link 1 -> link outside (304B).
• Linki position (linkjd = 1 ) -> NAND 390 output affects the result of 'lnk_os'. -> BkO<1 > is logically connected to the NAND 392 as one of inputs. The result isbank 1 access from link 0 -> link outside (304B).
[0074] Switch logic 304A has a first NAND gate 380 that receives Bka<0> and the inverted linkjd. The output of NAND gate 380 is connected as an input to NAND gate 382. The second input of NAND gate 382 comes from the output of a NAND gate 388 forming part of switch logic 304B described below. The overall output of switch logic 304A is labelled aaO.
[0075] Switch logic 304B has a first NAND gate 388 that receives Bka<1 > and the linkjd. The output of NAND gate 388 is connected as an input to NAND gate 382 76181-35
forming part of switch logic 304A described above. Logic 304B also includes a second NAND gate 390 that has three inputs: Bkb<1 >, slink_b and link_id. The output of NAND gate 390 is input to a third NAND gate 392 having a second input received from the output of NAND gate 400 forming part of link recognition logic 305 The overall output of switch logic 304B is labelled aa1.
[0076] Switch logic 304A,304B functions according to the truth table in Figure 13 for two link operation and according to the truth table in Figure 14 for single link operation. In Figure 13, the top half 1300 of the table represents behaviour for Linkjd = 0, while the bottom half 1302 of the table represents behaviour for Linkjd = 1. The output of logic 304A is referred to as aaO, while the output of logic 304B is referred to as aa1. The output is either "0" meaning deselect, "1" meaning select, or "Hold" meaning maintain previous output. Note that the logic combinations not shown in Figure 13 relate to invalid cases that are prevented by invalid check logic.
[0077] Hold circuit 306A functions to receive the output aaO of switch logic 304A and to pass this on to the output Inkj's unless the hldO is low and hldθ_b are high in which case lnk is holds its previous state. Similarly, Hold circuit 306B functions to receive the output aa1 of switch logic 304B and to pass this on to the output lnk_os unless the hldO is low and hldθ_b are high in which case lnk_os holds its previous state.
[0078] Finally, there is bank selection logic 307A,307B for the read data path.
This logic is used to select which bank is now connected to the accessed link control block. Logic 307A has a NAND gate 404 that receives Bka<0> and lnvalid_b as inputs. The output of NAND gate 404 is inverted by inverter 406 to produce bk_slctθ. Logic 307B has a NAND gate 408 that receives Bka<1 > and lnvalid_b as inputs. The output of NAND gate 408 is inverted by inverter 410 to produce bk_slct1.
[0079] In operation, other when there is an invalid state signalled by Invalid check logic 301 , Bka<0> and Bka<1 > logic values are passed by the circuit to 'bk_slctθ' and 76181-35
'bk_slct1 ' output ports. The outputs bk_slctθ and bk_slct1 are the Lnk_Bnk_slct<1 :0> signals of one of the switch controllers 48,50.
[0080] In the embodiments described above, the device elements and circuits are connected to each other as shown in the figures, for the sake of simplicity. In practical applications of the present invention, elements, circuits, etc. may be connected directly to each other. As well, elements, circuits etc. may be connected indirectly to each other through other elements, circuits, etc., necessary for operation of devices and apparatus. Thus, in actual configuration, the circuit elements and circuits are directly or indirectly coupled with or connected to each other.
[0081] The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims

76181-35WHAT IS CLAIMED IS:
1. A memory system comprising:
a plurality of memory banks;
a plurality of link controllers each link controller having at least one input for receiving control and data and having at least one output for outputting the data;
for each memory bank, first switching logic for receiving the at least one output for each link controller, and for passing on the at least one output of only one of the link controllers to the memory bank;
for each link controller, second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller; and
switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
2. The memory system of claim 1 wherein the first switching logic comprises a plurality of switching elements for a corresponding plurality of outputs of each of the link controllers.
3. The memory system of any one of claims 1 and 2 wherein the second switching logic comprises a single switching element for receiving a serial output from each of the memory banks.
4. The memory system of any one of claims 1 to 3 wherein the plurality of memory banks consist of two memory banks and the plurality of link controllers consist of two link controllers. 76181-35
5. The memory system of any one of claims 1 to 4 wherein the switch controller logic comprises:
a respective switch controller for each memory bank.
6. The memory system of claim 5 wherein the switch controllers have substantially identical circuit implementations, wherein each switch controller comprises:
link recognition logic for receiving an instruction that the switch controller is to operate according to a selected one of a plurality of possible positions for the switch controller in the system.
7. The memory system of claim 6 wherein the plurality of memory banks consist of a first memory bank and a second memory bank and the switch controller logic consists of a first link controller and a second link controller, and wherein the plurality of possible positions for the switch controller in the system comprises:
a first position in which the switch controller controls the first switching logic for the first bank and controls the second switching logic for the first link controller; and
a second position in which the switch controller controls the first switching logic for the second bank and controls the second switching logic for the second link controller.
8. The memory system of any one of claims 1 to 7 further comprising:
an input for selecting single link operation;
wherein upon assertion a single link operation through said input, the memory system operates as if there is only one link controller.
9. The memory system of any one of claims 1 to 8 further comprising: 76181-35
invalid check logic for receiving bank selection outputs from each of the link controllers and for determining if there is simultaneous or overlapping access to multiple banks by the same link controller, and if so generating an invalidity signal.
10. The memory system of claim 5 wherein each switch controller further comprises:
a hold circuit for holding previous control outputs in the event of simultaneous or overlapping access to multiple banks by the same link controller and in the event of simultaneous or overlapping access by multiple links to the same bank.
11. The memory system of claim 5 wherein each switch controller is operable to generate outputs comprising:
link bank select signals for selecting which link outputs that are to be passed on to the bank; and
bank select signals for selecting which bank outputs are to be passed on to the link controller.
12. The memory system of any one of claims 1 to 11 wherein each link controller comprises:
an input buffer for receiving incoming command and data;
serial to parallel register for converting incoming command and data to parallel form; and
command interpreter control logic for interpreting incoming commands.
13. The memory system of any one of claims 1 to 12 wherein each link controller is operable to output bank select signals for the switch controller logic.
14. A method comprising: 76181-35
receiving a plurality of inputs;
outputting a plurality of outputs;
selectably passing signals received on the plurality of inputs to memory bank inputs of a plurality of memory banks;
selectably passing signals received from memory bank outputs to the plurality of outputs; and
controlling the selectably passing signals received on the plurality of inputs to memory bank inputs and the selectably passing signals received from memory bank outputs to the plurality of outputs to prevent simultaneous or overlapping access from multiple inputs to the same memory bank, and to prevent simultaneous or overlapping output from multiple banks to the same output.
15. The method of claim 14 wherein selectably passing signals received on the plurality of inputs to memory bank inputs of a plurality of memory banks comprises:
for a given access from a given input of the plurality of inputs to a given memory bank of the plurality of memory banks, connecting the given memory bank to receive signals from the given input.
16. The method of any one of claims 14 to 15 selectably passing signals received from memory bank outputs to the plurality of outputs comprises:
for a given memory bank and a given bank, connecting the output of given memory bank to send signals towards the given output.
17. The method of any one of claims 14 to 16 wherein the controlling is performed by a plurality of identical switch controllers, the method further comprising: 76181-35
configuring each of the plurality of identical switch controllers to behave in a manner specific to their position within an overall memory system.
18. The method of any one of claims 14 to 17 further comprising:
upon occurrence of an invalid access attempt, either simultaneous or overlapping access from multiple inputs to the same memory bank or simultaneous or overlapping output from multiple banks to the same output comprises, maintaining a previous access state.
19. The method of claim 18 further comprising:
detecting invalid access attempts by examining bank select signals forming part of each of the plurality of inputs.
20. The method of any one of claims 14 to 19 wherein the plurality of inputs and the plurality of outputs comprise a respective at least one input and a respective at least one output for each of a plurality of link controllers.
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