WO2008085391A2 - Stacked packages - Google Patents
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- WO2008085391A2 WO2008085391A2 PCT/US2007/026095 US2007026095W WO2008085391A2 WO 2008085391 A2 WO2008085391 A2 WO 2008085391A2 US 2007026095 W US2007026095 W US 2007026095W WO 2008085391 A2 WO2008085391 A2 WO 2008085391A2
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- microelectronic
- subassembly
- microelectronic element
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Definitions
- the present invention generally relates to stacked microelectronic packages and more particularly relates to stacked microelectronic packages fabricated at the wafer level and to methods of making such packages .
- Semiconductor chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.
- the substrate materials used •• for packaging semiconductor chips are selected for their compatibility with the processes used to form the packages. For example, during solder or other bonding operations, intense heat may be applied to the substrate. Accordingly, metal lead frames have been used as substrates. Laminate substrates have also been used to package microelectronic devices. Such substrates may include two to four alternating layers of fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. Optionally, heat resistive compounds such as bismaleimide triazine (BT) may be added to such laminate substrates . [0005] Tapes have been used as substrates to provide thinner microelectronic packages. Such tapes are typically provided in the form of sheets or rolls of sheets.
- Microelectronic packages also include wafer level packages, which provide a package for a semiconductor component that is fabricated while the die are still in a wafer form. The wafer is subject to a number of additional process steps to form the package structure and the wafer is then diced to free the individual die, with no additional fabrication steps being necessary. Wafer level processing provides an advantage in that the cost of the packaging processes are divided among the various die on the wafer, resulting in a very low price differential between the die and the component. Furthermore, the package footprint can be substantially similar to the die size, resulting in very efficient utilization of area on a printed circuit board (PCB) to which the die will eventually be attached. As a result of these features, die packaged in this manner are commonly referred to as wafer level chip scale package (WLCSP) .
- WLCSP wafer level chip scale package
- the present invention is directed to a microelectronic assembly that includes a first microelectronic element having a first rear surface.
- the assembly further includes a second microelectronic element having a second rear surface.
- the second microelectronic element is attached to the first microelectronic element so as to form a stacked package.
- the first rear surface of the first microelectronic element faces toward the second rear surface of the second microelectronic element.
- the assembly includes at least one bridging element.
- the first microelectronic element and second microelectronic element each have a front surface and a plurality of contacts exposed there at.
- the at least one bridging element extends between the plurality of contacts of the first microelectronic element and the plurality of contacts of the second microelectronic element so as to electrically connect the two.
- the first microelectronic element includes a first edge and a second edge extending from the front surface to the rear surface of the first microelectronic element. And the at least one bridging element is disposed outside of the first edge and second edge.
- a plurality of traces exposed on the respective front surfaces of the first microelectronic element and second microelectronic element may be included as well. At least some of the plurality of traces extend from at least some of the plurality of contacts on the first microelectronic element to the at least one bridging element and at least some of the plurality of traces extend from at least some of the plurality of contacts of the second microelectronic element to the at least one bridging element.
- the microelectronic assembly in certain embodiments includes an adhesive that attaches the first microelectronic element to the second microelectronic element.
- the first microelectronic element includes a first edge and a second edge.
- the at least one bridging element is positioned between the first edge and the second edge.
- the second microelectronic element may have a first edge and a second edge such that the at least one bridging element is positioned between the first edge and the second edge of the second microelectronic element.
- the first microelectronic element includes a plurality of vias extending from the front face to the rear face and the at least one bridging element is disposed within at least one of the plurality of vias.
- the assembly may further include a third microelectronic element having a front face and a rear face and a fourth microelectronic element having a rear face.
- the third and fourth microelectronic elements are attached such that the rear face of the third microelectronic element faces toward the rear face of the fourth microelectronic element.
- the third microelectronic element is also attached to the first second microelectronic element such that the front face of the third microelectronic element faces toward the front surface of the second microelectronic element.
- the present invention is also directed to a method of assembling a stacked microelectronic assembly comprising the steps of forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements.
- the rear faces of the first subassembly and second subassembly confront one another.
- a plurality of contacts exposed at a front face of the first subassembly is connected to a plurality of contacts exposed at a front face of the second subassembly.
- the first subassembly and second subassembly each may include saw lanes that are aligned during the step of forming the microelectronic assembly. And the method may include dicing through the saw lanes of the first and second subassemblies so as so form individual stacked units . At least some of the plurality of microelectronic elements of the first subassembly and the second subassembly have traces that extend from respective contacts to the saw lanes of the respective first and second subassemblies such that after the dicing step the traces are exposed.
- FIG. IA is a top view of a subassembly according to one embodiment of the present invention.
- FIG. IB is a cross-sectional view of the subassembly of FIG. IA;
- FIG. 2 is a cross-sectional view of a plurality of subassemblies attached to one another to form a stacked assembly;
- FIG. 3 is a cross-sectional view of the stacked assembly of FIG. 2 after the stacked assembly has been diced into individual units;
- FIG. 4 is a cross-sectional view of individual units of FIG. 3 stacked upon each other.
- FIG. 5A is a top view of a subassembly according to one embodiment of the present invention.
- FIG. 5B is a cross-sectional view of the subassembly
- FIG. 6 is a cross-sectional view of the subassembly of FIG. 5B at a later stage of assembly
- FIG. 7 is a cross-sectional view of a plurality of subassemblies of FIG. 6 attached to one another to form a stacked assembly;
- FIG. 8 is a cross-sectional view of the stacked assembly of FIG. 7 after the stacked assembly has been diced into individual units;
- FIG. 9 is a cross-sectional view of individual units of FIG. 8 stacked upon each other.
- FIGS. IA and IB illustrate a top view and a cross-sectional view, respectively of a wafer or first subassembly 10.
- a portion of a first wafer or subassembly 10 includes a plurality of microelectronic elements 12, each positioned side by side and adjacent to one another.
- the first subassembly preferably includes numerous rows of microelectronic elements 12 aligned along an X-axis and a Y-axis in various columns and rows.
- the microelectronic elements 12 are formed integral with one another using conventional semiconductor process techniques.
- the present invention is also applicable to reconstituted wafers .
- Each microelectronic element 12 includes a front face 14 and an oppositely- facing rear face 16.
- the microelectronic elements 12 also include first edges 18, second edges 20, third edges 19 and fourth edges 21, all of which extend from the front faces 14 to the rear faces 16 of the microelectronic elements 12.
- a first edge 18 of one microelectronic element 12 is attached to a second edge 20 of a second and adjacent microelectronic element 12.
- the microelectronic elements 12 positioned within the middle of the first subassembly 10 are bordered by an adjacent microelectronic element 12 at all four edges, as shown in FIG. IA.
- the microelectronic elements 12 positioned at a first end 11, a second end 13, a third end 15 or a fourth end 17 of the wafer have at least one edge unencumbered by an additional microelectronic element.
- edges are depicted in the drawings for clarity of illustration, in practice the edges may not be visible. Rather, at this stage the edges or strips where adjacent microelectronic elements 12 contact one another are saw lanes or strips where the wafer can be cut without damaging the individual microelectronic elements. For instance, as shown in FIG. IB, second edge 20' of microelectronic element 12 ' abuts first edge 18" ' of microelectronic element 12 ' • and forms a saw lane 23. Similarly, throughout the wafer 10, saw lanes 23 are located at positions where microelectronic elements 12 abut one another.
- the first wafer/subassembly 10 may include any number of microelectronic elements including as little as one or as many as is desirable.
- Each of the microelectronic elements 12 in subassembly 10 also include a plurality of contacts 22 exposed at their respective front faces 16. Further, the contacts 22 are attached to traces 24 that extend from the contacts 22 to an edge of the microelectronic element.
- microelectronic 12' includes contact 22' and trace 24', which extends from contact 22 ' to first edge 18 ' of the microelectronic element 12 ' .
- microelectronic element 12 ' ' includes contact 22 ' ' and trace 24 ' ' , which extends from contact 22 ⁇ ' to second edge 20' ' of microelectronic element 12 ' ' .
- traces 24' and 24' ' actually are a unitary structure extending between contacts 22' and 22 ' ⁇ of adjacent microelectronic elements 12', 12".
- traces 24' and 24 ' ⁇ meet at the attachment point of microelectronic elements 12' and 12", or at saw lane 23'.
- the first subassembly 10 is positioned under a second wafer/subassembly 1OA.
- the second subassembly 1OA is similarly constructed to the first subassembly 10, and thus like elements will be given similar character references unless otherwise specified.
- the second assembly 1OA is inverted such that contacts 22A exposed at front faces 14A of microelectronic elements 12A face in an opposite direction as opposed to contacts 22 of subassembly 10.
- the rear faces 16A of subassembly 1OA face towards the rear faces 16 of subassembly 10.
- the microelectronic elements 12 are aligned with the microelectronic elements 12A.
- the respective first, second, third, and fourth edges of each of the microelectronic elements 12,12A are aligned along respective longitudinal axes.
- the respective saw lanes 23, 23A of each of the subassemblies 10, 1OA are also aligned.
- the stacked assembly 30 consists of a plurality of microelectronic elements 12, 12A, oriented and aligned in various rows and columns .
- an adhesive layer 32 is positioned between the rear faces 16, 16A and adhered thereto.
- the adhesive layer 32 is preferably comprised of an adhesive, epoxy or the like, and once cured, maintains a connection between the two subassemblies 10, 1OA, such that the subassemblies are attached to one another and form stacked assembly 30.
- the two subassemblies 10, 1OA may be attached using other methods that do not involve the use of an adhesive such as directly attaching the rear faces 16 of the subassembly 10 to the rear faces 16A of the second subassembly 1OA. For example, solder bonding, eutectic bonding, diffusion bonding or other known bonding procedures can be used.
- the stacked assembly 30 is diced to form individual stacked units 34 using a mechanical cutting instrument not shown in the figures. Examples of such a mechanical cutting instrument can be found in U.S. Patent Nos . 6,646,289 and 6,972,480, the disclosures of which are hereby incorporated by reference herein.
- the stacked assembly 30 is diced at locations that correspond to saw lanes 23, 23A of the individual subassemblies 10, 1OA and various edges of the microelectronic elements 12, 12A. Since the ends of the traces 24, 24A that are remote from the contacts 22, 22A are positioned within the saw lanes 23, 23A, the dicing of the stacked assembly 30 causes these ends to become exposed.
- Each individual stacked unit 34 includes a microelectronic element 12A disposed above a microelectronic element 12 and attached thereto by adhesive layer 32.
- the respective front faces 14, 14A of the microelectronic elements 12, 12A face in opposite directions as do the contacts 22, 22A of respective microelectronic elements.
- the individual stacked units 34 include a first side wall 36 and a second side wall 38 that extend between the front faces 14, 14A of the microelectronic elements 12 and 12A. Adjacent to both side walls 36, 38 are the ends of the traces 24, 24A that are exposed after the dicing process.
- Bridging elements such as trace bridges 40 are then formed on the side walls 36 and 38.
- a trace bridge 40 extends from a trace 40 across either side wall 36 or side wall 38 to a trace 24A, and thereby electrically interconnects the two traces disposed on opposite faces of individual stacked units 34.
- the traces bridges extend about the edges of the microelectronic elements as well as the edges of the adhesive layer 32 that is exposed as a result of the dicing process.
- a contact 22 is in electrical communication with a contact 22A.
- a dielectric layer 41 may be disposed onto the exposed edges of the microelectronic elements and adhesive layer so as to electrically isolate the trace bridges from the bodies of the microelectronic elements if desired.
- a mass of conductive material 42 may be deposited onto contacts 22 so as to enable the individual stacked units 34 to be electrically connected to a substrate such as a circuit panel and the like.
- the mass of conductive material 42 may be a ball of solder or similar material .
- individual stacked units 34 and 34 ' may be stacked one upon another with contacts of individual stacked unit 34 being electrically connected to contacts of individual stacked unit 34' as shown in FIG. 4.
- the contacts 50 exposed at a lower surface 52 of stacked unit 34 is aligned with the contacts 50' exposed at the top surface 54' of stacked unit 34'
- the contacts 50 and 50' may then be electrically connected using a mass of conductive material 56 such as solder or attached to one another using other methods known to those in the art.
- a subassembly 110 including a plurality of microelectronic elements 112 may ⁇ be provided as shown in FIGS. 5A and 5B.
- Subassembly 110 is similarly constructed as subassembly 10 and includes many of the same features. For this reason, like elements will be given similar character references unless otherwise specified.
- the microelectronic elements 112 of subassembly 110 include a front face 114 and an oppositely-facing rear face 116.
- each microelectronic element 112 includes a first edge 118, a second edge 120, a third edge 119 and a fourth edge 121 extending between the front face 114 and rear face 116.
- Each microelectronic element 112 also includes a plurality of contacts 122 exposed at their respective front face 114.
- the subassembly 110 is illustrated having four rows and three columns of microelectronic elements, the number of microelectronic elements may be as little as one and as many as is desirable.
- the subassembly 110 is subjected to a mechanical cutting process that bores vias 130 through each of the microelectronic elements 112.
- the vias extend from a rear face 116 to a front face 114 of each of the microelectronic elements.
- each of the vias 130 is preferably aligned with a contact 122 exposed on the front face 114 of each of the microelectronic elements 112 such that the contacts 122 are not only exposed at the front faces 114 but also at the rear faces 116.
- the vias 130 are formed, they are filled with a conductive material 131 such as a metal.
- the conductive material 131 may for instance be formed from copper or a copper/gold alloy.
- a stacked assembly 132 may be assembled by attaching the first subassembly 110 to a second subassembly 110'.
- the second subassembly HO 1 is similarly constructed as subassembly 110 and like features are described using similar character references unless otherwise specified.
- the second subassembly 110' is inverted such that the rear faces 116' of the microelectronic elements 112' of the second subassembly face toward the rear faces 116 of microelectronic elements 112.
- the saw lanes 123 of subassembly 110 are aligned with the saw lanes 123' of second subassembly 110' and the vias 130, 130' of each of the subassemblies are also aligned.
- the vias 130 By aligning the vias 130 to the vias 130', the contacts 122 of the microelectronic elements 112 are aligned with the contacts 122' of the second subassembly and the conductive material 131, 131 ' of each of the vias 130, 130' are brought proximate to one another.
- a second conductive material 137 may be utilized.
- masses of the second conductive material 137 such as solder, are disposed in and around the vias 130 proximate the rear faces 116 of the microelectronic elements 112 and in contact with the conductive material 131 contained within the vias.
- the subassembly 110 is then brought proximate with the second subassembly 110 ' such that the second conductive material 137 is proximate vias 130' and in contact with the conductive material 131' of the second subassembly. As shown in FIG.
- this configuration causes the contacts 122 to be electrically connected to contacts 122' through the various conductive materials disposed within the vias 130, 130' and thus the conductive material 131, 131' act as electrical bridges between contacts 122, 122'.
- a back fill such as encapsulant material 134 or an adhesive may be positioned between the two subassemblies 110, 110' to provide additional rigidity to the stacked assembly 132.
- the conductive material 131 of subassembly 110 may be directly adhered to the conductive material 131 ' of the second subassembly 110'.
- the conductive material 130, 130' is copper
- the copper in each via 130, 130' is reflowed and allowed to contact the copper in an aligned via.
- the copper in adjacent vias 130, 130' forms, not only an attachment area between the subassemblies but also an electrical connection between contacts 122, 122'.
- the stacked assembly 132 is now ready to be diced into individual stacked units 140.
- a similar mechanical instrument (not shown in the figures) described previously is brought proximate the saw lanes 123, 123' of each of the subassemblies 110, HO 1 .
- the mechanical tool is passed through the stacked assembly 132 at positions that correspond to the saw lanes 123, 123' thereby dissecting the stacked assembly into individual stacked units 140.
- a mass of solder 142 or other conductive material may be disposed on exposed contacts 122 or 122' so as to enable the individual stacked units 140 to be attached to a substrate such as a circuit panel.
- the stacked assembly 132 may also be attached to a circuit panel without having to dice the assembly into individual units if desired.
- individual stacked units 140 and 140' may be stacked one upon another with the contacts of individual stacked unit 140 being electrically connected to contacts of individual stacked unit 140'.
- the contacts 150 exposed at a lower surface 152 of stacked unit 140 are aligned with the contacts 150' exposed at the top surface 154' of stacked unit 140'
- the contacts 150 and 150' may then be electrically connected using a mass of conductive material 156 such as solder or attached to one another using other methods known to those in the art .
- the entire assembly 160 may be attached to a substrate such as circuit panel 170 illustrated in FIG. 9, which includes conductive pads 172.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009544043A JP5567346B2 (en) | 2006-12-28 | 2007-12-20 | Stacked package |
KR1020097015570A KR101454332B1 (en) | 2006-12-28 | 2007-12-20 | Stacked packages |
EP07867901.6A EP2097925B1 (en) | 2006-12-28 | 2007-12-20 | Stacked packages |
CN2007800504745A CN101595562B (en) | 2006-12-28 | 2007-12-20 | Stacked packages |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/648,172 | 2006-12-28 | ||
US11/648,172 US7952195B2 (en) | 2006-12-28 | 2006-12-28 | Stacked packages with bridging traces |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008085391A2 true WO2008085391A2 (en) | 2008-07-17 |
WO2008085391A3 WO2008085391A3 (en) | 2008-09-12 |
Family
ID=39488194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/026095 WO2008085391A2 (en) | 2006-12-28 | 2007-12-20 | Stacked packages |
Country Status (6)
Country | Link |
---|---|
US (2) | US7952195B2 (en) |
EP (1) | EP2097925B1 (en) |
JP (1) | JP5567346B2 (en) |
KR (1) | KR101454332B1 (en) |
CN (1) | CN101595562B (en) |
WO (1) | WO2008085391A2 (en) |
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Also Published As
Publication number | Publication date |
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KR20090128376A (en) | 2009-12-15 |
EP2097925B1 (en) | 2020-11-04 |
US20110230013A1 (en) | 2011-09-22 |
CN101595562B (en) | 2011-09-21 |
CN101595562A (en) | 2009-12-02 |
US7952195B2 (en) | 2011-05-31 |
US20080157323A1 (en) | 2008-07-03 |
JP2010515259A (en) | 2010-05-06 |
EP2097925A2 (en) | 2009-09-09 |
US8349654B2 (en) | 2013-01-08 |
JP5567346B2 (en) | 2014-08-06 |
WO2008085391A3 (en) | 2008-09-12 |
KR101454332B1 (en) | 2014-10-23 |
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