WO2008091742A2 - Pre-molded clip structure - Google Patents

Pre-molded clip structure Download PDF

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Publication number
WO2008091742A2
WO2008091742A2 PCT/US2008/050753 US2008050753W WO2008091742A2 WO 2008091742 A2 WO2008091742 A2 WO 2008091742A2 US 2008050753 W US2008050753 W US 2008050753W WO 2008091742 A2 WO2008091742 A2 WO 2008091742A2
Authority
WO
WIPO (PCT)
Prior art keywords
clip
semiconductor die
molding material
package
premolded
Prior art date
Application number
PCT/US2008/050753
Other languages
French (fr)
Other versions
WO2008091742A3 (en
Inventor
Erwin Victor Cruz
Maria Cristina Estacio
Original Assignee
Fairchild Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corporation filed Critical Fairchild Semiconductor Corporation
Priority to CN2008800028902A priority Critical patent/CN101595560B/en
Priority to DE112008000234T priority patent/DE112008000234T5/en
Publication of WO2008091742A2 publication Critical patent/WO2008091742A2/en
Publication of WO2008091742A3 publication Critical patent/WO2008091742A3/en

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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Definitions

  • Some semiconductor die packages use clips to provide connections between electrical terminals in a semiconductor die and a leadframe structure that provides external connections for such packages. Clips are used in many semiconductor die packages comprising power transistors such as power MOSFETs.
  • a pick-and-place tool can be used to attach a source clip to a source region and attach gate clip to a gate region of the MOSFET in the semiconductor die.
  • a typical pick-and-place tool has a two vacuum hole design, where one vacuum hole is for holding the source clip and another vacuum hole is for holding the gate clip. The package is then molded in a molding material.
  • Embodiments of the invention address these and other problems, individually and collectively.
  • Embodiments of the invention are directed to premolded clip structures, semiconductor die packages comprising the premolded clip structures, and methods for making the same.
  • One embodiment of the invention is directed to a method comprising: obtaining a first clip and a second clip; and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface, wherein the first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and wherein a premolded clip structure is thereafter formed.
  • Another embodiment of the invention is directed to a premolded clip structure comprising: a first clip comprising a first surface; a second clip comprising a second surface; and a molding material coupled to the first clip and the second clip, wherein the first surface and second surface are exposed through the molding material.
  • Another embodiment of the invention is directed to a semiconductor die package comprising: a premolded clip structure comprising a first clip comprising a first surface, a second clip comprising a second surface, and a molding material coupled to the first clip and the second clip, wherein the first and second surfaces are exposed through the molding material; and a semiconductor die comprising a first die surface and a second die surface, and a first electrical terminal and a second electrical terminal at the first die surface, wherein the first surface is electrically coupled to the first electrical terminal and the second surface is electrically coupled to the second electrical terminal.
  • FIG. 1 shows a side cross-sectional view of a semiconductor die package.
  • FIG. 2(a) shows a perspective view of a premolded clip structure.
  • FIG. 2(b) shows a side schematic view of a semiconductor die comprising a vertical MOSFET.
  • FIG. 3 shows a perspective view of a semiconductor die package comprising two dice.
  • FIG. 4 shows a top view of the die package in FIG. 3.
  • FIG. 5 shows a portion of the die package in FIG. 3, without a clip structure.
  • FIGS. 6-7 show exemplary process flows.
  • FIGS. 8-9 show portions of a clip structure that can be partially etched.
  • FIG. 10 shows a semiconductor die package according to another embodiment of the invention.
  • like numerals designate like elements.
  • Embodiments of the invention are directed to pre-molded clip structures, methods for making pre-molded clip structures, semiconductor die packages including the pre-molded clip structures, and methods for making the semiconductor die packages.
  • the pre-molded clip structures according to embodiments of the invention allow gate and source connections to be made simultaneously to electrical terminals (e.g., a source terminal and a gate terminal) in a single die or multiple dice, since clips that couple to those terminals are premolded together with a molding material. This can result in more uniform solder connections, since the relative positions of such clips can be fixed and consistent prior to when they are attached to the semiconductor die.
  • electrical terminals e.g., a source terminal and a gate terminal
  • a pre-molded clip structure can be made with solderable contact areas defined via a molding process or via a combination of molding and partial-etching (e.g., half-etching) processes to allow compatibility with stamped clip options.
  • a partial or half-etching process can define solderable connection sites at predetermined locations. This can result in optimum RDSon performance and can facilitate the flow of a molding material under a clip connection while improving clip locking within the die package.
  • Clip bonding processes using the premolded clip structure can advantageously use one pick-and-place step to provide connections for a single die or multiple dice.
  • the premolded clip structure may use a 0.203 mm (or larger) sheet of metal (e.g., copper), etched or stamped according to a desired design of the solderable part, and may then be molded.
  • the overall thickness of the premolded clip structure may be around 0.3 mm, or greater.
  • a premolded clip structure according to an embodiment of the invention can be used in any suitable type of semiconductor die package including a wireless MLP (micro- lead package) structure.
  • a clip frame For a wireless MLP type package, it is also possible to design a clip frame so that it is a high density matrix frame ( ⁇ 400 units per strip for a 70 mm frame width). Hence, it is possible to lower the cost of a clip frame and thereby compensate for any added cost resulting from additional clip molding and sawing processes. Another advantage of this concept is its adaptability for creating multiple chip modules (MCM).
  • MCM multiple chip modules
  • source and gate clip connections can be defined on a frame via a molding process instead of laying out complicated clip designs.
  • FIG. 1 shows a side, cross-sectional view of a semiconductor die package 100 according to an embodiment of the invention.
  • the package 100 comprises a semiconductor die 110 which is attached to a leadframe structure 124, and is a wireless MLP -type package.
  • the leadframe structure 124 comprises a die attach portion 124(a) (which may be a drain lead structure) comprising a die attach surface 124(a)-l proximate to the die 110. It is electrically coupled to a drain in a MOSFET in the die 110 An exterior leadframe surface 124(a)-2 may be opposite to the die attach surface 124(a)-l.
  • the leadframe structure 124 also comprises a source lead structure 124(b) including a first end portion 124(b)-l, an intermediate portion 124(b)-2, and a second end portion 124(b)-3. Portions 124(b)-l, 124(b)-2, and 124(b)-3 are in a stepped configuration.
  • the leadframe structures 124 may be made of any suitable conductive material including plated and unplated metals. Suitable materials may include copper.
  • the semiconductor die package 100 also comprises a premolded clip structure 130.
  • the premolded clip structure 130 comprises a first clip 118 and a first molding material 128 around at least a portion of the first clip 118.
  • the first molding material 128 may comprise any suitable material including an epoxy molding material.
  • the first clip 118 and any other clips may be made of any suitable material including copper.
  • the first clip 118 and any other clips may be plated or unplated.
  • the first clip 118 may be a source clip and may comprise a first portion 118(a) which is electrically and mechanically coupled to a source region of the semiconductor die 110 using a conductive material 122 (e.g., a conductive adhesive) such as solder or a conductive epoxy, as well as a second portion 118(b), and an intermediate portion 118(c).
  • the first portion 118(a) may comprise a die attach surface 118(a)-l and an opposite surface 118(a)-2.
  • the second portion 118(b) is mechanically and electrically coupled to the source lead structure 124 using a conductive adhesive 129 such as solder or a conductive epoxy.
  • the second portion 118(b) may comprise a lead attach surface 118(b)-l and an opposite surface 118(b)-2.
  • the intermediate portion 118(c) is between the first portion 118(a) and the second portion 118(b) of the first clip 118.
  • the intermediate portion 118(c) may have been formed by an etching process, and is therefore thinner than the first portion 118(a) and the second portion 118(b) of the first clip 118.
  • the first clip 118 has a number of partially etched regions 118(d) (sometimes referred to as "half-etched" when about half of the thickness of the clip is etched away). As shown in FIG. 1, the molding material 128 fills the regions that were etched away to lock the first clip 118 into the molding material 128.
  • a second molding material 114 which may be the same or different than the molding material 128 in the premolded clip structure 130, may cover some or all of the premolded clip structure 130, and the semiconductor die 110.
  • the second molding material 114 may also cover a portion of the leadframe structure 124. Because the second molding material 114 and the first molding material 128 are formed in separate processes, an interface may be formed between the first molding material 128 and the second molding material 114 in some embodiments.
  • the second molding material 114 does not extend beyond the lateral edges of the drain lead structure 124(a) and the source lead structure 124.
  • the packages could include leads which extend beyond the lateral edges of the second molding material 114.
  • the surface 124(a)-2 and the exterior surface corresponding to the second end portion 124(b)-3 are exposed by the second molding material 114. The exposed surfaces may be mounted to conductive lands on a circuit substrate (not shown) such as a circuit board.
  • FIG. 2(a) shows the underside of the premolded clip structure 130.
  • the cross- sectional view of the premolded clip in FIG. 1 may be along the line P-P.
  • the die attach surface 118(a)-l of the first clip 118 and the lead attach surface 118(b)-l of the first clip are exposed through the molding material 128.
  • FIG. 2(a) also shows a die attach surface 136(a)-l and a lead attach surface
  • the second clip 136 may electrically connect a gate lead in the previously described leadframe structure and a gate region in the previously described die using a conductive adhesive such as solder or a conductive epoxy.
  • the second clip 136 may also comprise a first portion including the die attach surface 136(a)-l, a second portion including the lead attach surface 136(b)-l, and an intermediate portion (covered by the molding material 128) that is thinner than the first portion and the second portion.
  • the first clip 118 and the second clip 136 are separated from each other and are electrically isolated from each other by the molding material 128.
  • the molding material 128 binds the first clip 118 and the second clip 136 together so that the first clip 118 and the second clip 136 can be mounted on to a corresponding source region and a corresponding gate region in a semiconductor die together in one step and using vacuum tool element that includes one vacuum hole.
  • This is unlike conventional processes where separate vacuum holes for a separated first clip and a separated second clip would be needed. Consequently, embodiments of the invention provide for more efficient processing and can also provide for more accurate alignment of the first and second clips 118, 136 when they are bonded to a semiconductor die, since they already in fixed positions relative to each other during bonding.
  • FIG. 2(b) shows a schematic cross-section of a die comprising a vertical power MOSFET.
  • the die 110 comprising a source region S and a gate region G at one surface of the die 118, and a drain region D at the opposite surface of the die 110.
  • VDMOS transistors include VDMOS transistors and vertical bipolar transistors.
  • a VDMOS transistor is a MOSFET that has two or more semiconductor regions formed by diffusion. It has a source region, a drain region, and a gate. The device is vertical in that the source region and the drain region are at opposite surfaces of the semiconductor die.
  • the gate may be a trenched gate structure or a planar gate structure, and is formed at the same surface as the source region. Trenched gate structures are preferred, since trenched gate structures are narrower and occupy less space than planar gate structures.
  • the current flow from the source region to the drain region in a VDMOS device is substantially perpendicular to the die surfaces.
  • the semiconductor dice could alternatively include other vertical devices such as resistors as well as bipolar junction transistors.
  • FIG. 3 shows a perspective view of a semiconductor die package 200 comprising two dice 210 within a single package.
  • the semiconductor die package 200 comprises two first clips 218 and two second clips 236.
  • the two first clips may be source clips coupled to source regions in the semiconductor dice 210.
  • the two second clips 236 may be gate clips coupled to the gate regions in the semiconductor dice 210.
  • the semiconductor dice 210 may be mounted on a leadframe structure 224.
  • a first molding material 228 may couple the first clips 218 and the second clips 236 together, and they may form a premolded clip structure 230.
  • a second molding material is not shown in FIG. 3.
  • two dice and two clips per die are shown in this example, it is understood that embodiments of the invention may include more than two dice and/or more than two clips per dice in other embodiments of the invention.
  • FIG. 4 shows a top view of the die package 200 shown in FIG. 3.
  • FIG. 5 shows a perspective view of the semiconductor die package shown in
  • conductive adhesives 228, 222(g), and 222(s) are shown. They may include a conductive adhesive 222(g) on a gate region and a conductive adhesive 222(s) on a source region of the semiconductor die 210.
  • FIG. 6 shows a flowchart illustrating a method according to an embodiment of the invention.
  • solder paste or a solder wire
  • solder paste may be used to attach a semiconductor die to a leadframe structure (step 502).
  • solder paste can be dispensed or screen printed on the surface of the semiconductor die opposite the leadframe structure (step 504).
  • the previously described premolded clip structure may be attached to the semiconductor die (step 506).
  • the clip premolding process (step 501) can occur using the previously described first molding material and first and second clips.
  • the first and second clips may be in an array of clips.
  • the array of premolded clip structures may be separated by sawing or some other process (step 503).
  • a reflow process and an optional flux cleaning process can be performed (steps 508, 510).
  • a block molding process is performed (step 512) using a molding tool.
  • a second molding material is formed around at least a portion of the die, the leadframe structure, and the premolded clip structure (step 512).
  • strip marking, package sawing, and test processes are performed (steps 514, 516, 518).
  • FIG. 7 shows another flowchart illustrating another method according to an embodiment of the invention.
  • the steps in FIG. 7 and FIG. 6 are the same, except that an additional step of partially etching exposed copper is shown (step 507). This additional step can be further described with references to FIGS. 8 and 9.
  • FIGS. 8 and 9 show how copper clips in premolded clip structures 330 including a first molding material 328 can be selectively plated with metallic materials 354 such as noble metals or composite layers comprising noble metals (e.g., NiPdAu).
  • metallic materials 354 such as noble metals or composite layers comprising noble metals (e.g., NiPdAu).
  • the exposed bare copper areas 352 will later be partially or half-etched to create specific soldering sites (as in FIG. 8) or specific soldering pedestals on the clip (as in FIG. 9). These bare copper areas 352 are recessed after etching.
  • the plated NiPdAu areas 354 will protrude from the bare copper areas 352 after etching.
  • the etched copper areas 352 can facilitate mold compound flow under the clip structures 330 and can enhance clip locking during the second, block molding process with the second molding material (step 512 in FIGS. 6-7).
  • FIGS. 8 and 9 also show tie bars 350 which form pathways for volatiles that can facilitate the escape of outgas components from solder paste during soldering process.
  • FIG. 10 shows a side, cross-sectional view of a semiconductor die package like the one shown in FIG. 1.
  • the second molding material 114 does not extend beyond the top surface (including surfaces 118(a)-2, 118(b)-2) of the first clip 118, as well as a corresponding second clip (not shown).
  • This top exposed option can use a film or tape assisted molding process, where a top and bottom film is placed on areas that will not receive a molding material. The molding process can be used to ensure that molding material does not bleed on to exposed pads.
  • the package shown in FIG. 10 is thinner, and a heat sink may be placed on top of the premolded clip structure 130 to provide for improved heat dissipation.
  • premolded clip structures and semiconductor die packages described above can be used in larger modules and systems.
  • Such systems may include cellular phones, computers, servers, etc.

Abstract

A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Description

PRE-MOLDED CLIP STRUCTURE
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] NOT APPLICABLE
BACKGROUND OF THE INVENTION
[0002] Some semiconductor die packages use clips to provide connections between electrical terminals in a semiconductor die and a leadframe structure that provides external connections for such packages. Clips are used in many semiconductor die packages comprising power transistors such as power MOSFETs.
[0003] When packaging a semiconductor die comprising a power MOSFET, the semiconductor die can be attached to a leadframe structure. A pick-and-place tool can be used to attach a source clip to a source region and attach gate clip to a gate region of the MOSFET in the semiconductor die. A typical pick-and-place tool has a two vacuum hole design, where one vacuum hole is for holding the source clip and another vacuum hole is for holding the gate clip. The package is then molded in a molding material.
[0004] Although a conventional packaging method such as this one could be used to package a semiconductor die, improvements could be made. For example, it would be desirable to improve the above method so that processing efficiency is improved and so that processing costs are reduced. Also, when mounting two separate clips to a die, there can be inconsistencies when aligning the clips to the source and the gate regions in the semiconductor die.
[0005] Embodiments of the invention address these and other problems, individually and collectively.
SUMMARY OF THE INVENTION
[0006] Embodiments of the invention are directed to premolded clip structures, semiconductor die packages comprising the premolded clip structures, and methods for making the same. [0007] One embodiment of the invention is directed to a method comprising: obtaining a first clip and a second clip; and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface, wherein the first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and wherein a premolded clip structure is thereafter formed.
[0008] Another embodiment of the invention is directed to a premolded clip structure comprising: a first clip comprising a first surface; a second clip comprising a second surface; and a molding material coupled to the first clip and the second clip, wherein the first surface and second surface are exposed through the molding material.
[0009] Another embodiment of the invention is directed to a semiconductor die package comprising: a premolded clip structure comprising a first clip comprising a first surface, a second clip comprising a second surface, and a molding material coupled to the first clip and the second clip, wherein the first and second surfaces are exposed through the molding material; and a semiconductor die comprising a first die surface and a second die surface, and a first electrical terminal and a second electrical terminal at the first die surface, wherein the first surface is electrically coupled to the first electrical terminal and the second surface is electrically coupled to the second electrical terminal.
[0010] These and other embodiments of the invention are described in further detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 shows a side cross-sectional view of a semiconductor die package.
[0012] FIG. 2(a) shows a perspective view of a premolded clip structure.
[0013] FIG. 2(b) shows a side schematic view of a semiconductor die comprising a vertical MOSFET.
[0014] FIG. 3 shows a perspective view of a semiconductor die package comprising two dice.
[0015] FIG. 4 shows a top view of the die package in FIG. 3.
[0016] FIG. 5 shows a portion of the die package in FIG. 3, without a clip structure. [00171 FIGS. 6-7 show exemplary process flows.
[0018] FIGS. 8-9 show portions of a clip structure that can be partially etched.
[0019] FIG. 10 shows a semiconductor die package according to another embodiment of the invention. [0020] In the Figures, like numerals designate like elements.
DETAILED DESCRIPTION
[0021] Embodiments of the invention are directed to pre-molded clip structures, methods for making pre-molded clip structures, semiconductor die packages including the pre-molded clip structures, and methods for making the semiconductor die packages.
[0022] The pre-molded clip structures according to embodiments of the invention allow gate and source connections to be made simultaneously to electrical terminals (e.g., a source terminal and a gate terminal) in a single die or multiple dice, since clips that couple to those terminals are premolded together with a molding material. This can result in more uniform solder connections, since the relative positions of such clips can be fixed and consistent prior to when they are attached to the semiconductor die.
[0023] In some embodiments of the invention, a pre-molded clip structure can be made with solderable contact areas defined via a molding process or via a combination of molding and partial-etching (e.g., half-etching) processes to allow compatibility with stamped clip options. Put another way, a partial or half-etching process can define solderable connection sites at predetermined locations. This can result in optimum RDSon performance and can facilitate the flow of a molding material under a clip connection while improving clip locking within the die package. Clip bonding processes using the premolded clip structure can advantageously use one pick-and-place step to provide connections for a single die or multiple dice.
[0024] In some embodiments, the premolded clip structure may use a 0.203 mm (or larger) sheet of metal (e.g., copper), etched or stamped according to a desired design of the solderable part, and may then be molded. In some embodiments, the overall thickness of the premolded clip structure (including a molding material and clip structures) may be around 0.3 mm, or greater. A premolded clip structure according to an embodiment of the invention can be used in any suitable type of semiconductor die package including a wireless MLP (micro- lead package) structure.
[0025] For a wireless MLP type package, it is also possible to design a clip frame so that it is a high density matrix frame (~ 400 units per strip for a 70 mm frame width). Hence, it is possible to lower the cost of a clip frame and thereby compensate for any added cost resulting from additional clip molding and sawing processes. Another advantage of this concept is its adaptability for creating multiple chip modules (MCM).
[0026] Also, using the premolded clip approach, source and gate clip connections can be defined on a frame via a molding process instead of laying out complicated clip designs.
[0027] Conventional clip designs are unique to one or several devices with dedicated stamped and clip singulation tooling. However, with a premold clip structure, high density etched frames can be designed according to desired layout requirements while sharing the same premold set-up and saw singulation equipment.
[0028] Conventional clip designs can have difficulty making simultaneous connections on a die and more so in when multiple chips are processed. With premold clips structures, two or more chips can be connected with clips in a single step.
[0029] FIG. 1 shows a side, cross-sectional view of a semiconductor die package 100 according to an embodiment of the invention. The package 100 comprises a semiconductor die 110 which is attached to a leadframe structure 124, and is a wireless MLP -type package.
[0030] The leadframe structure 124 comprises a die attach portion 124(a) (which may be a drain lead structure) comprising a die attach surface 124(a)-l proximate to the die 110. It is electrically coupled to a drain in a MOSFET in the die 110 An exterior leadframe surface 124(a)-2 may be opposite to the die attach surface 124(a)-l. The leadframe structure 124 also comprises a source lead structure 124(b) including a first end portion 124(b)-l, an intermediate portion 124(b)-2, and a second end portion 124(b)-3. Portions 124(b)-l, 124(b)-2, and 124(b)-3 are in a stepped configuration.
[0031] The leadframe structures 124 may be made of any suitable conductive material including plated and unplated metals. Suitable materials may include copper.
[0032] The semiconductor die package 100 also comprises a premolded clip structure 130. The premolded clip structure 130 comprises a first clip 118 and a first molding material 128 around at least a portion of the first clip 118. The first molding material 128 may comprise any suitable material including an epoxy molding material. The first clip 118 and any other clips may be made of any suitable material including copper. The first clip 118 and any other clips may be plated or unplated.
[0033] The first clip 118 may be a source clip and may comprise a first portion 118(a) which is electrically and mechanically coupled to a source region of the semiconductor die 110 using a conductive material 122 (e.g., a conductive adhesive) such as solder or a conductive epoxy, as well as a second portion 118(b), and an intermediate portion 118(c). The first portion 118(a) may comprise a die attach surface 118(a)-l and an opposite surface 118(a)-2. The second portion 118(b) is mechanically and electrically coupled to the source lead structure 124 using a conductive adhesive 129 such as solder or a conductive epoxy. The second portion 118(b) may comprise a lead attach surface 118(b)-l and an opposite surface 118(b)-2.
[0034] The intermediate portion 118(c) is between the first portion 118(a) and the second portion 118(b) of the first clip 118. The intermediate portion 118(c) may have been formed by an etching process, and is therefore thinner than the first portion 118(a) and the second portion 118(b) of the first clip 118. The first clip 118 has a number of partially etched regions 118(d) (sometimes referred to as "half-etched" when about half of the thickness of the clip is etched away). As shown in FIG. 1, the molding material 128 fills the regions that were etched away to lock the first clip 118 into the molding material 128.
[0035] A second molding material 114, which may be the same or different than the molding material 128 in the premolded clip structure 130, may cover some or all of the premolded clip structure 130, and the semiconductor die 110. The second molding material 114 may also cover a portion of the leadframe structure 124. Because the second molding material 114 and the first molding material 128 are formed in separate processes, an interface may be formed between the first molding material 128 and the second molding material 114 in some embodiments.
[0036] As shown in FIG. 1, in this example, the second molding material 114 does not extend beyond the lateral edges of the drain lead structure 124(a) and the source lead structure 124. (In other embodiments, the packages could include leads which extend beyond the lateral edges of the second molding material 114.) Also, the surface 124(a)-2 and the exterior surface corresponding to the second end portion 124(b)-3 are exposed by the second molding material 114. The exposed surfaces may be mounted to conductive lands on a circuit substrate (not shown) such as a circuit board.
[0037] FIG. 2(a) shows the underside of the premolded clip structure 130. The cross- sectional view of the premolded clip in FIG. 1 may be along the line P-P. As shown in FIG. 2(a), the die attach surface 118(a)-l of the first clip 118 and the lead attach surface 118(b)-l of the first clip are exposed through the molding material 128.
[0038] FIG. 2(a) also shows a die attach surface 136(a)-l and a lead attach surface
136(b)-l corresponding to a second clip 136 which may be a gate clip. The second clip 136 may electrically connect a gate lead in the previously described leadframe structure and a gate region in the previously described die using a conductive adhesive such as solder or a conductive epoxy. Like the first clip 118, the second clip 136 may also comprise a first portion including the die attach surface 136(a)-l, a second portion including the lead attach surface 136(b)-l, and an intermediate portion (covered by the molding material 128) that is thinner than the first portion and the second portion.
[0039] In the premolded clip 130, the first clip 118 and the second clip 136 are separated from each other and are electrically isolated from each other by the molding material 128. The molding material 128 binds the first clip 118 and the second clip 136 together so that the first clip 118 and the second clip 136 can be mounted on to a corresponding source region and a corresponding gate region in a semiconductor die together in one step and using vacuum tool element that includes one vacuum hole. This is unlike conventional processes where separate vacuum holes for a separated first clip and a separated second clip would be needed. Consequently, embodiments of the invention provide for more efficient processing and can also provide for more accurate alignment of the first and second clips 118, 136 when they are bonded to a semiconductor die, since they already in fixed positions relative to each other during bonding.
[0040] FIG. 2(b) shows a schematic cross-section of a die comprising a vertical power MOSFET. The die 110 comprising a source region S and a gate region G at one surface of the die 118, and a drain region D at the opposite surface of the die 110.
[0041] Vertical power transistors include VDMOS transistors and vertical bipolar transistors. A VDMOS transistor is a MOSFET that has two or more semiconductor regions formed by diffusion. It has a source region, a drain region, and a gate. The device is vertical in that the source region and the drain region are at opposite surfaces of the semiconductor die. The gate may be a trenched gate structure or a planar gate structure, and is formed at the same surface as the source region. Trenched gate structures are preferred, since trenched gate structures are narrower and occupy less space than planar gate structures. During operation, the current flow from the source region to the drain region in a VDMOS device is substantially perpendicular to the die surfaces. In embodiments of the invention, the semiconductor dice could alternatively include other vertical devices such as resistors as well as bipolar junction transistors.
[0042] FIG. 3 shows a perspective view of a semiconductor die package 200 comprising two dice 210 within a single package. The semiconductor die package 200 comprises two first clips 218 and two second clips 236. The two first clips may be source clips coupled to source regions in the semiconductor dice 210. The two second clips 236 may be gate clips coupled to the gate regions in the semiconductor dice 210. The semiconductor dice 210 may be mounted on a leadframe structure 224.
[0043] A first molding material 228 may couple the first clips 218 and the second clips 236 together, and they may form a premolded clip structure 230. For clarity of illustration, a second molding material is not shown in FIG. 3. Although two dice and two clips per die are shown in this example, it is understood that embodiments of the invention may include more than two dice and/or more than two clips per dice in other embodiments of the invention.
[0044] FIG. 4 shows a top view of the die package 200 shown in FIG. 3.
[0045] FIG. 5 shows a perspective view of the semiconductor die package shown in
FIG. 3, without the premolded clip structure 230 on top for the dice 210. In FIG. 5, conductive adhesives 228, 222(g), and 222(s) are shown. They may include a conductive adhesive 222(g) on a gate region and a conductive adhesive 222(s) on a source region of the semiconductor die 210.
[0046] FIG. 6 shows a flowchart illustrating a method according to an embodiment of the invention. In a die attachment process, solder paste (or a solder wire) may be used to attach a semiconductor die to a leadframe structure (step 502). Then, solder paste can be dispensed or screen printed on the surface of the semiconductor die opposite the leadframe structure (step 504). Then, the previously described premolded clip structure may be attached to the semiconductor die (step 506). [0047] In a separate process, the clip premolding process (step 501) can occur using the previously described first molding material and first and second clips. The first and second clips may be in an array of clips. After the premolded clip structures are formed in an array, the array of premolded clip structures may be separated by sawing or some other process (step 503).
[0048] After a separated premolded clip structure is attached to the semiconductor die, a reflow process and an optional flux cleaning process can be performed (steps 508, 510). Then, a block molding process is performed (step 512) using a molding tool. In this step, a second molding material is formed around at least a portion of the die, the leadframe structure, and the premolded clip structure (step 512). Then, strip marking, package sawing, and test processes are performed (steps 514, 516, 518).
[0049] FIG. 7 shows another flowchart illustrating another method according to an embodiment of the invention. The steps in FIG. 7 and FIG. 6 are the same, except that an additional step of partially etching exposed copper is shown (step 507). This additional step can be further described with references to FIGS. 8 and 9.
[0050] FIGS. 8 and 9 show how copper clips in premolded clip structures 330 including a first molding material 328 can be selectively plated with metallic materials 354 such as noble metals or composite layers comprising noble metals (e.g., NiPdAu). The exposed bare copper areas 352 will later be partially or half-etched to create specific soldering sites (as in FIG. 8) or specific soldering pedestals on the clip (as in FIG. 9). These bare copper areas 352 are recessed after etching. The plated NiPdAu areas 354 will protrude from the bare copper areas 352 after etching. The etched copper areas 352 can facilitate mold compound flow under the clip structures 330 and can enhance clip locking during the second, block molding process with the second molding material (step 512 in FIGS. 6-7). FIGS. 8 and 9 also show tie bars 350 which form pathways for volatiles that can facilitate the escape of outgas components from solder paste during soldering process.
[0051] FIG. 10 shows a side, cross-sectional view of a semiconductor die package like the one shown in FIG. 1. However, in FIG. 10, the second molding material 114 does not extend beyond the top surface (including surfaces 118(a)-2, 118(b)-2) of the first clip 118, as well as a corresponding second clip (not shown). This top exposed option can use a film or tape assisted molding process, where a top and bottom film is placed on areas that will not receive a molding material. The molding process can be used to ensure that molding material does not bleed on to exposed pads. Compared to the package shown in FIG. 1 , the package shown in FIG. 10 is thinner, and a heat sink may be placed on top of the premolded clip structure 130 to provide for improved heat dissipation.
[0052] The premolded clip structures and semiconductor die packages described above can be used in larger modules and systems. Such systems may include cellular phones, computers, servers, etc.
[0053] Any of the above-described embodiments and/or any features thereof may be combined with any other embodiment(s) and/or feature(s) without departing from the scope of the invention.
[0054] The above description is illustrative and is not restrictive. Many variations of the invention will become apparent to those skilled in the art upon review of the disclosure. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the pending claims along with their full scope or equivalents.
[0055] A recitation of "a", "an" or "the" is intended to mean "one or more" unless specifically indicated to the contrary.

Claims

WHAT IS CLAIMED IS:
L A method comprising: obtaining a first clip and a second clip; and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface, wherein the first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and wherein a premolded clip structure is thereafter formed.
2. The method of claim 1 further comprising: attaching the premolded clip structure to a semiconductor die.
3. The method of claim 2 wherein the semiconductor die comprises a source region and a gate region, and wherein the first clip is a source clip that is electrically coupled to the source region and the second clip is a gate clip electrically coupled to the gate region.
4. A premolded clip structure made according to the process of claim 1.
5. The method of claim 1 wherein the first clip structure comprises a third surface opposite the first surface, and wherein the second clip comprises a fourth surface opposite the second surface, wherein the third surface and fourth surface are also exposed through the molding material.
6. The method of claim 1 further comprising: attaching the premolded clip structure to a semiconductor die; and attaching the semiconductor die to a leadframe structure.
7. The method of claim 6 wherein the molding material is a first molding material, and wherein the method further comprises molding a second molding material around the leadframe structure, the premolded clip structure, and the semiconductor die to form a semiconductor die package.
8. The method of claim 7 wherein the semiconductor die package is an MLP -type package.
9. A semiconductor die package made by the process according to claim 7.
10. A semiconductor die package made by the process according to claim 8.
11. A premolded clip structure comprising: a first clip comprising a first surface; a second clip comprising a second surface; and a molding material coupled to the first clip and the second clip, wherein the first and second surfaces are exposed through the molding material.
12. The premolded clip of claim 11 wherein the first clip is a source clip and the second clip is a gate clip.
13. A semiconductor die package comprising: a premolded clip structure comprising a first clip comprising a first surface, a second clip comprising a second surface, and a molding material coupled to the first clip and the second clip, wherein the first and second surfaces are exposed through the molding material; and a semiconductor die comprising a first die surface and a second die surface, and a first electrical terminal and a second electrical terminal at the first die surface, wherein the first surface is electrically coupled to the first electrical terminal and the second surface is electrically coupled to the second electrical terminal.
14. The semiconductor die package of claim 13 further comprising: a leadframe structure, and wherein the die is on the leadframe structure.
15. The semiconductor die package of claim 14 wherein the package is an MLP -type package.
16. The semiconductor die package of claim 13 wherein the semiconductor die comprises a vertical MOSFET.
17. The semiconductor die package of claim 14 wherein the molding material is a first molding material, and wherein the semiconductor die package further comprises a second molding material around at least a portion of the semiconductor die, the premolded clip structure, and the leadframe structure.
18. The semiconductor die package of claim 17 wherein the second molding material is the same type of molding material as the first molding material.
19. The semiconductor die package of claim 17 wherein the leadframe structure comprises copper.
20. The semiconductor die page of claim 19 wherein the semiconductor die package is an MLP type package.
PCT/US2008/050753 2007-01-24 2008-01-10 Pre-molded clip structure WO2008091742A2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI727861B (en) * 2020-07-23 2021-05-11 朋程科技股份有限公司 Chip packaging structure and method of manufacturing the same

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106501B2 (en) * 2008-12-12 2012-01-31 Fairchild Semiconductor Corporation Semiconductor die package including low stress configuration
US7768105B2 (en) 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US7683463B2 (en) * 2007-04-19 2010-03-23 Fairchild Semiconductor Corporation Etched leadframe structure including recesses
US7972906B2 (en) * 2008-03-07 2011-07-05 Fairchild Semiconductor Corporation Semiconductor die package including exposed connections
US7969018B2 (en) * 2008-07-15 2011-06-28 Infineon Technologies Ag Stacked semiconductor chips with separate encapsulations
US7898067B2 (en) * 2008-10-31 2011-03-01 Fairchild Semiconductor Corporaton Pre-molded, clip-bonded multi-die semiconductor package
US8193618B2 (en) 2008-12-12 2012-06-05 Fairchild Semiconductor Corporation Semiconductor die package with clip interconnection
US7816784B2 (en) * 2008-12-17 2010-10-19 Fairchild Semiconductor Corporation Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same
US20100164078A1 (en) * 2008-12-31 2010-07-01 Ruben Madrid Package assembly for semiconductor devices
EP2242094A1 (en) * 2009-04-17 2010-10-20 Nxp B.V. Foil and method for foil-based bonding and resulting package
US8354303B2 (en) * 2009-09-29 2013-01-15 Texas Instruments Incorporated Thermally enhanced low parasitic power semiconductor package
US20110084332A1 (en) * 2009-10-08 2011-04-14 Vishay General Semiconductor, Llc. Trench termination structure
US20110095410A1 (en) * 2009-10-28 2011-04-28 Fairchild Semiconductor Corporation Wafer level semiconductor device connector
US20110095417A1 (en) * 2009-10-28 2011-04-28 Fairchild Semiconductor Corporation Leadless semiconductor device terminal
CN102842550B (en) * 2012-08-23 2015-12-16 苏州固锝电子股份有限公司 The DFN encapsulating structure of power mosfet chip
CN102842548A (en) * 2012-08-23 2012-12-26 苏州固锝电子股份有限公司 Square flat-type power metal oxide semi-conductor (MOS) chip packaging structure
CN102842549B (en) * 2012-08-23 2015-12-16 苏州固锝电子股份有限公司 The power MOSFET package body of square flat non-pin
JP5970316B2 (en) 2012-09-26 2016-08-17 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US9478484B2 (en) 2012-10-19 2016-10-25 Infineon Technologies Austria Ag Semiconductor packages and methods of formation thereof
US9070721B2 (en) * 2013-03-15 2015-06-30 Semiconductor Components Industries, Llc Semiconductor devices and methods of making the same
CN103208474A (en) * 2013-03-22 2013-07-17 苏州固锝电子股份有限公司 Quad flat type high-power chip packing structure
US9041170B2 (en) * 2013-04-02 2015-05-26 Infineon Technologies Austria Ag Multi-level semiconductor package
US9214415B2 (en) 2013-04-11 2015-12-15 Texas Instruments Incorporated Integrating multi-output power converters having vertically stacked semiconductor chips
JP6147588B2 (en) 2013-07-01 2017-06-14 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2015076960A1 (en) * 2013-11-21 2015-05-28 United Technologies Corporation Method to integrate multiple electric circuits into organic matrix composite
US9385111B2 (en) * 2013-11-22 2016-07-05 Infineon Technologies Austria Ag Electronic component with electronic chip between redistribution structure and mounting structure
JP2015142072A (en) 2014-01-30 2015-08-03 株式会社東芝 semiconductor device
JP6338937B2 (en) 2014-06-13 2018-06-06 ローム株式会社 Power module and manufacturing method thereof
US9171788B1 (en) * 2014-09-30 2015-10-27 Alpha And Omega Semiconductor Incorporated Semiconductor package with small gate clip and assembly method
US10796986B2 (en) * 2016-03-21 2020-10-06 Infineon Technologies Ag Leadframe leads having fully plated end faces
TWM544108U (en) * 2017-01-20 2017-06-21 Taiwan Semiconductor Co Ltd Integrated packaging structure
US10121742B2 (en) * 2017-03-15 2018-11-06 Amkor Technology, Inc. Method of forming a packaged semiconductor device using ganged conductive connective assembly and structure
DE112018002151T5 (en) * 2017-03-28 2020-01-16 Rohm Co., Ltd. SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
US10727151B2 (en) * 2017-05-25 2020-07-28 Infineon Technologies Ag Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package
KR20190071111A (en) * 2017-12-14 2019-06-24 삼성전자주식회사 An apparatus for x-ray inspection, and a method for manufacturing a semiconductor device using the same
US11088046B2 (en) * 2018-06-25 2021-08-10 Semiconductor Components Industries, Llc Semiconductor device package with clip interconnect and dual side cooling
IT201800020998A1 (en) 2018-12-24 2020-06-24 St Microelectronics Srl Process for manufacturing semiconductor devices and corresponding semiconductor device
US10964629B2 (en) 2019-01-18 2021-03-30 Texas Instruments Incorporated Siderail with mold compound relief
CN110190004A (en) * 2019-06-11 2019-08-30 山东海声尼克微电子有限公司 A kind of welding procedure for high-current supply Module bond
CN110211887A (en) * 2019-06-11 2019-09-06 山东海声尼克微电子有限公司 A kind of lock material hole copper sheet welding procedure for large-current electric source module wire bonding
CN110416101A (en) * 2019-08-07 2019-11-05 深圳市顺益微电子有限公司 Use sintering silver paste as the power module copper sheet welding procedure of bonding agent
US11158567B2 (en) 2019-08-09 2021-10-26 Texas Instruments Incorporated Package with stacked power stage and integrated control die
US11715679B2 (en) 2019-10-09 2023-08-01 Texas Instruments Incorporated Power stage package including flexible circuit and stacked die
US11302615B2 (en) 2019-12-30 2022-04-12 Texas Instruments Incorporated Semiconductor package with isolated heat spreader
US11239127B2 (en) * 2020-06-19 2022-02-01 Infineon Technologies Ag Topside-cooled semiconductor package with molded standoff
US11652078B2 (en) 2021-04-20 2023-05-16 Infineon Technologies Ag High voltage semiconductor package with pin fit leads
KR20230131024A (en) * 2022-03-04 2023-09-12 현대자동차주식회사 Power module for vehicle and manufacturing method the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821615A (en) * 1995-12-06 1998-10-13 Lg Semicon Co., Ltd. Semiconductor chip package having clip-type outlead and fabrication method of same
US6465276B2 (en) * 2000-05-18 2002-10-15 Siliconx (Taiwan) Ltd. Power semiconductor package and method for making the same
US6677672B2 (en) * 2002-04-26 2004-01-13 Semiconductor Components Industries Llc Structure and method of forming a multiple leadframe semiconductor device
US20040157372A1 (en) * 2003-02-11 2004-08-12 Manatad Romel N. Alternative flip chip in leaded molded package design and method for manufacture
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US6853064B2 (en) * 2003-05-12 2005-02-08 Micron Technology, Inc. Semiconductor component having stacked, encapsulated dice
US20060113646A1 (en) * 2004-11-30 2006-06-01 Eswarappa Channabasappa Connection arrangement for micro lead frame plastic packages

Family Cites Families (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2256493A (en) * 1934-04-13 1941-09-23 Budd Edward G Mfg Co Rail car front end construction
US2148078A (en) * 1935-09-26 1939-02-21 New York Central Railroad Co Streamline locomotive and tender
US2108203A (en) * 1935-09-26 1938-02-15 New York Central Railroad Co Streamlined locomotive and tender and vestibule curtain structure therefor
US3934922A (en) * 1974-09-05 1976-01-27 Aerovironment Inc. Aerodynamic drag reduction devices for surface vehicles
US4257640A (en) * 1975-12-16 1981-03-24 Rudkin-Wiley Corporation Drag reducer for land vehicles
US4030779A (en) * 1976-03-18 1977-06-21 Johnson David W Inflatable streamlining structure for vehicles
US4210354A (en) * 1978-02-06 1980-07-01 Canning Robert B Aerodynamic drag-reducing shield for mounting on the front of a cargo carrying compartment of a road vehicle
FR2467132B1 (en) * 1979-10-08 1985-08-16 Levassor Jean ANTI-WET DEVICE FOR A TRACTOR VEHICLE
US4441751A (en) * 1980-11-24 1984-04-10 Wesley William M Collapsible high speed extension for motor vehicles
US4738203A (en) * 1984-02-27 1988-04-19 Pullman Standard, Inc. Aerodynamically structured railway car with corner, air flow guides
US4746160A (en) * 1986-06-30 1988-05-24 Wiesemeyer Robert L Streamlined truck with semitrailer
US4756256A (en) * 1986-07-30 1988-07-12 Gunderson, Inc. Aerodynamic drag reduction for railcars
US4909154A (en) * 1989-02-27 1990-03-20 Aero Transportation Products, Inc. Aerodynamic end closures for railway hopper cars
US5222438A (en) * 1992-07-17 1993-06-29 Grumman Aerospace Corporation Aerodynamic fairing/brake for high-speed trains
US6423623B1 (en) * 1998-06-09 2002-07-23 Fairchild Semiconductor Corporation Low Resistance package for semiconductor devices
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6473852B1 (en) * 1998-10-30 2002-10-29 Fairchild Semiconductor Corporation Method and circuit for performing automatic power on reset of an integrated circuit
US6424035B1 (en) * 1998-11-05 2002-07-23 Fairchild Semiconductor Corporation Semiconductor bilateral switch
US6307755B1 (en) * 1999-05-27 2001-10-23 Richard K. Williams Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die
US6286894B1 (en) * 1999-08-10 2001-09-11 D. James Kingham Reduced-drag trailer
KR100335480B1 (en) * 1999-08-24 2002-05-04 김덕중 Leadframe using chip pad as heat spreading path and semiconductor package thereof
KR100335481B1 (en) * 1999-09-13 2002-05-04 김덕중 Power device having multi-chip package structure
JP2001166162A (en) 1999-12-09 2001-06-22 Hitachi Cable Ltd Array waveguide type grating
US6720642B1 (en) * 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6989588B2 (en) * 2000-04-13 2006-01-24 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6556750B2 (en) * 2000-05-26 2003-04-29 Fairchild Semiconductor Corporation Bi-directional optical coupler
KR100370231B1 (en) * 2000-06-13 2003-01-29 페어차일드코리아반도체 주식회사 Power module package having a insulator type heat sink attached a backside of leadframe & manufacturing method thereof
US6661082B1 (en) * 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
KR100403608B1 (en) * 2000-11-10 2003-11-01 페어차일드코리아반도체 주식회사 Stacked intelligent power module package and manufacturing method thereof
US6580165B1 (en) * 2000-11-16 2003-06-17 Fairchild Semiconductor Corporation Flip chip with solder pre-plated leadframe including locating holes
US6798044B2 (en) * 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
US6365942B1 (en) * 2000-12-06 2002-04-02 Fairchild Semiconductor Corporation MOS-gated power device with doped polysilicon body and process for forming same
KR100374629B1 (en) * 2000-12-19 2003-03-04 페어차일드코리아반도체 주식회사 A power semiconductor package for thin and small size
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6777786B2 (en) * 2001-03-12 2004-08-17 Fairchild Semiconductor Corporation Semiconductor device including stacked dies mounted on a leadframe
US6891257B2 (en) * 2001-03-30 2005-05-10 Fairchild Semiconductor Corporation Packaging system for die-up connection of a die-down oriented integrated circuit
US6645791B2 (en) * 2001-04-23 2003-11-11 Fairchild Semiconductor Semiconductor die package including carrier with mask
US6893901B2 (en) * 2001-05-14 2005-05-17 Fairchild Semiconductor Corporation Carrier with metal bumps for semiconductor die packages
US6646329B2 (en) * 2001-05-15 2003-11-11 Fairchild Semiconductor, Inc. Power chip scale package
US7061080B2 (en) * 2001-06-11 2006-06-13 Fairchild Korea Semiconductor Ltd. Power module package having improved heat dissipating capability
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US7084488B2 (en) * 2001-08-01 2006-08-01 Fairchild Semiconductor Corporation Packaged semiconductor device and method of manufacture using shaped die
US6449174B1 (en) * 2001-08-06 2002-09-10 Fairchild Semiconductor Corporation Current sharing in a multi-phase power supply by phase temperature control
US6633030B2 (en) * 2001-08-31 2003-10-14 Fiarchild Semiconductor Surface mountable optocoupler package
KR100442847B1 (en) * 2001-09-17 2004-08-02 페어차일드코리아반도체 주식회사 Power semiconductor module that has three dimensional structure and a method of manufacturing thereof
US6774465B2 (en) * 2001-10-05 2004-08-10 Fairchild Korea Semiconductor, Ltd. Semiconductor power package module
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6674157B2 (en) * 2001-11-02 2004-01-06 Fairchild Semiconductor Corporation Semiconductor package comprising vertical power transistor
US6630726B1 (en) * 2001-11-07 2003-10-07 Amkor Technology, Inc. Power semiconductor package with strap
US6566749B1 (en) * 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
US6867489B1 (en) * 2002-01-22 2005-03-15 Fairchild Semiconductor Corporation Semiconductor die package processable at the wafer level
US6830959B2 (en) * 2002-01-22 2004-12-14 Fairchild Semiconductor Corporation Semiconductor die package with semiconductor die having side electrical connection
WO2003079407A2 (en) * 2002-03-12 2003-09-25 Fairchild Semiconductor Corporation Wafer-level coated copper stud bumps
TWI287282B (en) * 2002-03-14 2007-09-21 Fairchild Kr Semiconductor Ltd Semiconductor package having oxidation-free copper wire
US7122884B2 (en) * 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
KR100843737B1 (en) * 2002-05-10 2008-07-04 페어차일드코리아반도체 주식회사 Semiconductor package having improved reliability of solder joint
US7017508B2 (en) * 2002-07-12 2006-03-28 Arthur Vanmoor Hydrodynamically and aerodynamically optimized leading and trailing edge configurations
US7061077B2 (en) * 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6943434B2 (en) * 2002-10-03 2005-09-13 Fairchild Semiconductor Corporation Method for maintaining solder thickness in flipchip attach packaging processes
US6806580B2 (en) * 2002-12-26 2004-10-19 Fairchild Semiconductor Corporation Multichip module including substrate with an array of interconnect structures
KR100958422B1 (en) * 2003-01-21 2010-05-18 페어차일드코리아반도체 주식회사 Semiconductor package having the structure for high voltage application
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
US7073845B2 (en) * 2003-05-30 2006-07-11 The Regents Of The University Of California Aerodynamic drag reduction apparatus for gap-divided bluff bodies such as tractor-trailers
ES2315605T3 (en) * 2003-09-17 2009-04-01 Ricoh Company, Ltd. PHOTORRECEPTOR ELECTROFOTOGRAFICO, PROCEDURE TO MANUFACTURE A PHOTORRECEPTOR ELECTROFOTOGRAFICO, AND APPLIANCE AS WELL AS PROCESS CARTRIDGE USING SUCH ELECTROPHOTOGRAPHIC PHOTORRECEPTOR.
US6972913B2 (en) * 2004-01-29 2005-12-06 Hewlett-Packard Development Company, L.P. Two axis tip-tilt platform
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
US7242076B2 (en) * 2004-05-18 2007-07-10 Fairchild Semiconductor Corporation Packaged integrated circuit with MLP leadframe and method of making same
US7008005B1 (en) * 2004-09-07 2006-03-07 Freight Wing Inc. Device for reducing vehicle aerodynamic resistance
US7256479B2 (en) * 2005-01-13 2007-08-14 Fairchild Semiconductor Corporation Method to manufacture a universal footprint for a package with exposed chip
KR101146973B1 (en) * 2005-06-27 2012-05-22 페어차일드코리아반도체 주식회사 Package frame and semiconductor package using the same
KR101297645B1 (en) * 2005-06-30 2013-08-20 페어차일드 세미컨덕터 코포레이션 Semiconductor die package and method for making the same
US7207620B2 (en) * 2005-08-23 2007-04-24 Cosgrove William E Aerodynamic drag reducing system with retrofittable, selectively removable frame
US8183682B2 (en) * 2005-11-01 2012-05-22 Nxp B.V. Methods of packaging a semiconductor die and package formed by the methods
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
KR101221805B1 (en) * 2006-03-03 2013-01-14 페어차일드코리아반도체 주식회사 Package and package assembly for power device
US7768105B2 (en) * 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US7898067B2 (en) * 2008-10-31 2011-03-01 Fairchild Semiconductor Corporaton Pre-molded, clip-bonded multi-die semiconductor package
US8222718B2 (en) * 2009-02-05 2012-07-17 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821615A (en) * 1995-12-06 1998-10-13 Lg Semicon Co., Ltd. Semiconductor chip package having clip-type outlead and fabrication method of same
US6465276B2 (en) * 2000-05-18 2002-10-15 Siliconx (Taiwan) Ltd. Power semiconductor package and method for making the same
US6677672B2 (en) * 2002-04-26 2004-01-13 Semiconductor Components Industries Llc Structure and method of forming a multiple leadframe semiconductor device
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US20040157372A1 (en) * 2003-02-11 2004-08-12 Manatad Romel N. Alternative flip chip in leaded molded package design and method for manufacture
US6853064B2 (en) * 2003-05-12 2005-02-08 Micron Technology, Inc. Semiconductor component having stacked, encapsulated dice
US20060113646A1 (en) * 2004-11-30 2006-06-01 Eswarappa Channabasappa Connection arrangement for micro lead frame plastic packages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI727861B (en) * 2020-07-23 2021-05-11 朋程科技股份有限公司 Chip packaging structure and method of manufacturing the same

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