WO2008101093B1 - Post-seed deposition process - Google Patents

Post-seed deposition process

Info

Publication number
WO2008101093B1
WO2008101093B1 PCT/US2008/053982 US2008053982W WO2008101093B1 WO 2008101093 B1 WO2008101093 B1 WO 2008101093B1 US 2008053982 W US2008053982 W US 2008053982W WO 2008101093 B1 WO2008101093 B1 WO 2008101093B1
Authority
WO
WIPO (PCT)
Prior art keywords
seed layer
resist
layer
exposed
metal
Prior art date
Application number
PCT/US2008/053982
Other languages
French (fr)
Other versions
WO2008101093A1 (en
Inventor
John Callahan
John Trezza
Original Assignee
Cubic Wafer Inc
John Callahan
John Trezza
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cubic Wafer Inc, John Callahan, John Trezza filed Critical Cubic Wafer Inc
Priority to CN200880004533XA priority Critical patent/CN101632166B/en
Priority to EP08729880A priority patent/EP2111635A1/en
Priority to JP2009549722A priority patent/JP5476127B2/en
Priority to KR1020097018804A priority patent/KR101118798B1/en
Publication of WO2008101093A1 publication Critical patent/WO2008101093A1/en
Publication of WO2008101093B1 publication Critical patent/WO2008101093B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Abstract

A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the phototresist and plated metal until all of the exposed seed layer has been removed.

Claims

AMENDED CLAIMS Received by the International Bureau on 29 August 2008 (29.08.08)
1. A method, comprising: depositing a seed layer onto a wafer; forming a patterned resist on top of the seed layer, wherein the patterned resist has one or more openings exposing at least one portion of the seed layer, and wherein the patterned resist overhangs all or part of a via; plating the exposed at least one portion of the seed layer with a layer of metal, wherein the layer of metal extends above the upper surface of the seed layer; removing the resist; and removing at least one portion of the seed layer that was exposed by said removing the resist.
2. The method of claim 1, wherein said removing the resist comprises exposing a side portion of the layer of metal.
3. The method of claim 1 , wherein said plating the exposed areas of the seed layer comprises performing an electroless plating process on the exposed areas of the seed layer.
A. The method of claim 1, wherein said plating the exposed areas of the seed layer comprises performing an electroplating process on the exposed areas of the seed layer.
5. The method of claim 1 , further comprising depositing an insulator on the wafer prior io depositing the seed layer.
6. The method of claim 1 , wherein removing those portions of the seed layer that were exposed comprises concurrently etching away the exposed portions of the seed layer and the layer of metal until the height of the layer of metal has been reduced by at least the thickness of the seed layer.
7. The method of claim 1, wherein the patterned resist defines at least one opening configured to define at least a portion of an integrated circuit path along a surface of the wafer.
8. The method of claim I , wherein the patterned resist defines at least one opening configured to define a post-like standoff.
9. The method of claim 1 , wherein a via is formed in the wafer, wherein the seed layer is deposited in the via, and wherein the openings in the resist are located at least partially over the via.
10. The method of claim 9, wherein the patterned resist is a solid resist that is configured to cover at least a portion of the opening of the via.
11. The method of claim 9, wherein a portion of the layer of metal extends beyond the opening of the via and is configured to provide a routing trace.
12. A method, comprising: patterning a resist that is located on a seed layer of a wafer to expose at least one portion of the seed layer and to overhang all or part of a via; plating the at least one exposed portion of the seed layer with a layer of metal, wherein the layer of metal extends above the upper surface of the seed layer; removing the solid resist; and subsequently removing the at least one exposed portion of the seed layer and at least a portion of the metal layer.
13. The method of claim 12, wherein plating the at least one exposed area of the seed layer comprises performing an electroless plating process on the at least one exposed area of the seed layer.
14. The method of claim 12, wherein plating the at least one exposed area of the seed layer comprises performing an electroplating process on the at least one exposed area of the seed layer.
15. The method of claim 12, wherein a via is formed in the wafer, and wherein the at least one exposed portion of the seed layer is located in the via.
16. The method of claim 12, wherein removing at least a portion of the metal layer comprises reducing the thickness of the metal layer by an amount at least equal to the thickness of the seed layer.
17. The method of claim 12, wherein the resist is patterned to define at least one opening configured to define at least a portion of an integrated circuit path along a surface of the wafer.
18. The method of claim 12, wherein the resist is patterned to define at least one opening configured to define a post-like standoff.
19. The method of claim 12, wherein the resist is a solid resist.
PCT/US2008/053982 2007-02-15 2008-02-14 Post-seed deposition process WO2008101093A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN200880004533XA CN101632166B (en) 2007-02-15 2008-02-14 Post-seed deposition process
EP08729880A EP2111635A1 (en) 2007-02-15 2008-02-14 Post-seed deposition process
JP2009549722A JP5476127B2 (en) 2007-02-15 2008-02-14 Post-seed stratification process
KR1020097018804A KR101118798B1 (en) 2007-02-15 2008-02-14 Post-seed deposition process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/675,268 2007-02-15
US11/675,268 US7598163B2 (en) 2007-02-15 2007-02-15 Post-seed deposition process

Publications (2)

Publication Number Publication Date
WO2008101093A1 WO2008101093A1 (en) 2008-08-21
WO2008101093B1 true WO2008101093B1 (en) 2008-10-30

Family

ID=39512688

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/053982 WO2008101093A1 (en) 2007-02-15 2008-02-14 Post-seed deposition process

Country Status (6)

Country Link
US (1) US7598163B2 (en)
EP (1) EP2111635A1 (en)
JP (1) JP5476127B2 (en)
KR (1) KR101118798B1 (en)
CN (1) CN101632166B (en)
WO (1) WO2008101093A1 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5065674B2 (en) * 2006-12-28 2012-11-07 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
JP5302522B2 (en) 2007-07-02 2013-10-02 スパンション エルエルシー Semiconductor device and manufacturing method thereof
WO2009023462A1 (en) * 2007-08-10 2009-02-19 Spansion Llc Semiconductor device and method for manufacturing thereof
US8264065B2 (en) * 2009-10-23 2012-09-11 Synopsys, Inc. ESD/antenna diodes for through-silicon vias
TWI392069B (en) * 2009-11-24 2013-04-01 Advanced Semiconductor Eng Package structure and packaging process thereof
TWI446420B (en) 2010-08-27 2014-07-21 Advanced Semiconductor Eng Releasing carrier method for semiconductor process
TWI445152B (en) 2010-08-30 2014-07-11 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
TWI434387B (en) 2010-10-11 2014-04-11 Advanced Semiconductor Eng Semiconductor element having a via and package having a semiconductor element with a via and method for making the same
TWI527174B (en) 2010-11-19 2016-03-21 日月光半導體製造股份有限公司 Package having semiconductor device
TWI445155B (en) 2011-01-06 2014-07-11 Advanced Semiconductor Eng Stacked semiconductor package and method for making the same
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
KR101441632B1 (en) * 2012-12-28 2014-09-23 (재)한국나노기술원 Manufacturing method of space transformer for glass base probe card and the space transformer for glass base probe card thereby
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US9089268B2 (en) 2013-03-13 2015-07-28 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US9173583B2 (en) 2013-03-15 2015-11-03 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US8987734B2 (en) 2013-03-15 2015-03-24 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
US11758666B2 (en) * 2020-09-14 2023-09-12 Innolux Corporation Manufacturing method of metal structure
US20230096301A1 (en) * 2021-09-29 2023-03-30 Catlam, Llc. Circuit Board Traces in Channels using Electroless and Electroplated Depositions

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5071518A (en) 1989-10-24 1991-12-10 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer interconnect
EP0516866A1 (en) 1991-05-03 1992-12-09 International Business Machines Corporation Modular multilayer interwiring structure
JP3313432B2 (en) * 1991-12-27 2002-08-12 株式会社東芝 Semiconductor device and manufacturing method thereof
US5603847A (en) 1993-04-07 1997-02-18 Zycon Corporation Annular circuit components coupled with printed circuit board through-hole
US5587119A (en) 1994-09-14 1996-12-24 E-Systems, Inc. Method for manufacturing a coaxial interconnect
US5814889A (en) 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US6946716B2 (en) * 1995-12-29 2005-09-20 International Business Machines Corporation Electroplated interconnection structures on integrated circuit chips
US6310484B1 (en) 1996-04-01 2001-10-30 Micron Technology, Inc. Semiconductor test interconnect with variable flexure contacts
US7052941B2 (en) 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
JP3176307B2 (en) 1997-03-03 2001-06-18 日本電気株式会社 Mounting structure of integrated circuit device and method of manufacturing the same
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US5962922A (en) 1998-03-18 1999-10-05 Wang; Bily Cavity grid array integrated circuit package
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
US6122187A (en) 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6316737B1 (en) 1999-09-09 2001-11-13 Vlt Corporation Making a connection between a component and a circuit board
JP3386029B2 (en) 2000-02-09 2003-03-10 日本電気株式会社 Flip chip type semiconductor device and manufacturing method thereof
JP2001338947A (en) 2000-05-26 2001-12-07 Nec Corp Flip chip type semiconductor device and its manufacturing method
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6740576B1 (en) 2000-10-13 2004-05-25 Bridge Semiconductor Corporation Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly
JP2002134545A (en) 2000-10-26 2002-05-10 Oki Electric Ind Co Ltd Semiconductor integrated circuit chip, board and their manufacturing method
JP4608763B2 (en) 2000-11-09 2011-01-12 日本電気株式会社 Semiconductor device
EP1405336A2 (en) * 2000-12-04 2004-04-07 Ebara Corporation Substrate processing method
US6512300B2 (en) 2001-01-10 2003-01-28 Raytheon Company Water level interconnection
US6747347B2 (en) 2001-08-30 2004-06-08 Micron Technology, Inc. Multi-chip electronic package and cooling system
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
US7135777B2 (en) 2002-05-03 2006-11-14 Georgia Tech Research Corporation Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof
US6939789B2 (en) 2002-05-13 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wafer level chip scale packaging
SG111069A1 (en) 2002-06-18 2005-05-30 Micron Technology Inc Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods
JP2004103911A (en) * 2002-09-11 2004-04-02 Shinko Electric Ind Co Ltd Method for forming wiring
SG111972A1 (en) 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
US20040108217A1 (en) * 2002-12-05 2004-06-10 Dubin Valery M. Methods for forming copper interconnect structures by co-plating of noble metals and structures formed thereby
JP4145301B2 (en) 2003-01-15 2008-09-03 富士通株式会社 Semiconductor device and three-dimensional mounting semiconductor device
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US20050104027A1 (en) 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
JP4114660B2 (en) * 2003-12-16 2008-07-09 セイコーエプソン株式会社 Semiconductor device manufacturing method, semiconductor device, circuit board, electronic device
US20050179120A1 (en) 2003-12-16 2005-08-18 Koji Yamaguchi Process for producing semiconductor device, semiconductor device, circuit board and electronic equipment
US7230318B2 (en) 2003-12-24 2007-06-12 Agency For Science, Technology And Research RF and MMIC stackable micro-modules
US7157310B2 (en) 2004-09-01 2007-01-02 Micron Technology, Inc. Methods for packaging microfeature devices and microfeature devices formed by such methods
JP4246132B2 (en) 2004-10-04 2009-04-02 シャープ株式会社 Semiconductor device and manufacturing method thereof
US7348671B2 (en) 2005-01-26 2008-03-25 Micron Technology, Inc. Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same
US7838997B2 (en) * 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices

Also Published As

Publication number Publication date
JP5476127B2 (en) 2014-04-23
KR101118798B1 (en) 2012-03-21
US7598163B2 (en) 2009-10-06
JP2010519738A (en) 2010-06-03
EP2111635A1 (en) 2009-10-28
CN101632166B (en) 2012-11-28
WO2008101093A1 (en) 2008-08-21
US20080200022A1 (en) 2008-08-21
KR20090115203A (en) 2009-11-04
CN101632166A (en) 2010-01-20

Similar Documents

Publication Publication Date Title
WO2008101093B1 (en) Post-seed deposition process
JP2010519738A5 (en)
US7550375B2 (en) Method for forming metal bumps
MY171428A (en) Method for metallization of solar cell substrates
TW200705632A (en) Method for forming high reliability bump structure
EP2197253A8 (en) Method for electric circuit deposition
ATE470237T1 (en) A METHOD FOR DEPOSING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE WITH A TOP LAYER
TW200735349A (en) Semiconductor devices having plated contacts, and methods of manufacturing the same
TW200701845A (en) Method of manufacturing wiring board
KR100674458B1 (en) Printed circuit board and method of manufacturing the same
US8051560B2 (en) Method of fabricating a solder pad structure
JP2009260216A (en) Method for manufacturing wiring board
KR20130051710A (en) Printed circuit board and method for manufacturing the same
CN103515259A (en) Method of manufacturing semiconductor packaging
US20090200072A1 (en) Wiring substrate and method for manufacturing the same
CN100524675C (en) Method for forming metal projection
JP2005206881A (en) Method of producing metal mask by electroforming process
JP2007234889A (en) Method of forming wiring
TW200604385A (en) Electroformed metallization
US20130044041A1 (en) Portable electronic device, antenna structure, and antenna producing process thereof
CN101339908B (en) Electroplating method of electric contact mat and semi-conductor substrate having the electric contact mat
KR20100078312A (en) Method for manufacturing air-bridge using negative photoresist
TWI363586B (en) Method for fabricating fine line on printing circuit board
CN102752962A (en) Substrate provided with metal layer and manufacturing method thereof
TW200643229A (en) Metal electroplating process of electrically connecting pad structure on circuit board and structure thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880004533.X

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08729880

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009549722

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2008729880

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020097018804

Country of ref document: KR