WO2008118489A1 - Chip scale power converter package having an inductor substrate - Google Patents

Chip scale power converter package having an inductor substrate Download PDF

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Publication number
WO2008118489A1
WO2008118489A1 PCT/US2008/004032 US2008004032W WO2008118489A1 WO 2008118489 A1 WO2008118489 A1 WO 2008118489A1 US 2008004032 W US2008004032 W US 2008004032W WO 2008118489 A1 WO2008118489 A1 WO 2008118489A1
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WO
WIPO (PCT)
Prior art keywords
inductor
substrate
magnetic core
planar spiral
power converter
Prior art date
Application number
PCT/US2008/004032
Other languages
French (fr)
Inventor
Francois Hebert
Ming Sun
Original Assignee
Alpha & Omega Semiconductor Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha & Omega Semiconductor Limited filed Critical Alpha & Omega Semiconductor Limited
Priority to CN2008800034833A priority Critical patent/CN101611494B/en
Publication of WO2008118489A1 publication Critical patent/WO2008118489A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1902—Structure including thick film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/4902—Electromagnet, transformer or inductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/4902—Electromagnet, transformer or inductor
    • Y10T29/49075—Electromagnet, transformer or inductor including permanent magnet or core

Definitions

  • the present invention generally relates to chip scale packaging and more particularly to a chip scale power converter package having an inductor substrate.
  • an inductor on top of an integrated circuit die such as a power converter integrated circuit die.
  • power converters available from Enpirion of Bridgewater, NJ include a MEMS-based inductor having a thick electroplated copper spiral coil sandwiched between two planar magnetic layers and disposed over an integrated DC-DC converter.
  • a large die is required resulting in a high cost and a large package.
  • complex processing is necessary in order to fabricate the planar magnetic layers.
  • the chip scale power converter in accordance with the invention combines an inductor with the chip scale package to improve efficiency of assembly.
  • An inductor substrate is provided that includes an optimized planar spiral inductor.
  • a power IC is flipped onto the inductor substrate to form the chip scale power converter.
  • a power converter package includes an inductor substrate and a power integrated circuit bonded onto the inductor substrate.
  • a chip scale inductor substrate includes a high resistivity substrate, and a planar spiral inductor formed on the substrate.
  • a method of fabricating a chip scale power converter package includes the steps of providing a substrate, fabricating a plurality of planar spiral inductors on the substrate to form a plurality of inductor substrates, bonding an integrated circuit onto each inductor substrate, and dicing the plurality of inductor substrates.
  • FIG. 1 is a top plan view of an inductor substrate in accordance with the invention.
  • FIG. 2 is a cross sectional view of the inductor substrate of FIG. 1 ;
  • FIG. 3 is a top plan view of an alternative inductor substrate in accordance with the invention.
  • FIG. 4 is a top plan view of a chip scale power converter package showing a flip chip power IC in phantom in accordance with the invention
  • FIG. 5 and Fig. 5A are cross sectional views of chip scale power converter packages in accordance with the invention.
  • FIG. 6 is a cross sectional view of the chip scale power converter package of FIG. 4 mounted to a printed circuit board in accordance with the invention
  • FIG. 7 is a cross sectional view of an alternative chip scale power converter package in accordance with the invention.
  • FIG. 8 and FIG. 9 are a flow chart showing a method in accordance with the invention.
  • FIG. 10 through FIG. 16 shows an inductor substrate in various stages of fabrication in accordance with the invention
  • FIG. 17 and 18 show an alternative inductor substrate in various stages of fabrication in accordance with the invention.
  • FIG. 19 is a cross sectional view of an alternative chip scale power converter package in accordance with the invention. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
  • the present invention provides a chip scale power converter having an inductor substrate.
  • An exemplary inductor substrate 100 is shown in FIG. 1 and FIG. 2.
  • Inductor substrate 100 includes a substrate 105 formed of a high resistivity material including silicon and glass, or a magnetic core material such as Ferrite or NiFe, or a mutil-layered structure of magnetic core material and oxide over silicon wafer or other substrate wafer.
  • a planar spiral inductor 150 having a first end 155 and a second end 160 is formed on the substrate 105 as further detailed herein.
  • An oxide layer 110 is formed over the substrate 105.
  • Optional cross over metal layers 115 and 117 are formed of metal or alloys including Cu, AICu, and Cu/TiW over portions of the oxide layer 110.
  • Cross over metal layer 115 provides contact to the planar spiral inductor first end 155 at peripheral contact 165.
  • An optional layer 120 of inter-metal dielectric material preferably a low-K dielectric material including benzocyclobutene (BCB), polyimide and other organic materials such as SU-8 available from MicroChem of Newton, Massachusetts, is disposed over the oxide layer 110 and layers 115 and 117 to provide for low parasitic capacitance.
  • Optional barrier metal layers 125 may be disposed between layers 115 and 117, and thick metal structures 130 defining the planar spiral inductor 150.
  • the thick metal structures 130 may be formed of Cu or other thick and low resistivity metals such as Au.
  • a passivation layer 140 covers the planar spiral inductor 150 to complete the inductor substrate 100.
  • optional cross over metal layers 115 and 117 may be formed over a passivation layer 140 to provide contact to the planar spiral inductor first end 155 at peripheral contact 165.
  • FIG. 3 A preferred embodiment of an inductor substrate 300 is shown in FIG. 3.
  • a planar spiral inductor 310 is disposed on a substrate 315 so as to maximize the inductance of the inductor 130.
  • Contacts 320, 323, 325, 327 and 329 provide contacts for a flip-chip power IC controller/converter as further described herein.
  • Contact 327 is electrically coupled to a first end 330 of the planar spiral inductor 310.
  • Contacts 320, 323, 325, and 329 are coupled to contacts 333, 335, 337 and 339 respectively by means of cross over metal layers 340, 343, 345 and 347.
  • Contact 350 is electrically coupled to a second end 353 of the planar spiral inductor 310.
  • Solder bumps 360, 363, 365, 367, and 369 provide connectivity to contacts 333, 335, 337, 350, and 339 respectively.
  • a chip scale power converter 400 is shown including a flip-chip power IC controller/converter 410 electrically coupled to the inductor substrate 300.
  • the flip-chip power IC controller/converter 410 is shown in phantom to show connection to contacts 320, 323, 325 and 327.
  • a cross sectional view of the chip scale power converter 400 is shown in FIG. 5.
  • the chip scale power converter 400 is shown in FIG. 6 mounted to a printed circuit board 600 having traces 610.
  • contacts 320, 323, 325, 327 and 329 are not provided and an IC chip 410 may be mounted on the inductor substrate 300 with contacts exposed to form a chip scale power converter 400' as shown in Fig. 5A.
  • the IC chip 410 has contacts on both its surfaces, some contacts may be accessed directly from one surface of IC chip 410 and some contacts may be accessed from contacts on the inductor substrate through cross over metals. Furthermore, the solder bump contacts may be replaced by patterned metal contact pads so that the combined inductor substrate with the IC chip can be packed into traditional packages by wire bonding.
  • a patterned magnetic core layer is formed under the planar spiral inductor in the substrate.
  • a patterned magnetic core layer is formed above the planar spiral inductor.
  • patterned magnetic core layers are formed above and below the planar spiral inductor.
  • multi-layered patterned magnetic core layers sandwiched by dialectical layers such as silicon oxides are formed above and /or below the planar inductor. Provision of patterned magnetic core layers increases the inductance per unit area of the spiral inductor and provides shielding of stray magnetic fields.
  • a patterned magnetic core layer 700 is shown formed under the planar spiral inductor 710 and a patterned magnetic core layer 720 is shown formed over the planar spiral inductor 710.
  • the magnetic core layers 700 and 720 can be sputtered, evaporated, plated, bonded or co-packaged as a chip on the inductor substrate.
  • Magnetic core layers 700 and 720 may be formed of materials with appropriate magnetic performance such as Ni, Co, ferrites, and combinations of these materials.
  • a method 800 (FIG. 8) of fabricating the inductor substrate in accordance with the invention includes providing a high resistivity substrate wafer 1000 (FIG. 10) in a step 805.
  • the substrate 1000 is thermally oxidized to form an oxide layer 1005 in a step 810.
  • a magnetic core material such as electroplated permalloy is deposited on the oxide layer 1005 to form a magnetic core layer 1010 and in a step 820, an oxide or dielectric layer 1015 is deposited on the magnetic core layer 1010.
  • step 825 cross over metal 1020 and 1025 (FIG. 11 ) is deposited onto oxide or dielectric layer 1015 such as by thick AICu deposition (>1.5 microns), sputtered Cu/TiW, or plated Cu.
  • Step 825 may include masking, stripping, and etching processes.
  • a thin oxide layer 1030 (FIG. 12) is next deposited to promote adhesion of a low-K inter-metal dielectric material including benzocyclobutene (BCB), polyimide or SU-8, in a step 830.
  • BCB benzocyclobutene
  • the BCB 1035 is spun to a thickness of 10 to 20 microns.
  • Vias 1040 are next formed in a step 840 including masking and developing the BCB or polyimide (in the case photodefined BCB or polyimide is used) or developing and etching the BCB (in the case non-photodefined BCB or polyimide is used).
  • a barrier metal 1045 (FIG. 13) including TiW or TiN is next deposited in a step 855 and a copper seed layer 1050 deposited in a step 860 overlaying barrier metal layer 1045.
  • a thick photoresist layer is patterned, copper is electroplated to a thickness of 17 microns or greater, and the photoresist stripped to form a planar spiral inductor 1055 (FIG. 14).
  • the copper layer may be deposited over the whole substrate and then patterned and etched with a mask.
  • a low resistivity metal like Gold can be used in place of Cu.
  • barrier metal 1045 and the seed layer 1050 are next etched in a step
  • a passivation layer 1060 (FIG. 16) formed of BCB or polyimide is deposited. Magnetic core material is next deposited and patterned or plated in an optional step 880 to form magnetic core layer 1065. A second passivation layer 1070 is then deposited in a step 885. Contact pads 1075 are masked and etched in a step 890 and solder bumps (not shown) formed in a step 895. In another embodiment, a layer of metal is deposited and then patterned to form cross over metals (not shown) before solder bumps are formed in step 895. Following the process 800, an IC chip may be attached to the inductor substrate by a standard bonding process or by a flip-chip bonding process and the whole inductor substrate diced into individual packages.
  • 1700 to the magnetic core layer 1010 is formed following the step 875 in which a passivation layer 1710 (FIG. 17) is formed over the planar spiral inductor 1055.
  • Magnetic core material is then deposited as a blanket layer and patterned or plated in the step 880 (FIG. 18) to form magnetic core layer 1065.
  • Magnetic core material in via 1700 connects the magnetic core layer 1065 with the magnetic core layer 1010 to maximize the inductance of the spiral inductor 1055.
  • An inductor substrate 1900 and mounted power IC flip chip 1910 is shown in FIG. 19. Maximum inductance is achieved by contact between the magnetic core layers but a separation on the order of a few microns is acceptable.
  • the chip scale power converter having an inductor substrate of the invention combines the inductor in the package to improve efficiency of assembly.
  • the inventive package does not integrate the inductor directly with the more costly power IC.
  • optimized interconnection between the power IC and the inductor is provided to minimize parasitics, improve performance and achieve high reliability.
  • the chip scale power converter having an inductor substrate according to the invention is particularly suited for high frequency (>5 MHz) applications requiring lower inductance values. It is also suited for low current applications to leverage the planar spiral inductor.
  • the inductor substrate of the invention is simple to fabricate at a low cost and maximizes the inductance while minimizing cost and space.
  • the inductor substrate may be formed without the magnetic core materials and optional components including resistors and capacitors may be formed in the substrate.
  • high power MOSFET devices may be incorporated in the substrate.
  • various aspects of a particular embodiment may contain patentably subject matter without regard to other aspects of the same embodiment. Still further, various aspects of different embodiments can be combined together. Accordingly, the scope of the invention should be determined by the following claims and their legal equivalents.

Abstract

A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.

Description

CHIP SCALE POWER CONVERTER PACKAGE HAVING AN INDUCTOR
SUBSTRATE
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The present invention generally relates to chip scale packaging and more particularly to a chip scale power converter package having an inductor substrate.
2. Description of Related Art
[0002] It is well known to include a discrete inductor on the printed circuit board when implementing a power converter circuit. For example, the Analogic™TECH 1 MHz 40OmA Step-Down Converter (AAT1143) requires the use of a discreet inductor. Power converters implemented in this way suffer the disadvantages of having higher component cost and of requiring more printed circuit board space. [0003] Discrete inductors co-packaged with power ICs and other components are also well known. For example, the LTM®4600 DC/DC power converter available from Linear Technology Corporation of Milpitas, CA, includes a built-in inductor in a 15mm x 15mm x 2.8mm package. The package disadvantageously uses valuable printed circuit board space.
[0004] It is further known to dispose an inductor on top of an integrated circuit die such as a power converter integrated circuit die. For example, power converters available from Enpirion of Bridgewater, NJ, include a MEMS-based inductor having a thick electroplated copper spiral coil sandwiched between two planar magnetic layers and disposed over an integrated DC-DC converter. To achieve high inductance, a large die is required resulting in a high cost and a large package. Furthermore, complex processing is necessary in order to fabricate the planar magnetic layers. [0005] There is therefore a need in the art for a chip scale power converter that overcomes the disadvantages of the prior art. There is a need for a low cost chip scale power converter that does not require an external inductor. There is a further need for a chip scale power converter having an optimized interconnection between the power IC and the inductor for minimized parasitics, improved performance and high reliability.
SUMMARY OF THE INVENTION
[0006] The chip scale power converter in accordance with the invention combines an inductor with the chip scale package to improve efficiency of assembly. An inductor substrate is provided that includes an optimized planar spiral inductor. A power IC is flipped onto the inductor substrate to form the chip scale power converter. [0007] In accordance with one aspect of the invention, a power converter package includes an inductor substrate and a power integrated circuit bonded onto the inductor substrate.
[0008] In accordance with another aspect of the invention, a chip scale inductor substrate includes a high resistivity substrate, and a planar spiral inductor formed on the substrate.
[0009] In accordance with another aspect of the invention, a method of fabricating a chip scale power converter package includes the steps of providing a substrate, fabricating a plurality of planar spiral inductors on the substrate to form a plurality of inductor substrates, bonding an integrated circuit onto each inductor substrate, and dicing the plurality of inductor substrates.
[0010] There has been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof that follows may be better understood, and in order that the present contribution to the art may be better appreciated. There are, of course, additional features of the invention that will be described below and which will form the subject matter of the claims appended herein. [0011] In this respect, before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of functional components and to the arrangements of these components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein, as well as the abstract, are for the purpose of description and should not be regarded as limiting. [0012] As such, those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for the designing of other methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] These and other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures, wherein:
[0014] FIG. 1 is a top plan view of an inductor substrate in accordance with the invention;
[0015] FIG. 2 is a cross sectional view of the inductor substrate of FIG. 1 ;
[0016] FIG. 3 is a top plan view of an alternative inductor substrate in accordance with the invention;
[0017] FIG. 4 is a top plan view of a chip scale power converter package showing a flip chip power IC in phantom in accordance with the invention;
[0018] FIG. 5 and Fig. 5A are cross sectional views of chip scale power converter packages in accordance with the invention;
[0019] FIG. 6 is a cross sectional view of the chip scale power converter package of FIG. 4 mounted to a printed circuit board in accordance with the invention;
[0020] FIG. 7 is a cross sectional view of an alternative chip scale power converter package in accordance with the invention;
[0021] FIG. 8 and FIG. 9 are a flow chart showing a method in accordance with the invention;
[0022] FIG. 10 through FIG. 16 shows an inductor substrate in various stages of fabrication in accordance with the invention;
[0023] FIG. 17 and 18 show an alternative inductor substrate in various stages of fabrication in accordance with the invention; and
[0024] FIG. 19 is a cross sectional view of an alternative chip scale power converter package in accordance with the invention. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
[0025] The present invention will now be described in detail with reference to the drawings, which are provided as illustrative examples of the invention so as to enable those skilled in the art to practice the invention. Notably, the figures and examples below are not meant to limit the scope of the present invention. Where certain elements of the present invention can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present invention will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the invention. Further, the present invention encompasses present and future known equivalents to the components referred to herein by way of illustration.
[0026] The present invention provides a chip scale power converter having an inductor substrate. An exemplary inductor substrate 100 is shown in FIG. 1 and FIG. 2. Inductor substrate 100 includes a substrate 105 formed of a high resistivity material including silicon and glass, or a magnetic core material such as Ferrite or NiFe, or a mutil-layered structure of magnetic core material and oxide over silicon wafer or other substrate wafer. A planar spiral inductor 150 having a first end 155 and a second end 160 is formed on the substrate 105 as further detailed herein.
[0027] An oxide layer 110 is formed over the substrate 105. Optional cross over metal layers 115 and 117 are formed of metal or alloys including Cu, AICu, and Cu/TiW over portions of the oxide layer 110. Cross over metal layer 115 provides contact to the planar spiral inductor first end 155 at peripheral contact 165. [0028] An optional layer 120 of inter-metal dielectric material, preferably a low-K dielectric material including benzocyclobutene (BCB), polyimide and other organic materials such as SU-8 available from MicroChem of Newton, Massachusetts, is disposed over the oxide layer 110 and layers 115 and 117 to provide for low parasitic capacitance. Optional barrier metal layers 125 may be disposed between layers 115 and 117, and thick metal structures 130 defining the planar spiral inductor 150. The thick metal structures 130 may be formed of Cu or other thick and low resistivity metals such as Au. A passivation layer 140 covers the planar spiral inductor 150 to complete the inductor substrate 100. Alternatively, optional cross over metal layers 115 and 117 may be formed over a passivation layer 140 to provide contact to the planar spiral inductor first end 155 at peripheral contact 165.
[0029] A preferred embodiment of an inductor substrate 300 is shown in FIG. 3.
A planar spiral inductor 310 is disposed on a substrate 315 so as to maximize the inductance of the inductor 130. Contacts 320, 323, 325, 327 and 329 provide contacts for a flip-chip power IC controller/converter as further described herein. Contact 327 is electrically coupled to a first end 330 of the planar spiral inductor 310. Contacts 320, 323, 325, and 329 are coupled to contacts 333, 335, 337 and 339 respectively by means of cross over metal layers 340, 343, 345 and 347. Contact 350 is electrically coupled to a second end 353 of the planar spiral inductor 310. Solder bumps 360, 363, 365, 367, and 369 provide connectivity to contacts 333, 335, 337, 350, and 339 respectively.
[0030] With reference to FIG. 4, a chip scale power converter 400 is shown including a flip-chip power IC controller/converter 410 electrically coupled to the inductor substrate 300. The flip-chip power IC controller/converter 410 is shown in phantom to show connection to contacts 320, 323, 325 and 327. A cross sectional view of the chip scale power converter 400 is shown in FIG. 5. The chip scale power converter 400 is shown in FIG. 6 mounted to a printed circuit board 600 having traces 610. Alternatively, contacts 320, 323, 325, 327 and 329 are not provided and an IC chip 410 may be mounted on the inductor substrate 300 with contacts exposed to form a chip scale power converter 400' as shown in Fig. 5A. In case the IC chip 410 has contacts on both its surfaces, some contacts may be accessed directly from one surface of IC chip 410 and some contacts may be accessed from contacts on the inductor substrate through cross over metals. Furthermore, the solder bump contacts may be replaced by patterned metal contact pads so that the combined inductor substrate with the IC chip can be packed into traditional packages by wire bonding.
[0031] In alternative embodiments, a patterned magnetic core layer is formed under the planar spiral inductor in the substrate. Alternatively, a patterned magnetic core layer is formed above the planar spiral inductor. In yet other alternative embodiments, patterned magnetic core layers are formed above and below the planar spiral inductor. In yet other alternative embodiments, multi-layered patterned magnetic core layers sandwiched by dialectical layers such as silicon oxides are formed above and /or below the planar inductor. Provision of patterned magnetic core layers increases the inductance per unit area of the spiral inductor and provides shielding of stray magnetic fields. With reference to FIG. 7, a patterned magnetic core layer 700 is shown formed under the planar spiral inductor 710 and a patterned magnetic core layer 720 is shown formed over the planar spiral inductor 710. The magnetic core layers 700 and 720 can be sputtered, evaporated, plated, bonded or co-packaged as a chip on the inductor substrate. Magnetic core layers 700 and 720 may be formed of materials with appropriate magnetic performance such as Ni, Co, ferrites, and combinations of these materials.
[0032] A method 800 (FIG. 8) of fabricating the inductor substrate in accordance with the invention includes providing a high resistivity substrate wafer 1000 (FIG. 10) in a step 805. The substrate 1000 is thermally oxidized to form an oxide layer 1005 in a step 810. In an optional step 815 a magnetic core material such as electroplated permalloy is deposited on the oxide layer 1005 to form a magnetic core layer 1010 and in a step 820, an oxide or dielectric layer 1015 is deposited on the magnetic core layer 1010.
[0033] In a optional step 825, cross over metal 1020 and 1025 (FIG. 11 ) is deposited onto oxide or dielectric layer 1015 such as by thick AICu deposition (>1.5 microns), sputtered Cu/TiW, or plated Cu. Step 825 may include masking, stripping, and etching processes.
[0034] A thin oxide layer 1030 (FIG. 12) is next deposited to promote adhesion of a low-K inter-metal dielectric material including benzocyclobutene (BCB), polyimide or SU-8, in a step 830. In an optional step 835, the BCB 1035 is spun to a thickness of 10 to 20 microns. Vias 1040 are next formed in a step 840 including masking and developing the BCB or polyimide (in the case photodefined BCB or polyimide is used) or developing and etching the BCB (in the case non-photodefined BCB or polyimide is used). The structure is next baked in a step 845 and the thin oxide layer 1030 is etched in a step 850 using the BCB, polyimide or SU-8 layer as mask. [0035] A barrier metal 1045 (FIG. 13) including TiW or TiN is next deposited in a step 855 and a copper seed layer 1050 deposited in a step 860 overlaying barrier metal layer 1045. In a step 865, a thick photoresist layer is patterned, copper is electroplated to a thickness of 17 microns or greater, and the photoresist stripped to form a planar spiral inductor 1055 (FIG. 14). Alternatively, the copper layer may be deposited over the whole substrate and then patterned and etched with a mask. A low resistivity metal like Gold (commonly used in RF and microwave power devices for example), can be used in place of Cu.
[0036] The barrier metal 1045 and the seed layer 1050 are next etched in a step
870 (FIG. 15). In a step 875, a passivation layer 1060 (FIG. 16) formed of BCB or polyimide is deposited. Magnetic core material is next deposited and patterned or plated in an optional step 880 to form magnetic core layer 1065. A second passivation layer 1070 is then deposited in a step 885. Contact pads 1075 are masked and etched in a step 890 and solder bumps (not shown) formed in a step 895. In another embodiment, a layer of metal is deposited and then patterned to form cross over metals (not shown) before solder bumps are formed in step 895. Following the process 800, an IC chip may be attached to the inductor substrate by a standard bonding process or by a flip-chip bonding process and the whole inductor substrate diced into individual packages.
[0037] In an alternative embodiment of the invention, a peripheral magnetic via
1700 to the magnetic core layer 1010 is formed following the step 875 in which a passivation layer 1710 (FIG. 17) is formed over the planar spiral inductor 1055. Magnetic core material is then deposited as a blanket layer and patterned or plated in the step 880 (FIG. 18) to form magnetic core layer 1065. Magnetic core material in via 1700 connects the magnetic core layer 1065 with the magnetic core layer 1010 to maximize the inductance of the spiral inductor 1055. An inductor substrate 1900 and mounted power IC flip chip 1910 is shown in FIG. 19. Maximum inductance is achieved by contact between the magnetic core layers but a separation on the order of a few microns is acceptable.
[0038] The chip scale power converter having an inductor substrate of the invention combines the inductor in the package to improve efficiency of assembly. The inventive package does not integrate the inductor directly with the more costly power IC. By flipping the power IC onto the inductor substrate, optimized interconnection between the power IC and the inductor is provided to minimize parasitics, improve performance and achieve high reliability.
[0039] The chip scale power converter having an inductor substrate according to the invention is particularly suited for high frequency (>5 MHz) applications requiring lower inductance values. It is also suited for low current applications to leverage the planar spiral inductor. The inductor substrate of the invention is simple to fabricate at a low cost and maximizes the inductance while minimizing cost and space. [0040] It is apparent that the above embodiments may be altered in many ways without departing from the scope of the invention. For example, the inductor substrate may be formed without the magnetic core materials and optional components including resistors and capacitors may be formed in the substrate. Additionally, high power MOSFET devices may be incorporated in the substrate. Further, various aspects of a particular embodiment may contain patentably subject matter without regard to other aspects of the same embodiment. Still further, various aspects of different embodiments can be combined together. Accordingly, the scope of the invention should be determined by the following claims and their legal equivalents.

Claims

What is claimed is:
1. A power converter package comprising: an inductor substrate; and a power integrated circuit bonded onto the inductor substrate.
2. The converter according to claim 1 , wherein the inductor substrate comprises a planar spiral inductor formed thereon.
3. The power converter according to claim 2, wherein the planar spiral inductor has a thickness greater than 17 microns.
4. The power converter according to claim 2, further comprising a magnetic core layer disposed under the planar spiral inductor.
5. The power converter according to claim 2, further comprising a magnetic core layer disposed over the planar spiral inductor.
6. The power converter according to claim 2, further comprising a first magnetic core layer disposed under the planar spiral inductor and a second magnetic core layer disposed over the planar spiral inductor, the first and second magnetic core layers being coupled by means of a magnetic core material via.
7. The power converter according to claim 2, wherein the power integrated circuit comprises a plurality of contacts coupled to a plurality of peripheral contacts on the inductor substrate by means of a cross over metal layer.
8. The power converter according to claim 2, wherein the power integrated circuit is flip chip bonded onto the inductor substrate.
9. A chip scale inductor substrate comprising: a high resistivity substrate; and a planar spiral inductor formed on the substrate.
10. The chip scale inductor substrate according to claim 9, wherein the planar spiral inductor has a thickness greater than 17 microns.
11. The chip scale inductor substrate according to claim 9, further comprising a plurality of magnetic core layers sandwiched by dielectric layers disposed under the planar spiral inductor.
12. The chip scale inductor substrate according to claim 11 , further comprising a magnetic core layer disposed over the planar spiral inductor.
13. The chip scale inductor substrate according to claim 9, further comprising a first magnetic core layer disposed under the planar spiral inductor and a second magnetic core layer disposed over the planar spiral inductor, the first and second magnetic core layers being coupled by means of a magnetic core material via.
14. The chip scale inductor substrate according to claim 9, wherein the inductor substrate comprises a plurality of contacts in a center area of the inductor substrate coupled to a plurality of peripheral contacts on the inductor substrate by means of a cross over metal layer.
15. The chip scale inductor substrate according to claim 9, further comprising a low- K dielectric material disposed under the planar spiral inductor to reduce parasitic capacitance.
16. A method of fabricating a chip scale power converter package comprising the steps of: providing a substrate; fabricating a plurality of planar spiral inductors on the substrate to form a plurality of inductor substrates; bonding an integrated circuit onto each inductor substrate; and dicing the plurality of inductor substrates.
17. The method according to claim 16, further comprising forming a first oxide layer on the high resistivity substrate before the fabrication step.
18. The method according to claim 17, further comprising depositing a first magnetic core material layer on the oxide layer before the fabrication step.
19. The method according to claim 18, further comprising depositing a second oxide layer on the magnetic core material layer before the fabrication step.
20. The method according to claim 19, further comprising depositing a cross over metal layer on the second oxide layer before the fabrication step.
21. The method according to claim 20, further comprising depositing a third oxide layer over the cross over metal layer before the fabrication step.
22. The method according to claim 21 , further comprising depositing a dielectic material over the third oxide layer before the fabrication step.
23. The method according to claim 22, further comprising forming vias to the cross over metal layer before the fabrication step.
24. The method according to claim 23, further comprising etching exposed portions of the third oxide layer before the fabrication step.
25. The method according to claim 24, further comprising depositing a barrier metal layer on the dielectic material and exposed portions of the cross over metal layer before the fabrication step.
26. The method according to claim 25, further comprising depositing a seed layer on the barrier metal layer before the fabrication step.
27. The method according to claim 26, wherein the fabrication step comprises plating the plurality of planar spiral inductors.
28. The method according to claim 27, wherein the fabrication step comprises patterning the plurality of planar spiral inductors.
29. The method according to claim 28, further comprising etching exposed portions of the barrier metal and seed layers.
30. The method according to claim 29, further comprising depositing a first passivation layer.
31. The method according to claim 30, further comprising forming a peripheral via reaching the first magnetic core material layer.
32. The method according to claim 31, further comprising depositing a second magnetic core material layer.
33. The method according to claim 32, further comprising depositing a second passivation layer.
34. The method according to claim 33, further comprising forming contact pads in the vias.
35. The method according to claim 34, further comprising forming solder balls on the contact pads.
PCT/US2008/004032 2007-03-27 2008-03-27 Chip scale power converter package having an inductor substrate WO2008118489A1 (en)

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